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authorMichael Neuling2013-03-04 13:45:50 -0600
committerBenjamin Herrenschmidt2013-03-04 23:56:29 -0600
commit57d231678ace658b3a73a0d144cfebbd4257bc0e (patch)
tree6b644ca8c160e8e3415718545ae57eeaca620627
parent8170a83f15eeca9a84ff895f1a89b58918425a3f (diff)
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powerpc: Fix setting FSCR for HV=0 and on secondary CPUs
Currently we only set the FSCR (Facility Status and Control Register) when HV=1 but this feature is available when HV=0 also. This patch sets FSCR when HV=0. Also, we currently only set the FSCR on the master CPU. This patch also sets the FSCR on secondary CPUs. Signed-off-by: Michael Neuling <mikey@neuling.org> cc: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-rw-r--r--arch/powerpc/kernel/cpu_setup_power.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index d29facbf9a2..bb2d2034d61 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -48,6 +48,7 @@ _GLOBAL(__restore_cpu_power7)
48 48
49_GLOBAL(__setup_cpu_power8) 49_GLOBAL(__setup_cpu_power8)
50 mflr r11 50 mflr r11
51 bl __init_FSCR
51 bl __init_hvmode_206 52 bl __init_hvmode_206
52 mtlr r11 53 mtlr r11
53 beqlr 54 beqlr
@@ -56,13 +57,13 @@ _GLOBAL(__setup_cpu_power8)
56 mfspr r3,SPRN_LPCR 57 mfspr r3,SPRN_LPCR
57 oris r3, r3, LPCR_AIL_3@h 58 oris r3, r3, LPCR_AIL_3@h
58 bl __init_LPCR 59 bl __init_LPCR
59 bl __init_FSCR
60 bl __init_TLB 60 bl __init_TLB
61 mtlr r11 61 mtlr r11
62 blr 62 blr
63 63
64_GLOBAL(__restore_cpu_power8) 64_GLOBAL(__restore_cpu_power8)
65 mflr r11 65 mflr r11
66 bl __init_FSCR
66 mfmsr r3 67 mfmsr r3
67 rldicl. r0,r3,4,63 68 rldicl. r0,r3,4,63
68 beqlr 69 beqlr