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authorPete Delaney2013-01-04 18:57:16 -0600
committerChris Zankel2013-02-23 21:12:52 -0600
commitd0b73b488c55df905ea8faaad079f8535629ed26 (patch)
tree8804f87c23da3d6540bc1aab7f4d1062f818e254 /arch/xtensa
parent2a02bc166dd1c7dae71bd3115fb10ec0c351a31f (diff)
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xtensa: Add config files for Diamond 233L - Rev C processor variant
The Diamond 233L processor is a pre-configured Xtensa processor tailored for Linux application. Signed-off-by: Pete Delaney <piet@tensilica.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/Kconfig6
-rw-r--r--arch/xtensa/Makefile1
-rw-r--r--arch/xtensa/variants/dc233c/include/variant/core.h475
-rw-r--r--arch/xtensa/variants/dc233c/include/variant/tie-asm.h193
-rw-r--r--arch/xtensa/variants/dc233c/include/variant/tie.h150
5 files changed, 825 insertions, 0 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 5aab1acabf1..b08d59e39a4 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -71,6 +71,12 @@ config XTENSA_VARIANT_DC232B
71 help 71 help
72 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 72 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
73 73
74config XTENSA_VARIANT_DC233C
75 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
76 select MMU
77 help
78 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
79
74config XTENSA_VARIANT_S6000 80config XTENSA_VARIANT_S6000
75 bool "s6000 - Stretch software configurable processor" 81 bool "s6000 - Stretch software configurable processor"
76 select VARIANT_IRQ_SWITCH 82 select VARIANT_IRQ_SWITCH
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 48c1a5b3bd3..afec8f000c4 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -15,6 +15,7 @@
15 15
16variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf 16variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
17variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b 17variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b
18variant-$(CONFIG_XTENSA_VARIANT_DC233C) := dc233c
18variant-$(CONFIG_XTENSA_VARIANT_S6000) := s6000 19variant-$(CONFIG_XTENSA_VARIANT_S6000) := s6000
19variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom 20variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
20 21
diff --git a/arch/xtensa/variants/dc233c/include/variant/core.h b/arch/xtensa/variants/dc233c/include/variant/core.h
new file mode 100644
index 00000000000..3a2e53b9493
--- /dev/null
+++ b/arch/xtensa/variants/dc233c/include/variant/core.h
@@ -0,0 +1,475 @@
1/*
2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
4 *
5 * See <xtensa/config/core.h>, which includes this file, for more details.
6 */
7
8/* Xtensa processor core configuration information.
9
10 Copyright (c) 1999-2010 Tensilica Inc.
11
12 Permission is hereby granted, free of charge, to any person obtaining
13 a copy of this software and associated documentation files (the
14 "Software"), to deal in the Software without restriction, including
15 without limitation the rights to use, copy, modify, merge, publish,
16 distribute, sublicense, and/or sell copies of the Software, and to
17 permit persons to whom the Software is furnished to do so, subject to
18 the following conditions:
19
20 The above copyright notice and this permission notice shall be included
21 in all copies or substantial portions of the Software.
22
23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
30
31#ifndef _XTENSA_CORE_CONFIGURATION_H
32#define _XTENSA_CORE_CONFIGURATION_H
33
34
35/****************************************************************************
36 Parameters Useful for Any Code, USER or PRIVILEGED
37 ****************************************************************************/
38
39/*
40 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
41 * configured, and a value of 0 otherwise. These macros are always defined.
42 */
43
44
45/*----------------------------------------------------------------------
46 ISA
47 ----------------------------------------------------------------------*/
48
49#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
50#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
51#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
52#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
53#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
54#define XCHAL_HAVE_DEBUG 1 /* debug option */
55#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
58#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
59#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
60#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
61#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
62#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
63#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
64#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
65#define XCHAL_HAVE_L32R 1 /* L32R instruction */
66#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
67#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
68#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
69#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
70#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
71#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
72#define XCHAL_HAVE_ABS 1 /* ABS instruction */
73/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
74/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
75#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
76#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
77#define XCHAL_HAVE_SPECULATION 0 /* speculation */
78#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
79#define XCHAL_NUM_CONTEXTS 1 /* */
80#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
81#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
82#define XCHAL_HAVE_PRID 1 /* processor ID register */
83#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
84#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
85#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
86#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
87#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
88#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
89#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
90#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
91#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
92#define XCHAL_HAVE_FP 0 /* floating point pkg */
93#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
94#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
95#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
96#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
97#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
98#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
99#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
100#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
101#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
102#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
103#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
104#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
105#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
106#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
107#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
108#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
109#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
110
111
112/*----------------------------------------------------------------------
113 MISC
114 ----------------------------------------------------------------------*/
115
116#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
117#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
118#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
119/* In T1050, applies to selected core load and store instructions (see ISA): */
120#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
121#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
122#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
123#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
124
125#define XCHAL_SW_VERSION 900001 /* sw version of this header */
126
127#define XCHAL_CORE_ID "dc233c" /* alphanum core name
128 (CoreID) set in the Xtensa
129 Processor Generator */
130
131#define XCHAL_CORE_DESCRIPTION "dc233c"
132#define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */
133
134/*
135 * These definitions describe the hardware targeted by this software.
136 */
137#define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/
138#define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/
139#define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */
140#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */
141#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
142#define XCHAL_HW_VERSION 240001 /* major*100+minor */
143#define XCHAL_HW_REL_LX4 1
144#define XCHAL_HW_REL_LX4_0 1
145#define XCHAL_HW_REL_LX4_0_1 1
146#define XCHAL_HW_CONFIGID_RELIABLE 1
147/* If software targets a *range* of hardware versions, these are the bounds: */
148#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */
149#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
150#define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */
151#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */
152#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
153#define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */
154
155
156/*----------------------------------------------------------------------
157 CACHE
158 ----------------------------------------------------------------------*/
159
160#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
161#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
162#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
163#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
164
165#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
166#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
167
168#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
169#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
170
171#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
172
173
174
175
176/****************************************************************************
177 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
178 ****************************************************************************/
179
180
181#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
182
183/*----------------------------------------------------------------------
184 CACHE
185 ----------------------------------------------------------------------*/
186
187#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
188
189/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
190
191/* Number of cache sets in log2(lines per way): */
192#define XCHAL_ICACHE_SETWIDTH 7
193#define XCHAL_DCACHE_SETWIDTH 7
194
195/* Cache set associativity (number of ways): */
196#define XCHAL_ICACHE_WAYS 4
197#define XCHAL_DCACHE_WAYS 4
198
199/* Cache features: */
200#define XCHAL_ICACHE_LINE_LOCKABLE 1
201#define XCHAL_DCACHE_LINE_LOCKABLE 1
202#define XCHAL_ICACHE_ECC_PARITY 0
203#define XCHAL_DCACHE_ECC_PARITY 0
204
205/* Cache access size in bytes (affects operation of SICW instruction): */
206#define XCHAL_ICACHE_ACCESS_SIZE 4
207#define XCHAL_DCACHE_ACCESS_SIZE 4
208
209/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
210#define XCHAL_CA_BITS 4
211
212
213/*----------------------------------------------------------------------
214 INTERNAL I/D RAM/ROMs and XLMI
215 ----------------------------------------------------------------------*/
216
217#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
218#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
219#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
220#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
222#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
223
224#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
225
226
227/*----------------------------------------------------------------------
228 INTERRUPTS and TIMERS
229 ----------------------------------------------------------------------*/
230
231#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
232#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
233#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
234#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
235#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
236#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
237#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
238#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
239#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
240 (not including level zero) */
241#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
242 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
243
244/* Masks of interrupts at each interrupt level: */
245#define XCHAL_INTLEVEL1_MASK 0x001F80FF
246#define XCHAL_INTLEVEL2_MASK 0x00000100
247#define XCHAL_INTLEVEL3_MASK 0x00200E00
248#define XCHAL_INTLEVEL4_MASK 0x00001000
249#define XCHAL_INTLEVEL5_MASK 0x00002000
250#define XCHAL_INTLEVEL6_MASK 0x00000000
251#define XCHAL_INTLEVEL7_MASK 0x00004000
252
253/* Masks of interrupts at each range 1..n of interrupt levels: */
254#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
255#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
256#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
257#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
258#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
259#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
260#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
261
262/* Level of each interrupt: */
263#define XCHAL_INT0_LEVEL 1
264#define XCHAL_INT1_LEVEL 1
265#define XCHAL_INT2_LEVEL 1
266#define XCHAL_INT3_LEVEL 1
267#define XCHAL_INT4_LEVEL 1
268#define XCHAL_INT5_LEVEL 1
269#define XCHAL_INT6_LEVEL 1
270#define XCHAL_INT7_LEVEL 1
271#define XCHAL_INT8_LEVEL 2
272#define XCHAL_INT9_LEVEL 3
273#define XCHAL_INT10_LEVEL 3
274#define XCHAL_INT11_LEVEL 3
275#define XCHAL_INT12_LEVEL 4
276#define XCHAL_INT13_LEVEL 5
277#define XCHAL_INT14_LEVEL 7
278#define XCHAL_INT15_LEVEL 1
279#define XCHAL_INT16_LEVEL 1
280#define XCHAL_INT17_LEVEL 1
281#define XCHAL_INT18_LEVEL 1
282#define XCHAL_INT19_LEVEL 1
283#define XCHAL_INT20_LEVEL 1
284#define XCHAL_INT21_LEVEL 3
285#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
286#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
287#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
288 EXCSAVE/EPS/EPC_n, RFI n) */
289
290/* Type of each interrupt: */
291#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
292#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
293#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
294#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
295#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
296#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
297#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
298#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
299#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
300#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
301#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
302#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
303#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
304#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
305#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
306#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
307#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
308#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
309#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
310#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
311#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
312#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
313
314/* Masks of interrupts for each type of interrupt: */
315#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
316#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
317#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
318#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
319#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
320#define XCHAL_INTTYPE_MASK_NMI 0x00004000
321#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
322
323/* Interrupt numbers assigned to specific interrupt sources: */
324#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
325#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
326#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
327#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
328#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
329
330/* Interrupt numbers for levels at which only one interrupt is configured: */
331#define XCHAL_INTLEVEL2_NUM 8
332#define XCHAL_INTLEVEL4_NUM 12
333#define XCHAL_INTLEVEL5_NUM 13
334#define XCHAL_INTLEVEL7_NUM 14
335/* (There are many interrupts each at level(s) 1, 3.) */
336
337
338/*
339 * External interrupt vectors/levels.
340 * These macros describe how Xtensa processor interrupt numbers
341 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
342 * map to external BInterrupt<n> pins, for those interrupts
343 * configured as external (level-triggered, edge-triggered, or NMI).
344 * See the Xtensa processor databook for more details.
345 */
346
347/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
348#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
349#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
350#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
351#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
352#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
353#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
354#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
355#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
356#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
357#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
358#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
359#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
360#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
361#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
362#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
363#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
364#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
365
366
367/*----------------------------------------------------------------------
368 EXCEPTIONS and VECTORS
369 ----------------------------------------------------------------------*/
370
371#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
372 number: 1 == XEA1 (old)
373 2 == XEA2 (new)
374 0 == XEAX (extern) or TX */
375#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
376#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
377#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
378#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
379#define XCHAL_HAVE_HALT 0 /* halt architecture option */
380#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
381#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
382#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
383#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
384#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
385#define XCHAL_VECBASE_RESET_PADDR 0x00002000
386#define XCHAL_RESET_VECBASE_OVERLAP 0
387
388#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
389#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
390#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
391#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
392#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
393#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
394#define XCHAL_USER_VECOFS 0x00000340
395#define XCHAL_USER_VECTOR_VADDR 0x00002340
396#define XCHAL_USER_VECTOR_PADDR 0x00002340
397#define XCHAL_KERNEL_VECOFS 0x00000300
398#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
399#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
400#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
401#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
402#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
403#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
404#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
405#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
406#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
407#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
408#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
409#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
410#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
411#define XCHAL_INTLEVEL2_VECOFS 0x00000180
412#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
413#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
414#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
415#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
416#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
417#define XCHAL_INTLEVEL4_VECOFS 0x00000200
418#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
419#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
420#define XCHAL_INTLEVEL5_VECOFS 0x00000240
421#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
422#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
423#define XCHAL_INTLEVEL6_VECOFS 0x00000280
424#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
425#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
426#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
427#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
428#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
429#define XCHAL_NMI_VECOFS 0x000002C0
430#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
431#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
432#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
433#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
434#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
435
436
437/*----------------------------------------------------------------------
438 DEBUG
439 ----------------------------------------------------------------------*/
440
441#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
442#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
443#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
444#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
445
446
447/*----------------------------------------------------------------------
448 MMU
449 ----------------------------------------------------------------------*/
450
451/* See core-matmap.h header file for more details. */
452
453#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
454#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
455#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
456#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
457#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
458#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
459#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
460#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
461 [autorefill] and protection)
462 usable for an MMU-based OS */
463/* If none of the above last 4 are set, it's a custom TLB configuration. */
464#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
465#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
466
467#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
468#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
469#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
470
471#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
472
473
474#endif /* _XTENSA_CORE_CONFIGURATION_H */
475
diff --git a/arch/xtensa/variants/dc233c/include/variant/tie-asm.h b/arch/xtensa/variants/dc233c/include/variant/tie-asm.h
new file mode 100644
index 00000000000..5dbd981ea42
--- /dev/null
+++ b/arch/xtensa/variants/dc233c/include/variant/tie-asm.h
@@ -0,0 +1,193 @@
1/*
2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file contains assembly-language definitions (assembly
8 macros, etc.) for this specific Xtensa processor's TIE extensions
9 and options. It is customized to this Xtensa processor configuration.
10
11 Copyright (c) 1999-2010 Tensilica Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_ASM_H
33#define _XTENSA_CORE_TIE_ASM_H
34
35/* Selection parameter values for save-area save/restore macros: */
36/* Option vs. TIE: */
37#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
38#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
39#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
40/* Whether used automatically by compiler: */
41#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
42#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
43#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
44/* ABI handling across function calls: */
45#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
47#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
48#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
49/* Misc */
50#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
51#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
52 | ((ccuse) & XTHAL_SAS_ANYCC) \
53 | ((abi) & XTHAL_SAS_ANYABI) )
54
55
56
57 /*
58 * Macro to save all non-coprocessor (extra) custom TIE and optional state
59 * (not including zero-overhead loop registers).
60 * Required parameters:
61 * ptr Save area pointer address register (clobbered)
62 * (register must contain a 4 byte aligned address).
63 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
64 * registers are clobbered, the remaining are unused).
65 * Optional parameters:
66 * continue If macro invoked as part of a larger store sequence, set to 1
67 * if this is not the first in the sequence. Defaults to 0.
68 * ofs Offset from start of larger sequence (from value of first ptr
69 * in sequence) at which to store. Defaults to next available space
70 * (or 0 if <continue> is 0).
71 * select Select what category(ies) of registers to store, as a bitmask
72 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
73 * alloc Select what category(ies) of registers to allocate; if any
74 * category is selected here that is not in <select>, space for
75 * the corresponding registers is skipped without doing any store.
76 */
77 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
78 xchal_sa_start \continue, \ofs
79 // Optional global register used by default by the compiler:
80 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
81 xchal_sa_align \ptr, 0, 1020, 4, 4
82 rur.THREADPTR \at1 // threadptr option
83 s32i \at1, \ptr, .Lxchal_ofs_+0
84 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
85 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
86 xchal_sa_align \ptr, 0, 1020, 4, 4
87 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
88 .endif
89 // Optional caller-saved registers used by default by the compiler:
90 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
91 xchal_sa_align \ptr, 0, 1016, 4, 4
92 rsr \at1, ACCLO // MAC16 option
93 s32i \at1, \ptr, .Lxchal_ofs_+0
94 rsr \at1, ACCHI // MAC16 option
95 s32i \at1, \ptr, .Lxchal_ofs_+4
96 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
97 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
98 xchal_sa_align \ptr, 0, 1016, 4, 4
99 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
100 .endif
101 // Optional caller-saved registers not used by default by the compiler:
102 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
103 xchal_sa_align \ptr, 0, 1004, 4, 4
104 rsr \at1, M0 // MAC16 option
105 s32i \at1, \ptr, .Lxchal_ofs_+0
106 rsr \at1, M1 // MAC16 option
107 s32i \at1, \ptr, .Lxchal_ofs_+4
108 rsr \at1, M2 // MAC16 option
109 s32i \at1, \ptr, .Lxchal_ofs_+8
110 rsr \at1, M3 // MAC16 option
111 s32i \at1, \ptr, .Lxchal_ofs_+12
112 rsr \at1, SCOMPARE1 // conditional store option
113 s32i \at1, \ptr, .Lxchal_ofs_+16
114 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
115 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
116 xchal_sa_align \ptr, 0, 1004, 4, 4
117 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
118 .endif
119 .endm // xchal_ncp_store
120
121 /*
122 * Macro to restore all non-coprocessor (extra) custom TIE and optional state
123 * (not including zero-overhead loop registers).
124 * Required parameters:
125 * ptr Save area pointer address register (clobbered)
126 * (register must contain a 4 byte aligned address).
127 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
128 * registers are clobbered, the remaining are unused).
129 * Optional parameters:
130 * continue If macro invoked as part of a larger load sequence, set to 1
131 * if this is not the first in the sequence. Defaults to 0.
132 * ofs Offset from start of larger sequence (from value of first ptr
133 * in sequence) at which to load. Defaults to next available space
134 * (or 0 if <continue> is 0).
135 * select Select what category(ies) of registers to load, as a bitmask
136 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
137 * alloc Select what category(ies) of registers to allocate; if any
138 * category is selected here that is not in <select>, space for
139 * the corresponding registers is skipped without doing any load.
140 */
141 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
142 xchal_sa_start \continue, \ofs
143 // Optional global register used by default by the compiler:
144 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
145 xchal_sa_align \ptr, 0, 1020, 4, 4
146 l32i \at1, \ptr, .Lxchal_ofs_+0
147 wur.THREADPTR \at1 // threadptr option
148 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
149 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
150 xchal_sa_align \ptr, 0, 1020, 4, 4
151 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
152 .endif
153 // Optional caller-saved registers used by default by the compiler:
154 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
155 xchal_sa_align \ptr, 0, 1016, 4, 4
156 l32i \at1, \ptr, .Lxchal_ofs_+0
157 wsr \at1, ACCLO // MAC16 option
158 l32i \at1, \ptr, .Lxchal_ofs_+4
159 wsr \at1, ACCHI // MAC16 option
160 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
161 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
162 xchal_sa_align \ptr, 0, 1016, 4, 4
163 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
164 .endif
165 // Optional caller-saved registers not used by default by the compiler:
166 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
167 xchal_sa_align \ptr, 0, 1004, 4, 4
168 l32i \at1, \ptr, .Lxchal_ofs_+0
169 wsr \at1, M0 // MAC16 option
170 l32i \at1, \ptr, .Lxchal_ofs_+4
171 wsr \at1, M1 // MAC16 option
172 l32i \at1, \ptr, .Lxchal_ofs_+8
173 wsr \at1, M2 // MAC16 option
174 l32i \at1, \ptr, .Lxchal_ofs_+12
175 wsr \at1, M3 // MAC16 option
176 l32i \at1, \ptr, .Lxchal_ofs_+16
177 wsr \at1, SCOMPARE1 // conditional store option
178 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
179 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
180 xchal_sa_align \ptr, 0, 1004, 4, 4
181 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
182 .endif
183 .endm // xchal_ncp_load
184
185
186#define XCHAL_NCP_NUM_ATMPS 1
187
188
189
190#define XCHAL_SA_NUM_ATMPS 1
191
192#endif /*_XTENSA_CORE_TIE_ASM_H*/
193
diff --git a/arch/xtensa/variants/dc233c/include/variant/tie.h b/arch/xtensa/variants/dc233c/include/variant/tie.h
new file mode 100644
index 00000000000..815e52bc3d0
--- /dev/null
+++ b/arch/xtensa/variants/dc233c/include/variant/tie.h
@@ -0,0 +1,150 @@
1/*
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file describes this specific Xtensa processor's TIE extensions
8 that extend basic Xtensa core functionality. It is customized to this
9 Xtensa processor configuration.
10
11 Copyright (c) 1999-2010 Tensilica Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_H
33#define _XTENSA_CORE_TIE_H
34
35#define XCHAL_CP_NUM 1 /* number of coprocessors */
36#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
38#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
39
40/* Basic parameters of each coprocessor: */
41#define XCHAL_CP7_NAME "XTIOP"
42#define XCHAL_CP7_IDENT XTIOP
43#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
44#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
45#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
46
47/* Filler info for unassigned coprocessors, to simplify arrays etc: */
48#define XCHAL_CP0_SA_SIZE 0
49#define XCHAL_CP0_SA_ALIGN 1
50#define XCHAL_CP1_SA_SIZE 0
51#define XCHAL_CP1_SA_ALIGN 1
52#define XCHAL_CP2_SA_SIZE 0
53#define XCHAL_CP2_SA_ALIGN 1
54#define XCHAL_CP3_SA_SIZE 0
55#define XCHAL_CP3_SA_ALIGN 1
56#define XCHAL_CP4_SA_SIZE 0
57#define XCHAL_CP4_SA_ALIGN 1
58#define XCHAL_CP5_SA_SIZE 0
59#define XCHAL_CP5_SA_ALIGN 1
60#define XCHAL_CP6_SA_SIZE 0
61#define XCHAL_CP6_SA_ALIGN 1
62
63/* Save area for non-coprocessor optional and custom (TIE) state: */
64#define XCHAL_NCP_SA_SIZE 32
65#define XCHAL_NCP_SA_ALIGN 4
66
67/* Total save area for optional and custom state (NCP + CPn): */
68#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
69#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
70
71/*
72 * Detailed contents of save areas.
73 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
74 * before expanding the XCHAL_xxx_SA_LIST() macros.
75 *
76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
77 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
78 *
79 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
80 * ccused = set if used by compiler without special options or code
81 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
82 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
83 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
84 * name = lowercase reg name (no quotes)
85 * galign = group byte alignment (power of 2) (galign >= align)
86 * align = register byte alignment (power of 2)
87 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
88 * (not including any pad bytes required to galign this or next reg)
89 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
90 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
91 * regnum = reg index in regfile, or special/TIE-user reg number
92 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
93 * gapsz = intervening bits, if bitsz bits not stored contiguously
94 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
95 * reset = register reset value (or 0 if undefined at reset)
96 * x = reserved for future use (0 until then)
97 *
98 * To filter out certain registers, e.g. to expand only the non-global
99 * registers used by the compiler, you can do something like this:
100 *
101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
102 * #define SELCC0(p...)
103 * #define SELCC1(abikind,p...) SELAK##abikind(p)
104 * #define SELAK0(p...) REG(p)
105 * #define SELAK1(p...) REG(p)
106 * #define SELAK2(p...)
107 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
108 * ...what you want to expand...
109 */
110
111#define XCHAL_NCP_SA_NUM 8
112#define XCHAL_NCP_SA_LIST(s) \
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
121
122#define XCHAL_CP0_SA_NUM 0
123#define XCHAL_CP0_SA_LIST(s) /* empty */
124
125#define XCHAL_CP1_SA_NUM 0
126#define XCHAL_CP1_SA_LIST(s) /* empty */
127
128#define XCHAL_CP2_SA_NUM 0
129#define XCHAL_CP2_SA_LIST(s) /* empty */
130
131#define XCHAL_CP3_SA_NUM 0
132#define XCHAL_CP3_SA_LIST(s) /* empty */
133
134#define XCHAL_CP4_SA_NUM 0
135#define XCHAL_CP4_SA_LIST(s) /* empty */
136
137#define XCHAL_CP5_SA_NUM 0
138#define XCHAL_CP5_SA_LIST(s) /* empty */
139
140#define XCHAL_CP6_SA_NUM 0
141#define XCHAL_CP6_SA_LIST(s) /* empty */
142
143#define XCHAL_CP7_SA_NUM 0
144#define XCHAL_CP7_SA_LIST(s) /* empty */
145
146/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
147#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
148
149#endif /*_XTENSA_CORE_TIE_H*/
150