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authorJon Medhurst2013-01-15 05:03:10 -0600
committerJon Medhurst2013-01-15 05:03:10 -0600
commit27eed928fcf0adc67fb2b0fd41bb6869d62d941f (patch)
tree2d988697dacf8c92d0621837f56b723a55015f8d
parent3c295d4955ed76ce1fee385305153c1334a9b890 (diff)
parent06ebd1eab0a782377611efee820bb57f09692cbf (diff)
downloadarm-ds5-gator-27eed928fcf0adc67fb2b0fd41bb6869d62d941f.tar.gz
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gator-daemon: Add files missing from original commit of DS-5.13
Diffstat
-rw-r--r--daemon/escape.c63
-rw-r--r--daemon/events-Cortex-A53.xml171
-rw-r--r--daemon/events-Cortex-A57.xml171
3 files changed, 405 insertions, 0 deletions
diff --git a/daemon/escape.c b/daemon/escape.c
new file mode 100644
index 0000000..c0f47f1
--- /dev/null
+++ b/daemon/escape.c
@@ -0,0 +1,63 @@
1/**
2 * Copyright (C) ARM Limited 2010-2012. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <errno.h>
10#include <stdio.h>
11#include <stdlib.h>
12#include <string.h>
13#include <ctype.h>
14
15static void print_escaped_path(char *path) {
16 if (isdigit(*path)) {
17 printf("__");
18 }
19 for (; *path != '\0'; ++path) {
20 printf("%c", isalnum(*path) ? *path : '_');
21 }
22}
23
24int main(int argc, char *argv[]) {
25 int i;
26 char *path;
27 FILE *in = NULL;
28 int ch;
29 unsigned int len = 0;
30
31 for (i = 1; i < argc && argv[i][0] == '-'; ++i) ;
32 if (i == argc) {
33 fprintf(stderr, "Usage: %s <filename>\n", argv[0]);
34 return EXIT_FAILURE;
35 }
36 path = argv[i];
37
38 errno = 0;
39 if ((in = fopen(path, "r")) == NULL) {
40 fprintf(stderr, "Unable to open '%s': %s\n", path, strerror(errno));
41 return EXIT_FAILURE;
42 }
43
44 printf("static const unsigned char ");
45 print_escaped_path(path);
46 printf("[] = {");
47 for (; (ch = fgetc(in)) != EOF; ++len) {
48 if (len != 0) {
49 printf(",");
50 }
51 if (len % 12 == 0) {
52 printf("\n ");
53 }
54 printf(" 0x%.2x", ch);
55 }
56 printf("\n};\nstatic const unsigned int ");
57 print_escaped_path(path);
58 printf("_len = %i;\n", len);
59
60 fclose(in);
61
62 return EXIT_SUCCESS;
63}
diff --git a/daemon/events-Cortex-A53.xml b/daemon/events-Cortex-A53.xml
new file mode 100644
index 0000000..3fa9c66
--- /dev/null
+++ b/daemon/events-Cortex-A53.xml
@@ -0,0 +1,171 @@
1 <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
2 <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <!-- 0x11 CPU_CYCLES - Cycle -->
4 <event counter="ARM_Cortex-A53_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
5 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
9 <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
10 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
11 <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
14 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
18 <event event="0x08" title="-" name="INST_RETIRED" description="Instruction architecturally executed"/>
19 <!-- 0x09 EXC_TAKEN - Exception taken -->
20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
22 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
23 <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
24 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
25 <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
26 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
29 <!-- 0x13 MEM_ACCESS - Data memory access -->
30 <event event="0x13" title="-" name="MEM_ACCESS" description="Data memory access"/>
31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
32 <event event="0x14" title="-" name="L1I_CACHE" description="Level 1 instruction cache access"/>
33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
34 <event event="0x15" title="-" name="L1D_CACHE_WB" description="Level 1 data cache Write-Back"/>
35 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
36 <event event="0x16" title="-" name="L2D_CACHE" description="Level 2 data cache access"/>
37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
38 <event event="0x17" title="-" name="L2D_CACHE_REFILL" description="Level 2 data cache refill"/>
39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
40 <event event="0x18" title="-" name="L2D_CACHE_WB" description="Level 2 data cache Write-Back"/>
41 <!-- 0x19 BUS_ACCESS - Bus access -->
42 <event event="0x19" title="-" name="BUS_ACCESS" description="Bus access"/>
43 <!-- 0x1A MEMORY_ERROR - Local memory error -->
44 <event event="0x1A" title="-" name="MEMORY_ERROR" description="Local memory error"/>
45 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
46 <event event="0x1B" title="-" name="INST_SPEC" description="Operation speculatively executed"/>
47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
48 <event event="0x1C" title="-" name="TTBR_WRITE_RETIRED" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
49 <!-- 0x1D BUS_CYCLES - Bus cycle -->
50 <event event="0x1D" title="-" name="BUS_CYCLES" description="Bus cycle"/>
51 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
52 <event event="0x1E" title="-" name="CHAIN" description="Odd performance counter chain mode"/>
53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
54 <event event="0x40" title="-" name="L1D_CACHE_LD" description="Level 1 data cache access - Read"/>
55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
56 <event event="0x41" title="-" name="L1D_CACHE_ST" description="Level 1 data cache access - Write"/>
57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
58 <event event="0x42" title="-" name="L1D_CACHE_REFILL_LD" description="Level 1 data cache refill - Read"/>
59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
60 <event event="0x43" title="-" name="L1D_CACHE_REFILL_ST" description="Level 1 data cache refill - Write"/>
61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
62 <event event="0x46" title="-" name="L1D_CACHE_WB_VICTIM" description="Level 1 data cache Write-back - Victim"/>
63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
64 <event event="0x47" title="-" name="L1D_CACHE_WB_CLEAN" description="Level 1 data cache Write-back - Cleaning and coherency"/>
65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
66 <event event="0x48" title="-" name="L1D_CACHE_INVAL" description="Level 1 data cache invalidate"/>
67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
68 <event event="0x4C" title="-" name="L1D_TLB_REFILL_LD" description="Level 1 data TLB refill - Read"/>
69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
70 <event event="0x4D" title="-" name="L1D_TLB_REFILL_ST" description="Level 1 data TLB refill - Write"/>
71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
72 <event event="0x50" title="-" name="L2D_CACHE_LD" description="Level 2 data cache access - Read"/>
73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
74 <event event="0x51" title="-" name="L2D_CACHE_ST" description="Level 2 data cache access - Write"/>
75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
76 <event event="0x52" title="-" name="L2D_CACHE_REFILL_LD" description="Level 2 data cache refill - Read"/>
77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
78 <event event="0x53" title="-" name="L2D_CACHE_REFILL_ST" description="Level 2 data cache refill - Write"/>
79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
80 <event event="0x56" title="-" name="L2D_CACHE_WB_VICTIM" description="Level 2 data cache Write-back - Victim"/>
81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
82 <event event="0x57" title="-" name="L2D_CACHE_WB_CLEAN" description="Level 2 data cache Write-back - Cleaning and coherency"/>
83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
84 <event event="0x58" title="-" name="L2D_CACHE_INVAL" description="Level 2 data cache invalidate"/>
85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
86 <event event="0x60" title="-" name="BUS_ACCESS_LD" description="Bus access - Read"/>
87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
88 <event event="0x61" title="-" name="BUS_ACCESS_ST" description="Bus access - Write"/>
89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
90 <event event="0x62" title="-" name="BUS_ACCESS_SHARED" description="Bus access - Normal"/>
91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
92 <event event="0x63" title="-" name="BUS_ACCESS_NOT_SHARED" description="Bus access - Not normal"/>
93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
94 <event event="0x64" title="-" name="BUS_ACCESS_NORMAL" description="Bus access - Normal"/>
95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
96 <event event="0x65" title="-" name="BUS_ACCESS_PERIPH" description="Bus access - Peripheral"/>
97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
98 <event event="0x66" title="-" name="MEM_ACCESS_LD" description="Data memory access - Read"/>
99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
100 <event event="0x67" title="-" name="MEM_ACCESS_ST" description="Data memory access - Write"/>
101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
102 <event event="0x68" title="-" name="UNALIGNED_LD_SPEC" description="Unaligned access - Read"/>
103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
104 <event event="0x69" title="-" name="UNALIGNED_ST_SPEC" description="Unaligned access - Write"/>
105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
106 <event event="0x6A" title="-" name="UNALIGNED_LDST_SPEC" description="Unaligned access"/>
107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
108 <event event="0x6C" title="-" name="LDREX_SPEC" description="Exclusive operation speculatively executed - LDREX"/>
109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
110 <event event="0x6D" title="-" name="STREX_PASS_SPEC" description="Exclusive instruction speculatively executed - STREX pass"/>
111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
112 <event event="0x6E" title="-" name="STREX_FAIL_SPEC" description="Exclusive operation speculatively executed - STREX fail"/>
113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
114 <event event="0x70" title="-" name="LD_SPEC" description="Operation speculatively executed - Load"/>
115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
116 <event event="0x71" title="-" name="ST_SPEC" description="Operation speculatively executed - Store"/>
117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
118 <event event="0x72" title="-" name="LDST_SPEC" description="Operation speculatively executed - Load or store"/>
119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
120 <event event="0x73" title="-" name="DP_SPEC" description="Operation speculatively executed - Integer data processing"/>
121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
122 <event event="0x74" title="-" name="ASE_SPEC" description="Operation speculatively executed - Advanced SIMD"/>
123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
124 <event event="0x75" title="-" name="VFP_SPEC" description="Operation speculatively executed - VFP"/>
125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
126 <event event="0x76" title="-" name="PC_WRITE_SPEC" description="Operation speculatively executed - Software change of the PC"/>
127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
128 <event event="0x77" title="-" name="CRYPTO_SPEC" description="Operation speculatively executed, crypto data processing"/>
129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
130 <event event="0x78" title="-" name="BR_IMMED_SPEC" description="Branch speculatively executed - Immediate branch"/>
131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
132 <event event="0x79" title="-" name="BR_RETURN_SPEC" description="Branch speculatively executed - Procedure return"/>
133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
134 <event event="0x7A" title="-" name="BR_INDIRECT_SPEC" description="Branch speculatively executed - Indirect branch"/>
135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
136 <event event="0x7C" title="-" name="ISB_SPEC" description="Barrier speculatively executed - ISB"/>
137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
138 <event event="0x7D" title="-" name="DSB_SPEC" description="Barrier speculatively executed - DSB"/>
139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
140 <event event="0x7E" title="-" name="DMB_SPEC" description="Barrier speculatively executed - DMB"/>
141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
142 <event event="0x81" title="-" name="EXC_UNDEF" description="Exception taken, other synchronous"/>
143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
144 <event event="0x82" title="-" name="EXC_SVC" description="Exception taken, Supervisor Call"/>
145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
146 <event event="0x83" title="-" name="EXC_PABORT" description="Exception taken, Instruction Abort"/>
147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
148 <event event="0x84" title="-" name="EXC_DABORT" description="Exception taken, Data Abort or SError"/>
149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
150 <event event="0x86" title="-" name="EXC_IRQ" description="Exception taken, IRQ"/>
151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
152 <event event="0x87" title="-" name="EXC_FIQ" description="Exception taken, FIQ"/>
153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
154 <event event="0x88" title="-" name="EXC_SMC" description="Exception taken, Secure Monitor Call"/>
155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
156 <event event="0x8A" title="-" name="EXC_HVC" description="Exception taken, Hypervisor Call"/>
157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
158 <event event="0x8B" title="-" name="EXC_TRAP_PABORT" description="Exception taken, Instruction Abort not taken locally"/>
159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
160 <event event="0x8C" title="-" name="EXC_TRAP_DABORT" description="Exception taken, Data Abort or SError not taken locally"/>
161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken – Other traps not taken locally -->
162 <event event="0x8D" title="-" name="EXC_TRAP_OTHER" description="Exception taken – Other traps not taken locally"/>
163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
164 <event event="0x8E" title="-" name="EXC_TRAP_IRQ" description="Exception taken, IRQ not taken locally"/>
165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
166 <event event="0x8F" title="-" name="EXC_TRAP_FIQ" description="Exception taken, FIQ not taken locally"/>
167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed – Load Acquire -->
168 <event event="0x90" title="-" name="RC_LD_SPEC" description="Release consistency instruction speculatively executed – Load Acquire"/>
169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed – Store Release -->
170 <event event="0x91" title="-" name="RC_ST_SPEC" description="Release consistency instruction speculatively executed – Store Release"/>
171 </category>
diff --git a/daemon/events-Cortex-A57.xml b/daemon/events-Cortex-A57.xml
new file mode 100644
index 0000000..5db6dc2
--- /dev/null
+++ b/daemon/events-Cortex-A57.xml
@@ -0,0 +1,171 @@
1 <counter_set name="ARM_Cortex-A57_cnt" count="6"/>
2 <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <!-- 0x11 CPU_CYCLES - Cycle -->
4 <event counter="ARM_Cortex-A57_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
5 <!-- 0x00 SW_INCR - Instruction architecturally executed number (condition check pass) - Software increment -->
6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
9 <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
10 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
11 <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
14 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
18 <event event="0x08" title="-" name="INST_RETIRED" description="Instruction architecturally executed"/>
19 <!-- 0x09 EXC_TAKEN - Exception taken -->
20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
22 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
23 <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
24 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
25 <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
26 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
29 <!-- 0x13 MEM_ACCESS - Data memory access -->
30 <event event="0x13" title="-" name="MEM_ACCESS" description="Data memory access"/>
31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
32 <event event="0x14" title="-" name="L1I_CACHE" description="Level 1 instruction cache access"/>
33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
34 <event event="0x15" title="-" name="L1D_CACHE_WB" description="Level 1 data cache Write-Back"/>
35 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
36 <event event="0x16" title="-" name="L2D_CACHE" description="Level 2 data cache access"/>
37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
38 <event event="0x17" title="-" name="L2D_CACHE_REFILL" description="Level 2 data cache refill"/>
39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
40 <event event="0x18" title="-" name="L2D_CACHE_WB" description="Level 2 data cache Write-Back"/>
41 <!-- 0x19 BUS_ACCESS - Bus access -->
42 <event event="0x19" title="-" name="BUS_ACCESS" description="Bus access"/>
43 <!-- 0x1A MEMORY_ERROR - Local memory error -->
44 <event event="0x1A" title="-" name="MEMORY_ERROR" description="Local memory error"/>
45 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
46 <event event="0x1B" title="-" name="INST_SPEC" description="Operation speculatively executed"/>
47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
48 <event event="0x1C" title="-" name="TTBR_WRITE_RETIRED" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
49 <!-- 0x1D BUS_CYCLES - Bus cycle -->
50 <event event="0x1D" title="-" name="BUS_CYCLES" description="Bus cycle"/>
51 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
52 <event event="0x1E" title="-" name="CHAIN" description="Odd performance counter chain mode"/>
53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
54 <event event="0x40" title="-" name="L1D_CACHE_LD" description="Level 1 data cache access - Read"/>
55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
56 <event event="0x41" title="-" name="L1D_CACHE_ST" description="Level 1 data cache access - Write"/>
57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
58 <event event="0x42" title="-" name="L1D_CACHE_REFILL_LD" description="Level 1 data cache refill - Read"/>
59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
60 <event event="0x43" title="-" name="L1D_CACHE_REFILL_ST" description="Level 1 data cache refill - Write"/>
61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
62 <event event="0x46" title="-" name="L1D_CACHE_WB_VICTIM" description="Level 1 data cache Write-back - Victim"/>
63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
64 <event event="0x47" title="-" name="L1D_CACHE_WB_CLEAN" description="Level 1 data cache Write-back - Cleaning and coherency"/>
65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
66 <event event="0x48" title="-" name="L1D_CACHE_INVAL" description="Level 1 data cache invalidate"/>
67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
68 <event event="0x4C" title="-" name="L1D_TLB_REFILL_LD" description="Level 1 data TLB refill - Read"/>
69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
70 <event event="0x4D" title="-" name="L1D_TLB_REFILL_ST" description="Level 1 data TLB refill - Write"/>
71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
72 <event event="0x50" title="-" name="L2D_CACHE_LD" description="Level 2 data cache access - Read"/>
73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
74 <event event="0x51" title="-" name="L2D_CACHE_ST" description="Level 2 data cache access - Write"/>
75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
76 <event event="0x52" title="-" name="L2D_CACHE_REFILL_LD" description="Level 2 data cache refill - Read"/>
77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
78 <event event="0x53" title="-" name="L2D_CACHE_REFILL_ST" description="Level 2 data cache refill - Write"/>
79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
80 <event event="0x56" title="-" name="L2D_CACHE_WB_VICTIM" description="Level 2 data cache Write-back - Victim"/>
81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
82 <event event="0x57" title="-" name="L2D_CACHE_WB_CLEAN" description="Level 2 data cache Write-back - Cleaning and coherency"/>
83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
84 <event event="0x58" title="-" name="L2D_CACHE_INVAL" description="Level 2 data cache invalidate"/>
85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
86 <event event="0x60" title="-" name="BUS_ACCESS_LD" description="Bus access - Read"/>
87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
88 <event event="0x61" title="-" name="BUS_ACCESS_ST" description="Bus access - Write"/>
89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
90 <event event="0x62" title="-" name="BUS_ACCESS_SHARED" description="Bus access - Normal"/>
91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
92 <event event="0x63" title="-" name="BUS_ACCESS_NOT_SHARED" description="Bus access - Not normal"/>
93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
94 <event event="0x64" title="-" name="BUS_ACCESS_NORMAL" description="Bus access - Normal"/>
95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
96 <event event="0x65" title="-" name="BUS_ACCESS_PERIPH" description="Bus access - Peripheral"/>
97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
98 <event event="0x66" title="-" name="MEM_ACCESS_LD" description="Data memory access - Read"/>
99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
100 <event event="0x67" title="-" name="MEM_ACCESS_ST" description="Data memory access - Write"/>
101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
102 <event event="0x68" title="-" name="UNALIGNED_LD_SPEC" description="Unaligned access - Read"/>
103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
104 <event event="0x69" title="-" name="UNALIGNED_ST_SPEC" description="Unaligned access - Write"/>
105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
106 <event event="0x6A" title="-" name="UNALIGNED_LDST_SPEC" description="Unaligned access"/>
107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
108 <event event="0x6C" title="-" name="LDREX_SPEC" description="Exclusive operation speculatively executed - LDREX"/>
109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
110 <event event="0x6D" title="-" name="STREX_PASS_SPEC" description="Exclusive instruction speculatively executed - STREX pass"/>
111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
112 <event event="0x6E" title="-" name="STREX_FAIL_SPEC" description="Exclusive operation speculatively executed - STREX fail"/>
113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
114 <event event="0x70" title="-" name="LD_SPEC" description="Operation speculatively executed - Load"/>
115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
116 <event event="0x71" title="-" name="ST_SPEC" description="Operation speculatively executed - Store"/>
117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
118 <event event="0x72" title="-" name="LDST_SPEC" description="Operation speculatively executed - Load or store"/>
119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
120 <event event="0x73" title="-" name="DP_SPEC" description="Operation speculatively executed - Integer data processing"/>
121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
122 <event event="0x74" title="-" name="ASE_SPEC" description="Operation speculatively executed - Advanced SIMD"/>
123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
124 <event event="0x75" title="-" name="VFP_SPEC" description="Operation speculatively executed - VFP"/>
125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
126 <event event="0x76" title="-" name="PC_WRITE_SPEC" description="Operation speculatively executed - Software change of the PC"/>
127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
128 <event event="0x77" title="-" name="CRYPTO_SPEC" description="Operation speculatively executed, crypto data processing"/>
129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
130 <event event="0x78" title="-" name="BR_IMMED_SPEC" description="Branch speculatively executed - Immediate branch"/>
131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
132 <event event="0x79" title="-" name="BR_RETURN_SPEC" description="Branch speculatively executed - Procedure return"/>
133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
134 <event event="0x7A" title="-" name="BR_INDIRECT_SPEC" description="Branch speculatively executed - Indirect branch"/>
135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
136 <event event="0x7C" title="-" name="ISB_SPEC" description="Barrier speculatively executed - ISB"/>
137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
138 <event event="0x7D" title="-" name="DSB_SPEC" description="Barrier speculatively executed - DSB"/>
139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
140 <event event="0x7E" title="-" name="DMB_SPEC" description="Barrier speculatively executed - DMB"/>
141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
142 <event event="0x81" title="-" name="EXC_UNDEF" description="Exception taken, other synchronous"/>
143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
144 <event event="0x82" title="-" name="EXC_SVC" description="Exception taken, Supervisor Call"/>
145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
146 <event event="0x83" title="-" name="EXC_PABORT" description="Exception taken, Instruction Abort"/>
147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
148 <event event="0x84" title="-" name="EXC_DABORT" description="Exception taken, Data Abort or SError"/>
149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
150 <event event="0x86" title="-" name="EXC_IRQ" description="Exception taken, IRQ"/>
151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
152 <event event="0x87" title="-" name="EXC_FIQ" description="Exception taken, FIQ"/>
153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
154 <event event="0x88" title="-" name="EXC_SMC" description="Exception taken, Secure Monitor Call"/>
155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
156 <event event="0x8A" title="-" name="EXC_HVC" description="Exception taken, Hypervisor Call"/>
157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
158 <event event="0x8B" title="-" name="EXC_TRAP_PABORT" description="Exception taken, Instruction Abort not taken locally"/>
159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
160 <event event="0x8C" title="-" name="EXC_TRAP_DABORT" description="Exception taken, Data Abort or SError not taken locally"/>
161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken – Other traps not taken locally -->
162 <event event="0x8D" title="-" name="EXC_TRAP_OTHER" description="Exception taken – Other traps not taken locally"/>
163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
164 <event event="0x8E" title="-" name="EXC_TRAP_IRQ" description="Exception taken, IRQ not taken locally"/>
165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
166 <event event="0x8F" title="-" name="EXC_TRAP_FIQ" description="Exception taken, FIQ not taken locally"/>
167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed – Load Acquire -->
168 <event event="0x90" title="-" name="RC_LD_SPEC" description="Release consistency instruction speculatively executed – Load Acquire"/>
169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed – Store Release -->
170 <event event="0x91" title="-" name="RC_ST_SPEC" description="Release consistency instruction speculatively executed – Store Release"/>
171 </category>
generated by cgit v1.2.3 (git 2.25.1)