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authorJon Medhurst2012-08-10 08:46:05 -0500
committerJon Medhurst2012-08-10 08:46:05 -0500
commit408ffc1cdebaf3a34d3815077860fb8c3bbaf2e8 (patch)
treeae2068bf70049b90790d49666b20cf832aa70f68
parent4c7cf996b31246f8094e5717dbf5ad291d50ef34 (diff)
parent1963aa53d43ccd827335b28ba2c7e25300065e6c (diff)
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Merge branch 'master' into android
-rw-r--r--[-rwxr-xr-x]daemon/Android.mk82
-rw-r--r--daemon/Child.cpp8
-rw-r--r--daemon/Collector.cpp2
-rw-r--r--daemon/Fifo.cpp251
-rw-r--r--daemon/Fifo.h66
-rw-r--r--daemon/Makefile7
-rw-r--r--[-rwxr-xr-x]daemon/OlySocket.cpp0
-rw-r--r--[-rwxr-xr-x]daemon/OlySocket.h0
-rw-r--r--[-rwxr-xr-x]daemon/OlyUtility.cpp5
-rw-r--r--[-rwxr-xr-x]daemon/OlyUtility.h0
-rw-r--r--daemon/SessionData.h2
-rw-r--r--daemon/configuration.xml80
-rw-r--r--daemon/events-ARM11.xml86
-rw-r--r--daemon/events-ARM11MPCore.xml8
-rw-r--r--daemon/events-Cortex-A15.xml152
-rw-r--r--daemon/events-Cortex-A5.xml78
-rw-r--r--[-rwxr-xr-x]daemon/events-Cortex-A7.xml98
-rw-r--r--daemon/events-Cortex-A8.xml114
-rw-r--r--daemon/events-Cortex-A9.xml138
-rw-r--r--[-rwxr-xr-x]daemon/events-Krait-architected.xml54
-rw-r--r--daemon/events-L2C-310.xml42
-rw-r--r--daemon/events-Linux.xml34
-rw-r--r--daemon/events-Mali-400.xml800
-rw-r--r--daemon/events-Mali-T6xx.xml38
-rw-r--r--daemon/events-Mali-T6xx_hw.xml278
-rw-r--r--daemon/events-Scorpion.xml224
-rw-r--r--daemon/events-ScorpionMP.xml190
-rw-r--r--daemon/main.cpp30
-rw-r--r--daemon/mxml/mxml-file.c6
-rw-r--r--driver/Makefile7
-rw-r--r--driver/gator_annotate.c9
-rw-r--r--driver/gator_cookies.c5
-rw-r--r--driver/gator_ebs.c18
-rw-r--r--[-rwxr-xr-x]driver/gator_events_mali_400.c (renamed from driver/gator_events_mali.c)335
-rw-r--r--driver/gator_events_mali_400.h19
-rw-r--r--driver/gator_events_mali_common.c79
-rw-r--r--driver/gator_events_mali_common.h85
-rw-r--r--driver/gator_events_mali_t6xx.c553
-rw-r--r--driver/gator_events_mali_t6xx_hw.c571
-rw-r--r--driver/gator_events_meminfo.c5
-rw-r--r--driver/gator_events_net.c1
-rw-r--r--[-rwxr-xr-x]driver/gator_events_perf_pmu.c20
-rw-r--r--driver/gator_fs.c1
-rw-r--r--[-rwxr-xr-x]driver/gator_hrtimer_gator.c0
-rw-r--r--driver/gator_main.c15
-rw-r--r--[-rwxr-xr-x]driver/gator_marshaling.c0
-rw-r--r--driver/gator_trace_gpu.c152
-rw-r--r--[-rwxr-xr-x]driver/gator_trace_power.c0
-rw-r--r--driver/mali_t6xx.mk24
49 files changed, 3280 insertions, 1492 deletions
diff --git a/daemon/Android.mk b/daemon/Android.mk
index 715e5b6..cbaf42d 100755..100644
--- a/daemon/Android.mk
+++ b/daemon/Android.mk
@@ -1,41 +1,41 @@
1LOCAL_PATH:= $(call my-dir) 1LOCAL_PATH:= $(call my-dir)
2include $(CLEAR_VARS) 2include $(CLEAR_VARS)
3 3
4$(shell cd $(LOCAL_PATH);cat events_header.xml events-*\.xml events_footer.xml > events.xml;xxd -i events.xml > events_xml.h;xxd -i configuration.xml > configuration_xml.h) 4$(shell cd $(LOCAL_PATH);cat events_header.xml events-*\.xml events_footer.xml > events.xml;xxd -i events.xml > events_xml.h;xxd -i configuration.xml > configuration_xml.h)
5 5
6LOCAL_CFLAGS += -Wall -O3 -ftree-vectorize -Wno-error=sequence-point 6LOCAL_CFLAGS += -Wall -O3 -ftree-vectorize -Wno-error=sequence-point
7 7
8LOCAL_SRC_FILES:= \ 8LOCAL_SRC_FILES:= \
9 CapturedXML.cpp \ 9 CapturedXML.cpp \
10 Child.cpp \ 10 Child.cpp \
11 Collector.cpp \ 11 Collector.cpp \
12 ConfigurationXML.cpp \ 12 ConfigurationXML.cpp \
13 Fifo.cpp \ 13 Fifo.cpp \
14 LocalCapture.cpp \ 14 LocalCapture.cpp \
15 Logging.cpp \ 15 Logging.cpp \
16 main.cpp \ 16 main.cpp \
17 OlySocket.cpp \ 17 OlySocket.cpp \
18 OlyUtility.cpp \ 18 OlyUtility.cpp \
19 Sender.cpp \ 19 Sender.cpp \
20 SessionData.cpp \ 20 SessionData.cpp \
21 SessionXML.cpp \ 21 SessionXML.cpp \
22 StreamlineSetup.cpp \ 22 StreamlineSetup.cpp \
23 mxml/mxml-attr.c \ 23 mxml/mxml-attr.c \
24 mxml/mxml-entity.c \ 24 mxml/mxml-entity.c \
25 mxml/mxml-file.c \ 25 mxml/mxml-file.c \
26 mxml/mxml-get.c \ 26 mxml/mxml-get.c \
27 mxml/mxml-index.c \ 27 mxml/mxml-index.c \
28 mxml/mxml-node.c \ 28 mxml/mxml-node.c \
29 mxml/mxml-private.c \ 29 mxml/mxml-private.c \
30 mxml/mxml-search.c \ 30 mxml/mxml-search.c \
31 mxml/mxml-set.c \ 31 mxml/mxml-set.c \
32 mxml/mxml-string.c 32 mxml/mxml-string.c
33 33
34LOCAL_C_INCLUDES := $(LOCAL_PATH) 34LOCAL_C_INCLUDES := $(LOCAL_PATH)
35 35
36LOCAL_MODULE:= gatord 36LOCAL_MODULE:= gatord
37LOCAL_MODULE_TAGS:= optional 37LOCAL_MODULE_TAGS:= optional
38 38
39LOCAL_LDLIBS := -lz -llog 39LOCAL_LDLIBS := -lz -llog
40 40
41include $(BUILD_EXECUTABLE) 41include $(BUILD_EXECUTABLE)
diff --git a/daemon/Child.cpp b/daemon/Child.cpp
index bcc868a..2c7c292 100644
--- a/daemon/Child.cpp
+++ b/daemon/Child.cpp
@@ -79,7 +79,7 @@ void child_handler(int signum) {
79} 79}
80 80
81void* durationThread(void* pVoid) { 81void* durationThread(void* pVoid) {
82 prctl(PR_SET_NAME, (unsigned int)&"gatord-duration", 0, 0, 0); 82 prctl(PR_SET_NAME, (unsigned long)&"gatord-duration", 0, 0, 0);
83 sem_wait(&startProfile); 83 sem_wait(&startProfile);
84 if (gSessionData->mSessionIsActive) { 84 if (gSessionData->mSessionIsActive) {
85 // Time out after duration seconds 85 // Time out after duration seconds
@@ -99,7 +99,7 @@ void* stopThread(void* pVoid) {
99 char type; 99 char type;
100 OlySocket* socket = child->socket; 100 OlySocket* socket = child->socket;
101 101
102 prctl(PR_SET_NAME, (unsigned int)&"gatord-stopper", 0, 0, 0); 102 prctl(PR_SET_NAME, (unsigned long)&"gatord-stopper", 0, 0, 0);
103 while (gSessionData->mSessionIsActive) { 103 while (gSessionData->mSessionIsActive) {
104 // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected 104 // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected
105 if (socket->receiveNBytes(&type, sizeof(type)) > 0) { 105 if (socket->receiveNBytes(&type, sizeof(type)) > 0) {
@@ -137,7 +137,7 @@ void* senderThread(void* pVoid) {
137 char end_sequence[] = {RESPONSE_APC_DATA, 0, 0, 0, 0}; 137 char end_sequence[] = {RESPONSE_APC_DATA, 0, 0, 0, 0};
138 138
139 sem_post(&senderThreadStarted); 139 sem_post(&senderThreadStarted);
140 prctl(PR_SET_NAME, (unsigned int)&"gatord-sender", 0, 0, 0); 140 prctl(PR_SET_NAME, (unsigned long)&"gatord-sender", 0, 0, 0);
141 sem_wait(&haltPipeline); 141 sem_wait(&haltPipeline);
142 142
143 do { 143 do {
@@ -196,7 +196,7 @@ void Child::run() {
196 LocalCapture* localCapture = NULL; 196 LocalCapture* localCapture = NULL;
197 pthread_t durationThreadID, stopThreadID, senderThreadID; 197 pthread_t durationThreadID, stopThreadID, senderThreadID;
198 198
199 prctl(PR_SET_NAME, (unsigned int)&"gatord-child", 0, 0, 0); 199 prctl(PR_SET_NAME, (unsigned long)&"gatord-child", 0, 0, 0);
200 200
201 // Disable line wrapping when generating xml files; carriage returns and indentation to be added manually 201 // Disable line wrapping when generating xml files; carriage returns and indentation to be added manually
202 mxmlSetWrapMargin(0); 202 mxmlSetWrapMargin(0);
diff --git a/daemon/Collector.cpp b/daemon/Collector.cpp
index db7b9c0..d29cd16 100644
--- a/daemon/Collector.cpp
+++ b/daemon/Collector.cpp
@@ -237,7 +237,7 @@ void Collector::getCoreName() {
237 "The core name in the captured xml file will be 'unknown'."); 237 "The core name in the captured xml file will be 'unknown'.");
238 return; 238 return;
239 } 239 }
240 strncpy(gSessionData->mCoreName, (char*)((int)position + 2), sizeof(gSessionData->mCoreName)); 240 strncpy(gSessionData->mCoreName, (char*)((long)position + 2), sizeof(gSessionData->mCoreName));
241 gSessionData->mCoreName[sizeof(gSessionData->mCoreName) - 1] = 0; // strncpy does not guarantee a null-terminated string 241 gSessionData->mCoreName[sizeof(gSessionData->mCoreName) - 1] = 0; // strncpy does not guarantee a null-terminated string
242 fclose(f); 242 fclose(f);
243 return; 243 return;
diff --git a/daemon/Fifo.cpp b/daemon/Fifo.cpp
index bbfc919..191536f 100644
--- a/daemon/Fifo.cpp
+++ b/daemon/Fifo.cpp
@@ -1,126 +1,125 @@
1/** 1/**
2 * Copyright (C) ARM Limited 2010-2012. All rights reserved. 2 * Copyright (C) ARM Limited 2010-2012. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <stdlib.h> 9#include <stdlib.h>
10#include <string.h> 10#include <string.h>
11#include <unistd.h> 11#include <unistd.h>
12#include "Fifo.h" 12#include "Fifo.h"
13#include "Logging.h" 13#include "Logging.h"
14 14
15extern void handleException(); 15extern void handleException();
16 16
17// bufferSize is the amount of data to be filled 17// bufferSize is the amount of data to be filled
18// singleBufferSize is the maximum size that may be filled during a single write 18// singleBufferSize is the maximum size that may be filled during a single write
19// (bufferSize + singleBufferSize) will be allocated 19// (bufferSize + singleBufferSize) will be allocated
20Fifo::Fifo(int singleBufferSize, int bufferSize) { 20Fifo::Fifo(int singleBufferSize, int bufferSize) {
21 mWrite = mRead = mReadCommit = mRaggedEnd = 0; 21 mWrite = mRead = mReadCommit = mRaggedEnd = 0;
22 mWrapThreshold = bufferSize; 22 mWrapThreshold = bufferSize;
23 mSingleBufferSize = singleBufferSize; 23 mSingleBufferSize = singleBufferSize;
24 mBuffer = (char*)valloc(bufferSize + singleBufferSize); 24 mBuffer = (char*)valloc(bufferSize + singleBufferSize);
25 mEnd = false; 25 mEnd = false;
26 26
27 if (mBuffer == NULL) { 27 if (mBuffer == NULL) {
28 logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize); 28 logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize);
29 handleException(); 29 handleException();
30 } 30 }
31 31
32 if (sem_init(&mWaitForSpaceSem, 0, 0) || sem_init(&mWaitForDataSem, 0, 0)) { 32 if (sem_init(&mWaitForSpaceSem, 0, 0) || sem_init(&mWaitForDataSem, 0, 0)) {
33 logg->logError(__FILE__, __LINE__, "sem_init() failed"); 33 logg->logError(__FILE__, __LINE__, "sem_init() failed");
34 handleException(); 34 handleException();
35 } 35 }
36} 36}
37 37
38Fifo::~Fifo() { 38Fifo::~Fifo() {
39 free(mBuffer); 39 free(mBuffer);
40} 40}
41 41
42int Fifo::numBytesFilled() { 42int Fifo::numBytesFilled() {
43 return mWrite - mRead + mRaggedEnd; 43 return mWrite - mRead + mRaggedEnd;
44} 44}
45 45
46char* Fifo::start() { 46char* Fifo::start() {
47 return mBuffer; 47 return mBuffer;
48} 48}
49 49
50bool Fifo::isEmpty() { 50bool Fifo::isEmpty() {
51 return mRead == mWrite; 51 return mRead == mWrite && mRaggedEnd == 0;
52} 52}
53 53
54bool Fifo::isFull() { 54bool Fifo::isFull() {
55 return willFill(0); 55 return willFill(0);
56} 56}
57 57
58// Determines if the buffer will fill assuming 'additional' bytes will be added to the buffer 58// Determines if the buffer will fill assuming 'additional' bytes will be added to the buffer
59// comparisons use '<', read and write pointers must never equal when not empty 59// 'full' means there is less than singleBufferSize bytes available contiguously; it does not mean there are zero bytes available
60// 'full' means there is less than singleBufferSize bytes available; it does not mean there are zero bytes available 60bool Fifo::willFill(int additional) {
61bool Fifo::willFill(int additional) { 61 if (mWrite > mRead) {
62 if (mWrite > mRead) { 62 if (numBytesFilled() + additional < mWrapThreshold) {
63 if (numBytesFilled() + additional < mWrapThreshold) { 63 return false;
64 return false; 64 }
65 } 65 } else {
66 } else { 66 if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) {
67 if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) { 67 return false;
68 return false; 68 }
69 } 69 }
70 } 70 return true;
71 return true; 71}
72} 72
73 73// This function will stall until contiguous singleBufferSize bytes are available
74// This function will stall until contiguous singleBufferSize bytes are available 74char* Fifo::write(int length) {
75char* Fifo::write(int length) { 75 if (length <= 0) {
76 if (length <= 0) { 76 length = 0;
77 length = 0; 77 mEnd = true;
78 mEnd = true; 78 }
79 } 79
80 80 // update the write pointer
81 // update the write pointer 81 mWrite += length;
82 mWrite += length; 82
83 83 // handle the wrap-around
84 // handle the wrap-around 84 if (mWrite >= mWrapThreshold) {
85 if (mWrite >= mWrapThreshold) { 85 mRaggedEnd = mWrite;
86 mRaggedEnd = mWrite; 86 mWrite = 0;
87 mWrite = 0; 87 }
88 } 88
89 89 // send a notification that data is ready
90 // send a notification that data is ready 90 sem_post(&mWaitForDataSem);
91 sem_post(&mWaitForDataSem); 91
92 92 // wait for space
93 // wait for space 93 while (isFull()) {
94 while (isFull()) { 94 sem_wait(&mWaitForSpaceSem);
95 sem_wait(&mWaitForSpaceSem); 95 }
96 } 96
97 97 return &mBuffer[mWrite];
98 return &mBuffer[mWrite]; 98}
99} 99
100 100// This function will stall until data is available
101// This function will stall until data is available 101char* Fifo::read(int* length) {
102char* Fifo::read(int* length) { 102 // update the read pointer now that the data has been handled
103 // update the read pointer now that the data has been handled 103 mRead = mReadCommit;
104 mRead = mReadCommit; 104
105 105 // handle the wrap-around
106 // handle the wrap-around 106 if (mRead >= mWrapThreshold) {
107 if (mRead >= mWrapThreshold) { 107 mRaggedEnd = mRead = mReadCommit = 0;
108 mRaggedEnd = mRead = mReadCommit = 0; 108 }
109 } 109
110 110 // send a notification that data is free (space is available)
111 // send a notification that data is free (space is available) 111 sem_post(&mWaitForSpaceSem);
112 sem_post(&mWaitForSpaceSem); 112
113 113 // wait for data
114 // wait for data 114 while (isEmpty() && !mEnd) {
115 while (isEmpty() && !mEnd) { 115 sem_wait(&mWaitForDataSem);
116 sem_wait(&mWaitForDataSem); 116 }
117 } 117
118 118 // obtain the length
119 // obtain the length 119 do {
120 do { 120 mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite;
121 mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite; 121 *length = mReadCommit - mRead;
122 *length = mReadCommit - mRead; 122 } while (*length < 0); // plugs race condition without using semaphores
123 } while (*length < 0); // plugs race condition without using semaphores 123
124 124 return &mBuffer[mRead];
125 return &mBuffer[mRead]; 125}
126}
diff --git a/daemon/Fifo.h b/daemon/Fifo.h
index 548ba27..b460549 100644
--- a/daemon/Fifo.h
+++ b/daemon/Fifo.h
@@ -1,33 +1,33 @@
1/** 1/**
2 * Copyright (C) ARM Limited 2010-2012. All rights reserved. 2 * Copyright (C) ARM Limited 2010-2012. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#ifndef __FIFO_H__ 9#ifndef __FIFO_H__
10#define __FIFO_H__ 10#define __FIFO_H__
11 11
12#include <semaphore.h> 12#include <semaphore.h>
13 13
14class Fifo { 14class Fifo {
15public: 15public:
16 Fifo(int singleBufferSize, int totalBufferSize); 16 Fifo(int singleBufferSize, int totalBufferSize);
17 ~Fifo(); 17 ~Fifo();
18 int numBytesFilled(); 18 int numBytesFilled();
19 bool isEmpty(); 19 bool isEmpty();
20 bool isFull(); 20 bool isFull();
21 bool willFill(int additional); 21 bool willFill(int additional);
22 char* start(); 22 char* start();
23 char* write(int length); 23 char* write(int length);
24 char* read(int* length); 24 char* read(int* length);
25 25
26private: 26private:
27 int mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold; 27 int mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold;
28 sem_t mWaitForSpaceSem, mWaitForDataSem; 28 sem_t mWaitForSpaceSem, mWaitForDataSem;
29 char* mBuffer; 29 char* mBuffer;
30 bool mEnd; 30 bool mEnd;
31}; 31};
32 32
33#endif //__FIFO_H__ 33#endif //__FIFO_H__
diff --git a/daemon/Makefile b/daemon/Makefile
index 300c3e9..b62a223 100644
--- a/daemon/Makefile
+++ b/daemon/Makefile
@@ -16,9 +16,10 @@ GCC=$(CROSS_COMPILE)gcc
16# -Werror treats warnings as errors 16# -Werror treats warnings as errors
17# -std=c++0x is the planned new c++ standard 17# -std=c++0x is the planned new c++ standard
18# -std=c++98 is the 1998 c++ standard 18# -std=c++98 is the 1998 c++ standard
19# -march=armv5t is required to set the minimum architecture
20# -mthumb-interwork is required for interworking to ARM or Thumb stdlibc 19# -mthumb-interwork is required for interworking to ARM or Thumb stdlibc
21CFLAGS=-O3 -Wall -Werror -Wno-error=sequence-point -march=armv5t -mthumb-interwork 20CFLAGS=-O3 -Wall -Werror -Wno-error=sequence-point -mthumb-interwork
21# -s strips the binary of debug info
22LDFLAGS=-s
22TARGET=gatord 23TARGET=gatord
23C_SRC = $(wildcard mxml/*.c) 24C_SRC = $(wildcard mxml/*.c)
24CPP_SRC = $(wildcard *.cpp) 25CPP_SRC = $(wildcard *.cpp)
@@ -34,7 +35,7 @@ all: $(TARGET)
34 $(CPP) -c $(CFLAGS) -o $@ $< 35 $(CPP) -c $(CFLAGS) -o $@ $<
35 36
36$(TARGET): convert $(TGT_OBJS) 37$(TARGET): convert $(TGT_OBJS)
37 $(CPP) -s -o $@ $(TGT_OBJS) -lc -lrt -lpthread 38 $(CPP) $(LDFLAGS) -o $@ $(TGT_OBJS) -lc -lrt -lpthread
38 rm events_xml.h configuration_xml.h 39 rm events_xml.h configuration_xml.h
39 40
40convert: 41convert:
diff --git a/daemon/OlySocket.cpp b/daemon/OlySocket.cpp
index a3bf746..a3bf746 100755..100644
--- a/daemon/OlySocket.cpp
+++ b/daemon/OlySocket.cpp
diff --git a/daemon/OlySocket.h b/daemon/OlySocket.h
index 266a831..266a831 100755..100644
--- a/daemon/OlySocket.h
+++ b/daemon/OlySocket.h
diff --git a/daemon/OlyUtility.cpp b/daemon/OlyUtility.cpp
index ec852df..c72b0d1 100755..100644
--- a/daemon/OlyUtility.cpp
+++ b/daemon/OlyUtility.cpp
@@ -197,7 +197,7 @@ const char* OlyUtility::getFilePart(const char* path) {
197 return path; 197 return path;
198 } 198 }
199 199
200 return (const char*)((int)last_sep + 1); 200 return last_sep++;
201} 201}
202 202
203// getPathPart may modify the contents of path 203// getPathPart may modify the contents of path
@@ -209,7 +209,8 @@ char* OlyUtility::getPathPart(char* path) {
209 if (last_sep == NULL) { 209 if (last_sep == NULL) {
210 return 0; 210 return 0;
211 } 211 }
212 *(char*)((int)last_sep + 1) = 0; 212 last_sep++;
213 *last_sep = 0;
213 214
214 return (path); 215 return (path);
215} 216}
diff --git a/daemon/OlyUtility.h b/daemon/OlyUtility.h
index 793a733..793a733 100755..100644
--- a/daemon/OlyUtility.h
+++ b/daemon/OlyUtility.h
diff --git a/daemon/SessionData.h b/daemon/SessionData.h
index 7daee72..6f42c07 100644
--- a/daemon/SessionData.h
+++ b/daemon/SessionData.h
@@ -13,7 +13,7 @@
13#define MAX_STRING_LEN 80 13#define MAX_STRING_LEN 80
14#define MAX_DESCRIPTION_LEN 400 14#define MAX_DESCRIPTION_LEN 400
15 15
16#define PROTOCOL_VERSION 9 16#define PROTOCOL_VERSION 10
17#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions 17#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions
18 18
19struct ImageLinkList { 19struct ImageLinkList {
diff --git a/daemon/configuration.xml b/daemon/configuration.xml
index 9d083d5..4875f1f 100644
--- a/daemon/configuration.xml
+++ b/daemon/configuration.xml
@@ -1,51 +1,51 @@
1<?xml version="1.0" encoding='UTF-8'?> 1<?xml version="1.0" encoding='UTF-8'?>
2<configurations version="1" revision="1"> 2<configurations version="1" revision="1">
3 <configuration counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" per_cpu="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <configuration counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" per_cpu="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
4 <configuration counter="ARM_ARM11_cnt0" event="0x7" title="Instruction" name="Executed" per_cpu="yes" alias="InstructionsExecuted" description="Instructions executed"/> 4 <configuration counter="ARM_ARM11_cnt0" event="0x7" title="Instruction" name="Executed" per_cpu="yes" description="Instructions executed"/>
5 <configuration counter="ARM_ARM11_cnt1" event="0xb" title="Cache" name="Data miss" per_cpu="yes" alias="L1Miss" description="Data cache miss, not including Cache Operations"/> 5 <configuration counter="ARM_ARM11_cnt1" event="0xb" title="Cache" name="Data miss" per_cpu="yes" description="Data cache miss, not including Cache Operations"/>
6 <configuration counter="ARM_ARM11MPCore_ccnt" title="Clock" name="Cycles" per_cpu="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 6 <configuration counter="ARM_ARM11MPCore_ccnt" title="Clock" name="Cycles" per_cpu="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
7 <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08" title="Core" name="Instructions" per_cpu="yes" alias="InstructionsExecuted" description="Instructions executed"/> 7 <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08" title="Core" name="Instructions" per_cpu="yes" description="Instructions executed"/>
8 <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b" title="Cache" name="Data read miss" per_cpu="yes" alias="L1Miss" description="Data cache miss, not including Cache Operations"/> 8 <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b" title="Cache" name="Data read miss" per_cpu="yes" description="Data cache miss, not including Cache Operations"/>
9 <configuration counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 9 <configuration counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
10 <configuration counter="ARM_Cortex-A5_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 10 <configuration counter="ARM_Cortex-A5_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
11 <configuration counter="ARM_Cortex-A5_cnt1" event="0x1" title="Cache" name="Instruction refill" per_cpu="yes" event_based_sampling="yes" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 11 <configuration counter="ARM_Cortex-A5_cnt1" event="0x1" title="Cache" name="Instruction refill" per_cpu="yes" event_based_sampling="yes" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
12 <configuration counter="ARM_Cortex-A7_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 12 <configuration counter="ARM_Cortex-A7_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
13 <configuration counter="ARM_Cortex-A7_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 13 <configuration counter="ARM_Cortex-A7_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
14 <configuration counter="ARM_Cortex-A7_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 14 <configuration counter="ARM_Cortex-A7_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
15 <configuration counter="ARM_Cortex-A7_cnt2" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" event_based_sampling="yes" alias="L1Miss" description="Level 2 data cache access"/> 15 <configuration counter="ARM_Cortex-A7_cnt2" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" event_based_sampling="yes" description="Level 2 data cache access"/>
16 <configuration counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 16 <configuration counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
17 <configuration counter="ARM_Cortex-A8_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <configuration counter="ARM_Cortex-A8_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
18 <configuration counter="ARM_Cortex-A8_cnt1" event="0x44" title="Cache" name="L2 miss" per_cpu="yes" event_based_sampling="yes" alias="L2Miss" description="Any cacheable miss in the L2 cache"/> 18 <configuration counter="ARM_Cortex-A8_cnt1" event="0x44" title="Cache" name="L2 miss" per_cpu="yes" event_based_sampling="yes" description="Any cacheable miss in the L2 cache"/>
19 <configuration counter="ARM_Cortex-A8_cnt2" event="0x43" title="Cache" name="L1 miss" per_cpu="yes" event_based_sampling="yes" alias="L1Miss" description="Any accesses to the L2 cache"/> 19 <configuration counter="ARM_Cortex-A8_cnt2" event="0x43" title="Cache" name="L1 miss" per_cpu="yes" event_based_sampling="yes" description="Any accesses to the L2 cache"/>
20 <configuration counter="ARM_Cortex-A8_cnt3" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 20 <configuration counter="ARM_Cortex-A8_cnt3" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
21 <configuration counter="ARM_Cortex-A9_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 21 <configuration counter="ARM_Cortex-A9_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
22 <configuration counter="ARM_Cortex-A9_cnt0" event="0x68" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/> 22 <configuration counter="ARM_Cortex-A9_cnt0" event="0x68" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>
23 <configuration counter="ARM_Cortex-A9_cnt1" event="0x06" title="Instruction" name="Memory read" per_cpu="yes" event_based_sampling="yes" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 23 <configuration counter="ARM_Cortex-A9_cnt1" event="0x06" title="Instruction" name="Memory read" per_cpu="yes" event_based_sampling="yes" description="Memory-reading instruction architecturally executed"/>
24 <configuration counter="ARM_Cortex-A9_cnt2" event="0x07" title="Instruction" name="Memory write" per_cpu="yes" event_based_sampling="yes" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 24 <configuration counter="ARM_Cortex-A9_cnt2" event="0x07" title="Instruction" name="Memory write" per_cpu="yes" event_based_sampling="yes" description="Memory-writing instruction architecturally executed"/>
25 <configuration counter="ARM_Cortex-A9_cnt3" event="0x03" title="Cache" name="Data refill" per_cpu="yes" event_based_sampling="yes" alias="DataRefill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 25 <configuration counter="ARM_Cortex-A9_cnt3" event="0x03" title="Cache" name="Data refill" per_cpu="yes" event_based_sampling="yes" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
26 <configuration counter="ARM_Cortex-A9_cnt4" event="0x04" title="Cache" name="Data access" per_cpu="yes" event_based_sampling="yes" alias="DataAccess" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 26 <configuration counter="ARM_Cortex-A9_cnt4" event="0x04" title="Cache" name="Data access" per_cpu="yes" event_based_sampling="yes" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
27 <configuration counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 27 <configuration counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
28 <configuration counter="ARM_Cortex-A15_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 28 <configuration counter="ARM_Cortex-A15_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
29 <configuration counter="ARM_Cortex-A15_cnt1" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" event_based_sampling="yes" alias="L1Miss" description="Level 2 data cache access"/> 29 <configuration counter="ARM_Cortex-A15_cnt1" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" event_based_sampling="yes" description="Level 2 data cache access"/>
30 <configuration counter="ARM_Cortex-A15_cnt2" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 30 <configuration counter="ARM_Cortex-A15_cnt2" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
31 <configuration counter="ARM_Cortex-A15_cnt3" event="0x19" title="Bus" name="Access" per_cpu="yes" event_based_sampling="yes" description=""/> 31 <configuration counter="ARM_Cortex-A15_cnt3" event="0x19" title="Bus" name="Access" per_cpu="yes" event_based_sampling="yes" description=""/>
32 <configuration counter="Scorpion_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 32 <configuration counter="Scorpion_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
33 <configuration counter="Scorpion_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 33 <configuration counter="Scorpion_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
34 <configuration counter="Scorpion_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 34 <configuration counter="Scorpion_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
35 <configuration counter="ScorpionMP_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 35 <configuration counter="ScorpionMP_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
36 <configuration counter="ScorpionMP_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 36 <configuration counter="ScorpionMP_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
37 <configuration counter="ScorpionMP_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 37 <configuration counter="ScorpionMP_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
38 <configuration counter="Krait_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 38 <configuration counter="Krait_ccnt" title="Clock" name="Cycles" per_cpu="yes" event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
39 <configuration counter="Krait_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 39 <configuration counter="Krait_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" event_based_sampling="yes" description="Instruction architecturally executed"/>
40 <configuration counter="Krait_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 40 <configuration counter="Krait_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
41 <configuration counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/> 41 <configuration counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/>
42 <configuration counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/> 42 <configuration counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/>
43 <configuration counter="Linux_net_rx" title="Network" name="Receive" units="B" description="Receive network traffic, excluding effect from Streamline"/> 43 <configuration counter="Linux_net_rx" title="Network" name="Receive" units="B" description="Receive network traffic, including effect from Streamline"/>
44 <configuration counter="Linux_net_tx" title="Network" name="Transmit" units="B" description="Transmit network traffic, excluding effect from Streamline"/> 44 <configuration counter="Linux_net_tx" title="Network" name="Transmit" units="B" description="Transmit network traffic, including effect from Streamline"/>
45 <configuration counter="Linux_cpuload_system" title="CPU Load" name="System" description="Scheduler CPU Load of System Behavior"/> 45 <configuration counter="Linux_cpuload_system" title="CPU Load" name="System" description="Scheduler CPU Load of System Behavior"/>
46 <configuration counter="Linux_cpuload_user" title="CPU Load" name="User" description="Scheduler CPU Load of User Application"/> 46 <configuration counter="Linux_cpuload_user" title="CPU Load" name="User" description="Scheduler CPU Load of User Application"/>
47 <configuration counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/> 47 <configuration counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/>
48 <configuration counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/> 48 <configuration counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/>
49 <configuration counter="Linux_power_cpu_freq" title="Clock" name="DVFS" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Target frequency of the CPU"/> 49 <configuration counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Frequency setting of the CPU"/>
50 <configuration counter="L2C-310_cnt0" event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOut, of a line from the L2 cache"/> 50 <configuration counter="L2C-310_cnt0" event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
51</configurations> 51</configurations>
diff --git a/daemon/events-ARM11.xml b/daemon/events-ARM11.xml
index c9d188f..d4a2914 100644
--- a/daemon/events-ARM11.xml
+++ b/daemon/events-ARM11.xml
@@ -1,43 +1,43 @@
1 <counter_set name="ARM_ARM11_cntX"> 1 <counter_set name="ARM_ARM11_cntX">
2 <counter name="ARM_ARM11_cnt0"/> 2 <counter name="ARM_ARM11_cnt0"/>
3 <counter name="ARM_ARM11_cnt1"/> 3 <counter name="ARM_ARM11_cnt1"/>
4 <counter name="ARM_ARM11_cnt2"/> 4 <counter name="ARM_ARM11_cnt2"/>
5 </counter_set> 5 </counter_set>
6 <category name="ARM11" counter_set="ARM_ARM11_cntX" per_cpu="yes"> 6 <category name="ARM11" counter_set="ARM_ARM11_cntX" per_cpu="yes">
7 <event counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 7 <event counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
8 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/> 8 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
9 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/> 9 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
10 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/> 10 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
11 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/> 11 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
12 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/> 12 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
13 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/> 13 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/>
14 <event event="0x06" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mis-predicted"/> 14 <event event="0x06" title="Branch" name="Mispredicted" description="Branch mis-predicted"/>
15 <event event="0x07" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instructions executed"/> 15 <event event="0x07" title="Instruction" name="Executed" description="Instructions executed"/>
16 <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/> 16 <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/>
17 <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/> 17 <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/>
18 <event event="0x0b" title="Cache" name="Data miss" alias="L1Miss" description="Data cache miss, not including Cache Operations"/> 18 <event event="0x0b" title="Cache" name="Data miss" description="Data cache miss, not including Cache Operations"/>
19 <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/> 19 <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/>
20 <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/> 20 <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/>
21 <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/> 21 <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/>
22 <event event="0x10" title="External" name="Access" description="Explicit external data or peripheral access"/> 22 <event event="0x10" title="External" name="Access" description="Explicit external data or peripheral access"/>
23 <event event="0x11" title="Cache" name="Data miss" description="Stall because of Load Store Unit request queue being full"/> 23 <event event="0x11" title="Cache" name="Data miss" description="Stall because of Load Store Unit request queue being full"/>
24 <event event="0x12" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation"/> 24 <event event="0x12" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation"/>
25 <event event="0x13" title="Disable Interrupts" name="FIQ" description="The number of cycles which FIQ interrupts are disabled (ARM1156 only)"/> 25 <event event="0x13" title="Disable Interrupts" name="FIQ" description="The number of cycles which FIQ interrupts are disabled (ARM1156 only)"/>
26 <event event="0x14" title="Disable Interrupts" name="IRQ" description="The number of cycles which IRQ interrupts are disabled (ARM1156 only)"/> 26 <event event="0x14" title="Disable Interrupts" name="IRQ" description="The number of cycles which IRQ interrupts are disabled (ARM1156 only)"/>
27 <event event="0x20" title="ETM" name="ETMEXTOUT[0]" description="ETMEXTOUT[0] signal was asserted for a cycle"/> 27 <event event="0x20" title="ETM" name="ETMEXTOUT[0]" description="ETMEXTOUT[0] signal was asserted for a cycle"/>
28 <event event="0x21" title="ETM" name="ETMEXTOUT[1]" description="ETMEXTOUT[1] signal was asserted for a cycle"/> 28 <event event="0x21" title="ETM" name="ETMEXTOUT[1]" description="ETMEXTOUT[1] signal was asserted for a cycle"/>
29 <event event="0x22" title="ETM" name="ETMEXTOUT[0,1]" description="ETMEXTOUT[0] or ETMEXTOUT[1] was asserted"/> 29 <event event="0x22" title="ETM" name="ETMEXTOUT[0,1]" description="ETMEXTOUT[0] or ETMEXTOUT[1] was asserted"/>
30 <event event="0x23" title="Procedure" name="Calls" description="Procedure call instruction executed"/> 30 <event event="0x23" title="Procedure" name="Calls" description="Procedure call instruction executed"/>
31 <event event="0x24" title="Procedure" name="Returns" description="Procedure return instruction executed"/> 31 <event event="0x24" title="Procedure" name="Returns" description="Procedure return instruction executed"/>
32 <event event="0x25" title="Procedure" name="Return and predicted" description="Procedure return instruction executed and return address predicted"/> 32 <event event="0x25" title="Procedure" name="Return and predicted" description="Procedure return instruction executed and return address predicted"/>
33 <event event="0x26" title="Procedure" name="Return and mispredicted" description="Procedure return instruction executed and return address predicted incorrectly"/> 33 <event event="0x26" title="Procedure" name="Return and mispredicted" description="Procedure return instruction executed and return address predicted incorrectly"/>
34 <event event="0x30" title="Cache" name="Inst tag or parity error" description="Instruction cache Tag or Valid RAM parity error (ARM1156 only)"/> 34 <event event="0x30" title="Cache" name="Inst tag or parity error" description="Instruction cache Tag or Valid RAM parity error (ARM1156 only)"/>
35 <event event="0x31" title="Cache" name="Inst parity error" description="Instruction cache RAM parity error (ARM1156 only)"/> 35 <event event="0x31" title="Cache" name="Inst parity error" description="Instruction cache RAM parity error (ARM1156 only)"/>
36 <event event="0x32" title="Cache" name="Data tag or parity error" description="Data cache Tag or Valid RAM parity error (ARM1156 only)"/> 36 <event event="0x32" title="Cache" name="Data tag or parity error" description="Data cache Tag or Valid RAM parity error (ARM1156 only)"/>
37 <event event="0x33" title="Cache" name="Data parity error" description="Data cache RAM parity error (ARM1156 only)"/> 37 <event event="0x33" title="Cache" name="Data parity error" description="Data cache RAM parity error (ARM1156 only)"/>
38 <event event="0x34" title="ITCM" name="Error" description="ITCM error (ARM1156 only)"/> 38 <event event="0x34" title="ITCM" name="Error" description="ITCM error (ARM1156 only)"/>
39 <event event="0x35" title="DTCM" name="Error" description="DTCM error (ARM1156 only)"/> 39 <event event="0x35" title="DTCM" name="Error" description="DTCM error (ARM1156 only)"/>
40 <event event="0x36" title="Procedure" name="Return address pop" description="Procedure return address popped off the return stack (ARM1156 only)"/> 40 <event event="0x36" title="Procedure" name="Return address pop" description="Procedure return address popped off the return stack (ARM1156 only)"/>
41 <event event="0x37" title="Procedure" name="Return address misprediction" description="Procedure return address popped off the return stack has been incorrectly predicted by the PFU (ARM1156 only)"/> 41 <event event="0x37" title="Procedure" name="Return address misprediction" description="Procedure return address popped off the return stack has been incorrectly predicted by the PFU (ARM1156 only)"/>
42 <event event="0x38" title="Cache" name="Data dirty parity error" description="Data cache Dirty RAM parity error (ARM1156 only)"/> 42 <event event="0x38" title="Cache" name="Data dirty parity error" description="Data cache Dirty RAM parity error (ARM1156 only)"/>
43 </category> 43 </category>
diff --git a/daemon/events-ARM11MPCore.xml b/daemon/events-ARM11MPCore.xml
index 74a29e6..7de51b0 100644
--- a/daemon/events-ARM11MPCore.xml
+++ b/daemon/events-ARM11MPCore.xml
@@ -4,7 +4,7 @@
4 <counter name="ARM_ARM11MPCore_cnt2"/> 4 <counter name="ARM_ARM11MPCore_cnt2"/>
5 </counter_set> 5 </counter_set>
6 <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cntX" per_cpu="yes"> 6 <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cntX" per_cpu="yes">
7 <event counter="ARM_ARM11MPCore_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 7 <event counter="ARM_ARM11MPCore_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
8 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/> 8 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
9 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/> 9 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
10 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/> 10 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
@@ -12,11 +12,11 @@
12 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/> 12 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
13 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instructions executed, branch might or might not have changed program flow"/> 13 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instructions executed, branch might or might not have changed program flow"/>
14 <event event="0x06" title="Branch" name="Not predicted" description="Branch not predicted"/> 14 <event event="0x06" title="Branch" name="Not predicted" description="Branch not predicted"/>
15 <event event="0x07" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted"/> 15 <event event="0x07" title="Branch" name="Mispredicted" description="Branch mispredicted"/>
16 <event event="0x08" title="Core" name="Instructions" alias="InstructionsExecuted" description="Instructions executed"/> 16 <event event="0x08" title="Core" name="Instructions" description="Instructions executed"/>
17 <event event="0x09" title="Core" name="Folded Instructions" description="Folded instructions executed"/> 17 <event event="0x09" title="Core" name="Folded Instructions" description="Folded instructions executed"/>
18 <event event="0x0a" title="Cache" name="Data read access" description="Data cache read access, not including cache operations"/> 18 <event event="0x0a" title="Cache" name="Data read access" description="Data cache read access, not including cache operations"/>
19 <event event="0x0b" title="Cache" name="Data read miss" alias="L1Miss" description="Data cache miss, not including Cache Operations"/> 19 <event event="0x0b" title="Cache" name="Data read miss" description="Data cache miss, not including Cache Operations"/>
20 <event event="0x0c" title="Cache" name="Data write access" description="Data cache write access"/> 20 <event event="0x0c" title="Cache" name="Data write access" description="Data cache write access"/>
21 <event event="0x0d" title="Cache" name="Data write miss" description="Data cache write miss"/> 21 <event event="0x0d" title="Cache" name="Data write miss" description="Data cache write miss"/>
22 <event event="0x0e" title="Cache" name="Data line eviction" description="Data cache line eviction, not including cache operations"/> 22 <event event="0x0e" title="Cache" name="Data line eviction" description="Data cache line eviction, not including cache operations"/>
diff --git a/daemon/events-Cortex-A15.xml b/daemon/events-Cortex-A15.xml
index 74c7290..d6222eb 100644
--- a/daemon/events-Cortex-A15.xml
+++ b/daemon/events-Cortex-A15.xml
@@ -1,76 +1,76 @@
1 <counter_set name="ARM_Cortex-A15_cntX"> 1 <counter_set name="ARM_Cortex-A15_cntX">
2 <counter name="ARM_Cortex-A15_cnt0"/> 2 <counter name="ARM_Cortex-A15_cnt0"/>
3 <counter name="ARM_Cortex-A15_cnt1"/> 3 <counter name="ARM_Cortex-A15_cnt1"/>
4 <counter name="ARM_Cortex-A15_cnt2"/> 4 <counter name="ARM_Cortex-A15_cnt2"/>
5 <counter name="ARM_Cortex-A15_cnt3"/> 5 <counter name="ARM_Cortex-A15_cnt3"/>
6 <counter name="ARM_Cortex-A15_cnt4"/> 6 <counter name="ARM_Cortex-A15_cnt4"/>
7 <counter name="ARM_Cortex-A15_cnt5"/> 7 <counter name="ARM_Cortex-A15_cnt5"/>
8 </counter_set> 8 </counter_set>
9 <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cntX" per_cpu="yes" event_based_sampling="yes"> 9 <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cntX" per_cpu="yes" event_based_sampling="yes">
10 <event counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 10 <event counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
11 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> 11 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
12 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 12 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
13 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 13 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
14 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 14 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
15 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 15 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
21 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 21 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
22 <event event="0x11" title="Cycle" name="Cycle" description=""/> 22 <event event="0x11" title="Cycle" name="Cycle" description=""/>
23 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 23 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
24 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/> 24 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
25 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/> 25 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
26 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/> 26 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
27 <event event="0x16" title="Cache" name="L2 data access" alias="L1Miss" description="Level 2 data cache access"/> 27 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
28 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/> 28 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
29 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/> 29 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
30 <event event="0x19" title="Bus" name="Access" description=""/> 30 <event event="0x19" title="Bus" name="Access" description=""/>
31 <event event="0x1a" title="Memory" name="Error" description="Local memory error"/> 31 <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
32 <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/> 32 <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
33 <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/> 33 <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
34 <event event="0x1d" title="Bus" name="Cycle" description=""/> 34 <event event="0x1d" title="Bus" name="Cycle" description=""/>
35 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/> 35 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
36 <event event="0x41" title="Cache" name="L1 data write" description="Level 1 data cache access - Write"/> 36 <event event="0x41" title="Cache" name="L1 data write" description="Level 1 data cache access - Write"/>
37 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/> 37 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
38 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/> 38 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
39 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/> 39 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>
40 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/> 40 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>
41 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/> 41 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
42 <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/> 42 <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
43 <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/> 43 <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
44 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/> 44 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
45 <event event="0x51" title="Cache" name="L2 data write" description="Level 2 data cache access - Write"/> 45 <event event="0x51" title="Cache" name="L2 data write" description="Level 2 data cache access - Write"/>
46 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/> 46 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
47 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/> 47 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
48 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/> 48 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
49 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/> 49 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
50 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/> 50 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
51 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/> 51 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
52 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/> 52 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
53 <event event="0x64" title="Bus" name="Access" description="Bus access - Normal"/> 53 <event event="0x64" title="Bus" name="Access" description="Bus access - Normal"/>
54 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/> 54 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
55 <event event="0x66" title="Memory" name="Read" alias="MemoryRead" description="Data memory access - Read"/> 55 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
56 <event event="0x67" title="Memory" name="Write" alias="MemoryWrite" description="Data memory access - Write"/> 56 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
57 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/> 57 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
58 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/> 58 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
59 <event event="0x6a" title="Memory" name="Unaligned" alias="UnalignedAccess" description="Unaligned access"/> 59 <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
60 <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/> 60 <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
61 <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/> 61 <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
62 <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/> 62 <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
63 <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/> 63 <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/>
64 <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/> 64 <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/>
65 <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/> 65 <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
66 <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/> 66 <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
67 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/> 67 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
68 <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/> 68 <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
69 <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/> 69 <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
70 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/> 70 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
71 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/> 71 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
72 <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/> 72 <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
73 <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/> 73 <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
74 <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/> 74 <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
75 <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/> 75 <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
76 </category> 76 </category>
diff --git a/daemon/events-Cortex-A5.xml b/daemon/events-Cortex-A5.xml
index 0a70a62..e01492b 100644
--- a/daemon/events-Cortex-A5.xml
+++ b/daemon/events-Cortex-A5.xml
@@ -1,39 +1,39 @@
1 <counter_set name="ARM_Cortex-A5_cntX"> 1 <counter_set name="ARM_Cortex-A5_cntX">
2 <counter name="ARM_Cortex-A5_cnt0"/> 2 <counter name="ARM_Cortex-A5_cnt0"/>
3 <counter name="ARM_Cortex-A5_cnt1"/> 3 <counter name="ARM_Cortex-A5_cnt1"/>
4 </counter_set> 4 </counter_set>
5 <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cntX" per_cpu="yes" event_based_sampling="yes"> 5 <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cntX" per_cpu="yes" event_based_sampling="yes">
6 <event counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 6 <event counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
7 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 7 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
9 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 9 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
10 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 10 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
11 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 11 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
12 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 12 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
13 <event event="0x06" title="Instruction" name="Memory read" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 13 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
14 <event event="0x07" title="Instruction" name="Memory write" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 14 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
15 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 15 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
16 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 16 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
17 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 17 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
18 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 18 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
19 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/> 19 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
20 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 20 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
21 <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/> 21 <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
22 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 22 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
23 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 23 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
24 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 24 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
25 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/> 25 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
26 <event event="0x14" title="Cache" name="Instruction access" description="Instruction cache access"/> 26 <event event="0x14" title="Cache" name="Instruction access" description="Instruction cache access"/>
27 <event event="0x15" title="Cache" name="Data eviction" description="Data cache eviction"/> 27 <event event="0x15" title="Cache" name="Data eviction" description="Data cache eviction"/>
28 <event event="0x86" title="Interrupts" name="IRQ" description="IRQ exception taken"/> 28 <event event="0x86" title="Interrupts" name="IRQ" description="IRQ exception taken"/>
29 <event event="0x87" title="Interrupts" name="FIQ" description="FIQ exception taken"/> 29 <event event="0x87" title="Interrupts" name="FIQ" description="FIQ exception taken"/>
30 <event event="0xC0" title="Memory" name="External request" description="External memory request"/> 30 <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
31 <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/> 31 <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
32 <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/> 32 <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
33 <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/> 33 <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
34 <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/> 34 <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
35 <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/> 35 <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
36 <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/> 36 <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/>
37 <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/> 37 <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/>
38 <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/> 38 <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
39 </category> 39 </category>
diff --git a/daemon/events-Cortex-A7.xml b/daemon/events-Cortex-A7.xml
index 1a55817..9ee4580 100755..100644
--- a/daemon/events-Cortex-A7.xml
+++ b/daemon/events-Cortex-A7.xml
@@ -1,49 +1,49 @@
1 <counter_set name="ARM_Cortex-A7_cntX"> 1 <counter_set name="ARM_Cortex-A7_cntX">
2 <counter name="ARM_Cortex-A7_cnt0"/> 2 <counter name="ARM_Cortex-A7_cnt0"/>
3 <counter name="ARM_Cortex-A7_cnt1"/> 3 <counter name="ARM_Cortex-A7_cnt1"/>
4 <counter name="ARM_Cortex-A7_cnt2"/> 4 <counter name="ARM_Cortex-A7_cnt2"/>
5 <counter name="ARM_Cortex-A7_cnt3"/> 5 <counter name="ARM_Cortex-A7_cnt3"/>
6 </counter_set> 6 </counter_set>
7 <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cntX" per_cpu="yes" event_based_sampling="yes"> 7 <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cntX" per_cpu="yes" event_based_sampling="yes">
8 <event counter="ARM_Cortex-A7_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 8 <event counter="ARM_Cortex-A7_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
9 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> 9 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
15 <event event="0x06" title="Memory" name="Data Read" alias="MemoryRead" description="Data read architecturally executed"/> 15 <event event="0x06" title="Memory" name="Data Read" description="Data read architecturally executed"/>
16 <event event="0x07" title="Memory" name="Data Write" alias="MemoryWrite" description="Data write architecturally executed"/> 16 <event event="0x07" title="Memory" name="Data Write" description="Data write architecturally executed"/>
17 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
21 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/> 21 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
23 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 23 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
24 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 24 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
25 <event event="0x11" title="Cycle" name="Counter" description=""/> 25 <event event="0x11" title="Cycle" name="Counter" description=""/>
26 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
27 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/> 27 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
28 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/> 28 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
29 <event event="0x15" title="Cache" name="L1 data eviction" description="Level 1 data cache eviction"/> 29 <event event="0x15" title="Cache" name="L1 data eviction" description="Level 1 data cache eviction"/>
30 <event event="0x16" title="Cache" name="L2 data access" alias="L1Miss" description="Level 2 data cache access"/> 30 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
31 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/> 31 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
32 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/> 32 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
33 <event event="0x19" title="Bus" name="Access" description=""/> 33 <event event="0x19" title="Bus" name="Access" description=""/>
34 <event event="0x1d" title="Bus" name="Cycle" description=""/> 34 <event event="0x1d" title="Bus" name="Cycle" description=""/>
35 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/> 35 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
36 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/> 36 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
37 <event event="0x86" title="Exception" name="IRQ" description="IRQ exception taken"/> 37 <event event="0x86" title="Exception" name="IRQ" description="IRQ exception taken"/>
38 <event event="0x87" title="Exception" name="FIQ" description="FIQ exception taken"/> 38 <event event="0x87" title="Exception" name="FIQ" description="FIQ exception taken"/>
39 <event event="0xC0" title="Memory" name="External request" description="External memory request"/> 39 <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
40 <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/> 40 <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
41 <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/> 41 <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
42 <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/> 42 <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
43 <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/> 43 <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
44 <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/> 44 <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
45 <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/> 45 <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/>
46 <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/> 46 <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/>
47 <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/> 47 <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
48 <event event="0xCA" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local cluster, rather than accessing the L2 cache or issuing an external read."/> 48 <event event="0xCA" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local cluster, rather than accessing the L2 cache or issuing an external read."/>
49 </category> 49 </category>
diff --git a/daemon/events-Cortex-A8.xml b/daemon/events-Cortex-A8.xml
index 02260ba..1981c36 100644
--- a/daemon/events-Cortex-A8.xml
+++ b/daemon/events-Cortex-A8.xml
@@ -1,57 +1,57 @@
1 <counter_set name="ARM_Cortex-A8_cntX"> 1 <counter_set name="ARM_Cortex-A8_cntX">
2 <counter name="ARM_Cortex-A8_cnt0"/> 2 <counter name="ARM_Cortex-A8_cnt0"/>
3 <counter name="ARM_Cortex-A8_cnt1"/> 3 <counter name="ARM_Cortex-A8_cnt1"/>
4 <counter name="ARM_Cortex-A8_cnt2"/> 4 <counter name="ARM_Cortex-A8_cnt2"/>
5 <counter name="ARM_Cortex-A8_cnt3"/> 5 <counter name="ARM_Cortex-A8_cnt3"/>
6 </counter_set> 6 </counter_set>
7 <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cntX" per_cpu="yes" event_based_sampling="yes"> 7 <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cntX" per_cpu="yes" event_based_sampling="yes">
8 <event counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 8 <event counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
15 <event event="0x06" title="Instruction" name="Memory read" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 15 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
16 <event event="0x07" title="Instruction" name="Memory write" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 16 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
17 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
21 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/> 21 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
23 <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/> 23 <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
24 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 24 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
25 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 25 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
26 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
27 <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/> 27 <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>
28 <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/> 28 <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>
29 <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/> 29 <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>
30 <event event="0x43" title="Cache" name="L1 miss" alias="L1Miss" description="Any accesses to the L2 cache"/> 30 <event event="0x43" title="Cache" name="L1 miss" description="Any accesses to the L2 cache"/>
31 <event event="0x44" title="Cache" name="L2 miss" alias="L2Miss" description="Any cacheable miss in the L2 cache"/> 31 <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>
32 <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/> 32 <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>
33 <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/> 33 <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>
34 <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/> 34 <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/>
35 <event event="0x48" title="Memory" name="Unaligned access" description="Any unaligned memory access that results in a replay"/> 35 <event event="0x48" title="Memory" name="Unaligned access" description="Any unaligned memory access that results in a replay"/>
36 <event event="0x49" title="Cache" name="L1 data hash miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/> 36 <event event="0x49" title="Cache" name="L1 data hash miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/>
37 <event event="0x4a" title="Cache" name="L1 inst hash miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/> 37 <event event="0x4a" title="Cache" name="L1 inst hash miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/>
38 <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/> 38 <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/>
39 <event event="0x4c" title="NEON" name="L1 cache hit" description="Any NEON access that hits in the L1 data cache"/> 39 <event event="0x4c" title="NEON" name="L1 cache hit" description="Any NEON access that hits in the L1 data cache"/>
40 <event event="0x4d" title="NEON" name="L1 cache access" description="Any NEON cacheable data accesses for L1 data cache"/> 40 <event event="0x4d" title="NEON" name="L1 cache access" description="Any NEON cacheable data accesses for L1 data cache"/>
41 <event event="0x4e" title="NEON" name="L2 cache access" description="Any L2 cache accesses as a result of a NEON memory access"/> 41 <event event="0x4e" title="NEON" name="L2 cache access" description="Any L2 cache accesses as a result of a NEON memory access"/>
42 <event event="0x4f" title="NEON" name="L2 cache hit" description="Any NEON hit in the L2 cache"/> 42 <event event="0x4f" title="NEON" name="L2 cache hit" description="Any NEON hit in the L2 cache"/>
43 <event event="0x50" title="Cache" name="L1 inst access" description="Any L1 instruction cache access, excluding CP15 cache accesses"/> 43 <event event="0x50" title="Cache" name="L1 inst access" description="Any L1 instruction cache access, excluding CP15 cache accesses"/>
44 <event event="0x51" title="Branch" name="Return stack misprediction" description="Any return stack misprediction because of incorrect target address for a taken return stack pop"/> 44 <event event="0x51" title="Branch" name="Return stack misprediction" description="Any return stack misprediction because of incorrect target address for a taken return stack pop"/>
45 <event event="0x52" title="Branch" name="Direction misprediction" description="Branch direction misprediction"/> 45 <event event="0x52" title="Branch" name="Direction misprediction" description="Branch direction misprediction"/>
46 <event event="0x53" title="Branch" name="Taken prediction" description="Any predictable branch that is predicted to be taken"/> 46 <event event="0x53" title="Branch" name="Taken prediction" description="Any predictable branch that is predicted to be taken"/>
47 <event event="0x54" title="Branch" name="Executed and taken prediction" description="Any predictable branch that is executed and taken"/> 47 <event event="0x54" title="Branch" name="Executed and taken prediction" description="Any predictable branch that is executed and taken"/>
48 <event event="0x55" title="Core" name="Operations issued" description="Number of operations issued, where an operation is either: an instruction or one operation in a sequence of operations that make up a multi-cycle instruction"/> 48 <event event="0x55" title="Core" name="Operations issued" description="Number of operations issued, where an operation is either: an instruction or one operation in a sequence of operations that make up a multi-cycle instruction"/>
49 <event event="0x56" title="Core" name="No issue cycles" description="Increment for every cycle that no instructions are available for issue"/> 49 <event event="0x56" title="Core" name="No issue cycles" description="Increment for every cycle that no instructions are available for issue"/>
50 <event event="0x57" title="Core" name="Issue cycles" description="For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once"/> 50 <event event="0x57" title="Core" name="Issue cycles" description="For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once"/>
51 <event event="0x58" title="NEON" name="MRC data wait" description="Number of cycles the processor stalls waiting on MRC data from NEON"/> 51 <event event="0x58" title="NEON" name="MRC data wait" description="Number of cycles the processor stalls waiting on MRC data from NEON"/>
52 <event event="0x59" title="NEON" name="Full queue" description="Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue"/> 52 <event event="0x59" title="NEON" name="Full queue" description="Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue"/>
53 <event event="0x5a" title="NEON" name="Idle" description="Number of cycles that NEON and integer processors are both not idle"/> 53 <event event="0x5a" title="NEON" name="Idle" description="Number of cycles that NEON and integer processors are both not idle"/>
54 <event event="0x70" title="External" name="PMUEXTIN[0]" description="Counts any event from external input source PMUEXTIN[0]"/> 54 <event event="0x70" title="External" name="PMUEXTIN[0]" description="Counts any event from external input source PMUEXTIN[0]"/>
55 <event event="0x71" title="External" name="PMUEXTIN[1]" description="Counts any event from external input source PMUEXTIN[1]"/> 55 <event event="0x71" title="External" name="PMUEXTIN[1]" description="Counts any event from external input source PMUEXTIN[1]"/>
56 <event event="0x72" title="External" name="PMUEXTIN[0,1]" description="Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"/> 56 <event event="0x72" title="External" name="PMUEXTIN[0,1]" description="Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"/>
57 </category> 57 </category>
diff --git a/daemon/events-Cortex-A9.xml b/daemon/events-Cortex-A9.xml
index 363862c..faccb2f 100644
--- a/daemon/events-Cortex-A9.xml
+++ b/daemon/events-Cortex-A9.xml
@@ -1,66 +1,72 @@
1 <counter_set name="ARM_Cortex-A9_cntX"> 1 <counter_set name="ARM_Cortex-A9_cntX">
2 <counter name="ARM_Cortex-A9_cnt0"/> 2 <counter name="ARM_Cortex-A9_cnt0"/>
3 <counter name="ARM_Cortex-A9_cnt1"/> 3 <counter name="ARM_Cortex-A9_cnt1"/>
4 <counter name="ARM_Cortex-A9_cnt2"/> 4 <counter name="ARM_Cortex-A9_cnt2"/>
5 <counter name="ARM_Cortex-A9_cnt3"/> 5 <counter name="ARM_Cortex-A9_cnt3"/>
6 <counter name="ARM_Cortex-A9_cnt4"/> 6 <counter name="ARM_Cortex-A9_cnt4"/>
7 <counter name="ARM_Cortex-A9_cnt5"/> 7 <counter name="ARM_Cortex-A9_cnt5"/>
8 </counter_set> 8 </counter_set>
9 <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cntX" per_cpu="yes" event_based_sampling="yes"> 9 <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cntX" per_cpu="yes" event_based_sampling="yes">
10 <event counter="ARM_Cortex-A9_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 10 <event counter="ARM_Cortex-A9_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
11 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 11 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
12 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 12 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
13 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 13 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
14 <event event="0x03" title="Cache" name="Data refill" alias="DataRefill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 14 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
15 <event event="0x04" title="Cache" name="Data access" alias="DataAccess" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 15 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <event event="0x06" title="Instruction" name="Memory read" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 17 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
18 <event event="0x07" title="Instruction" name="Memory write" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 18 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
19 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 19 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
20 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 20 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
21 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 21 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
22 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/> 22 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
23 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 23 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
24 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 24 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
25 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 25 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
26 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
27 <event event="0x40" title="Java" name="Bytecode execute" description="Counts the number of Java bytecodes being decoded, including speculative ones"/> 27 <event event="0x40" title="Java" name="Bytecode execute" description="Counts the number of Java bytecodes being decoded, including speculative ones"/>
28 <event event="0x41" title="Java" name="SW bytecode execute" description="Counts the number of software java bytecodes being decoded, including speculative ones"/> 28 <event event="0x41" title="Java" name="SW bytecode execute" description="Counts the number of software java bytecodes being decoded, including speculative ones"/>
29 <event event="0x42" title="Jazelle" name="Backward branch execute" description="Counts the number of Jazelle taken branches being executed"/> 29 <event event="0x42" title="Jazelle" name="Backward branch execute" description="Counts the number of Jazelle taken branches being executed"/>
30 <event event="0x50" title="Cache" name="Coherency miss" alias="L1CoherencyMiss" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which also miss in all the other Cortex-A9 processors, meaning that the request is sent to the external memory"/> 30 <event event="0x50" title="Cache" name="Coherency miss" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which also miss in all the other Cortex-A9 processors, meaning that the request is sent to the external memory"/>
31 <event event="0x51" title="Cache" name="Coherency hit" alias="L1CoherencyHit" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which hit in another Cortex-A9 processor, meaning that the linefill data is fetched directly from the relevant Cortex-A9 cache"/> 31 <event event="0x51" title="Cache" name="Coherency hit" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which hit in another Cortex-A9 processor, meaning that the linefill data is fetched directly from the relevant Cortex-A9 cache"/>
32 <event event="0x60" title="Cache" name="Inst dependent stall" description="Counts the number of cycles where the processor is ready to accept new instructions, but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill"/> 32 <event event="0x60" title="Cache" name="Inst dependent stall" description="Counts the number of cycles where the processor is ready to accept new instructions, but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill"/>
33 <event event="0x61" title="Cache" name="Data dependent stall" description="Counts the number of cycles where the core has some instructions that it cannot issue to any pipeline, and the Load Store unit has at least one pending linefill request, and no pending TLB requests"/> 33 <event event="0x61" title="Cache" name="Data dependent stall" description="Counts the number of cycles where the core has some instructions that it cannot issue to any pipeline, and the Load Store unit has at least one pending linefill request, and no pending TLB requests"/>
34 <event event="0x62" title="Cache" name="TLB stall" description="Counts the number of cycles where the processor is stalled waiting for the completion of translation table walks from the main TLB"/> 34 <event event="0x62" title="Cache" name="TLB stall" description="Counts the number of cycles where the processor is stalled waiting for the completion of translation table walks from the main TLB"/>
35 <event event="0x63" title="Intrinsic" name="STREX pass" description="Counts the number of STREX instructions architecturally executed and passed"/> 35 <event event="0x63" title="Intrinsic" name="STREX pass" description="Counts the number of STREX instructions architecturally executed and passed"/>
36 <event event="0x64" title="Intrinsic" name="STREX fail" description="Counts the number of STREX instructions architecturally executed and failed"/> 36 <event event="0x64" title="Intrinsic" name="STREX fail" description="Counts the number of STREX instructions architecturally executed and failed"/>
37 <event event="0x65" title="Cache" name="Data eviction" description="Counts the number of eviction requests because of a linefill in the data cache"/> 37 <event event="0x65" title="Cache" name="Data eviction" description="Counts the number of eviction requests because of a linefill in the data cache"/>
38 <event event="0x66" title="Pipeline" name="Issue stage no dispatch" description="Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions"/> 38 <event event="0x66" title="Pipeline" name="Issue stage no dispatch" description="Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions"/>
39 <event event="0x67" title="Pipeline" name="Issue stage empty" description="Counts the number of cycles where the issue stage is empty"/> 39 <event event="0x67" title="Pipeline" name="Issue stage empty" description="Counts the number of cycles where the issue stage is empty"/>
40 <event event="0x68" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/> 40 <event event="0x68" title="Instruction" name="Executed" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>
41 <event event="0x6E" title="Core" name="Functions" description="Counts the number of procedure returns whose condition codes do not fail, excluding all returns from exception"/> 41 <event event="0x69" title="Cache" name="Data linefills" description="Counts the number of linefills performed on the external AXI bus"/>
42 <event event="0x70" title="Instruction" name="Main execution unit" description="Counts the number of instructions being executed in the main execution pipeline of the processor, the multiply pipeline and arithmetic logic unit pipeline"/> 42 <event event="0x6A" title="Cache" name="Prefetch linefills" description="Counts the number of data linefills caused by prefetcher requests"/>
43 <event event="0x71" title="Instruction" name="Second execution unit" description="Counts the number of instructions being executed in the processor second execution pipeline (ALU)"/> 43 <event event="0x6B" title="Cache" name="Prefetch hits" description="Counts the number of cache hits in a line that belongs to a stream followed by the prefetcher"/>
44 <event event="0x72" title="Instruction" name="Load/Store" description="Counts the number of instructions being executed in the Load/Store unit"/> 44 <event event="0x6E" title="Core" name="Functions" description="Counts the number of procedure returns whose condition codes do not fail, excluding all returns from exception"/>
45 <event event="0x73" title="Instruction" name="Floating point" description="Counts the number of Floating-point instructions going through the Register Rename stage"/> 45 <event event="0x70" title="Instruction" name="Main execution unit" description="Counts the number of instructions being executed in the main execution pipeline of the processor, the multiply pipeline and arithmetic logic unit pipeline"/>
46 <event event="0x74" title="Instruction" name="NEON" description="Counts the number of NEON instructions going through the Register Rename stage"/> 46 <event event="0x71" title="Instruction" name="Second execution unit" description="Counts the number of instructions being executed in the processor second execution pipeline (ALU)"/>
47 <event event="0x80" title="Stalls" name="PLD" description="Counts the number of cycles where the processor is stalled because PLD slots are all full"/> 47 <event event="0x72" title="Instruction" name="Load/Store" description="Counts the number of instructions being executed in the Load/Store unit"/>
48 <event event="0x81" title="Stalls" name="Memory write" description="Counts the number of cycles when the processor is stalled and the data side is stalled too because it is full and executing writes to the external memory"/> 48 <event event="0x73" title="Instruction" name="Floating point" description="Counts the number of Floating-point instructions going through the Register Rename stage"/>
49 <event event="0x82" title="Stalls" name="Inst main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side"/> 49 <event event="0x74" title="Instruction" name="NEON" description="Counts the number of NEON instructions going through the Register Rename stage"/>
50 <event event="0x83" title="Stalls" name="Data main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the data side"/> 50 <event event="0x80" title="Stalls" name="PLD" description="Counts the number of cycles where the processor is stalled because PLD slots are all full"/>
51 <event event="0x84" title="Stalls" name="Inst micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the instruction side"/> 51 <event event="0x81" title="Stalls" name="Memory write" description="Counts the number of cycles when the processor is stalled and the data side is stalled too because it is full and executing writes to the external memory"/>
52 <event event="0x85" title="Stalls" name="Data micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the data side"/> 52 <event event="0x82" title="Stalls" name="Inst main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side"/>
53 <event event="0x86" title="Stalls" name="DMB" description="Counts the number of stall cycles because of the execution of a DMB memory barrier"/> 53 <event event="0x83" title="Stalls" name="Data main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the data side"/>
54 <event event="0x8A" title="Clock" name="Integer core" description="Counts the number of cycles during which the integer core clock is enabled"/> 54 <event event="0x84" title="Stalls" name="Inst micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the instruction side"/>
55 <event event="0x8B" title="Clock" name="Data engine" description="Counts the number of cycles during which the Data Engine clock is enabled"/> 55 <event event="0x85" title="Stalls" name="Data micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the data side"/>
56 <event event="0x90" title="Instruction" name="ISB" description="Counts the number of ISB instructions architecturally executed"/> 56 <event event="0x86" title="Stalls" name="DMB" description="Counts the number of stall cycles because of the execution of a DMB memory barrier"/>
57 <event event="0x91" title="Instruction" name="DSB" description="Counts the number of DSB instructions architecturally executed"/> 57 <event event="0x8A" title="Clock" name="Integer core" description="Counts the number of cycles during which the integer core clock is enabled"/>
58 <event event="0x92" title="Instruction" name="DMB" description="Counts the number of DMB instructions speculatively executed"/> 58 <event event="0x8B" title="Clock" name="Data engine" description="Counts the number of cycles during which the Data Engine clock is enabled"/>
59 <event event="0x93" title="External" name="Interrupts" description="Counts the number of external interrupts executed by the processor"/> 59 <event event="0x8C" title="Clock" name="NEON" description="Counts the number of cycles when the NEON SIMD clock is enabled"/>
60 <event event="0xA0" title="PLE" name="Cache line rq completed" description="Counts the number of PLE cache line requests completed"/> 60 <event event="0x8D" title="Memory" name="TLB inst allocations" description="Counts the number of TLB allocations because of Instruction requests"/>
61 <event event="0xA1" title="PLE" name="Cache line rq skipped" description="Counts the number of PLE cache line requests skipped"/> 61 <event event="0x8E" title="Memory" name="TLB data allocations" description="Counts the number of TLB allocations because of Data requests"/>
62 <event event="0xA2" title="PLE" name="FIFO flush" description="Counts the number of PLE FIFO flush requests"/> 62 <event event="0x90" title="Instruction" name="ISB" description="Counts the number of ISB instructions architecturally executed"/>
63 <event event="0xA3" title="PLE" name="Request completed" description="Counts the number of PLE FIFO flush completed"/> 63 <event event="0x91" title="Instruction" name="DSB" description="Counts the number of DSB instructions architecturally executed"/>
64 <event event="0xA4" title="PLE" name="FIFO overflow" description="Counts the number of PLE FIFO flush overflowed"/> 64 <event event="0x92" title="Instruction" name="DMB" description="Counts the number of DMB instructions speculatively executed"/>
65 <event event="0xA5" title="PLE" name="Request programmed" description="Counts the number of PLE FIFO flush program requests"/> 65 <event event="0x93" title="External" name="Interrupts" description="Counts the number of external interrupts executed by the processor"/>
66 </category> 66 <event event="0xA0" title="PLE" name="Cache line rq completed" description="Counts the number of PLE cache line requests completed"/>
67 <event event="0xA1" title="PLE" name="Cache line rq skipped" description="Counts the number of PLE cache line requests skipped"/>
68 <event event="0xA2" title="PLE" name="FIFO flush" description="Counts the number of PLE FIFO flush requests"/>
69 <event event="0xA3" title="PLE" name="Request completed" description="Counts the number of PLE FIFO flush completed"/>
70 <event event="0xA4" title="PLE" name="FIFO overflow" description="Counts the number of PLE FIFO flush overflowed"/>
71 <event event="0xA5" title="PLE" name="Request programmed" description="Counts the number of PLE FIFO flush program requests"/>
72 </category>
diff --git a/daemon/events-Krait-architected.xml b/daemon/events-Krait-architected.xml
index cc3f4e5..6f2982e 100755..100644
--- a/daemon/events-Krait-architected.xml
+++ b/daemon/events-Krait-architected.xml
@@ -1,27 +1,27 @@
1 <counter_set name="Krait_cntX"> 1 <counter_set name="Krait_cntX">
2 <counter name="Krait_cnt0"/> 2 <counter name="Krait_cnt0"/>
3 <counter name="Krait_cnt1"/> 3 <counter name="Krait_cnt1"/>
4 <counter name="Krait_cnt2"/> 4 <counter name="Krait_cnt2"/>
5 <counter name="Krait_cnt3"/> 5 <counter name="Krait_cnt3"/>
6 </counter_set> 6 </counter_set>
7 <category name="Krait" counter_set="Krait_cntX" per_cpu="yes"> 7 <category name="Krait" counter_set="Krait_cntX" per_cpu="yes">
8 <event counter="Krait_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 8 <event counter="Krait_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
15 <event event="0x06" title="Instruction" name="Memory read" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 15 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
16 <event event="0x07" title="Instruction" name="Memory write" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 16 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
17 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/> 21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/> 23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
24 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 24 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
25 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 25 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
26 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
27 </category> 27 </category>
diff --git a/daemon/events-L2C-310.xml b/daemon/events-L2C-310.xml
index 35592cf..695b6b8 100644
--- a/daemon/events-L2C-310.xml
+++ b/daemon/events-L2C-310.xml
@@ -1,21 +1,21 @@
1 <counter_set name="L2C-310_cntX"> 1 <counter_set name="L2C-310_cntX">
2 <counter name="L2C-310_cnt0"/> 2 <counter name="L2C-310_cnt0"/>
3 <counter name="L2C-310_cnt1"/> 3 <counter name="L2C-310_cnt1"/>
4 </counter_set> 4 </counter_set>
5 <category name="L2C-310" counter_set="L2C-310_cntX" per_cpu="no"> 5 <category name="L2C-310" counter_set="L2C-310_cntX" per_cpu="no">
6 <event event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOut, of a line from the L2 cache"/> 6 <event event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
7 <event event="0x2" title="L2 Cache" name="DRH" description="Data read hit"/> 7 <event event="0x2" title="L2 Cache" name="DRH" description="Data read hit"/>
8 <event event="0x3" title="L2 Cache" name="DRREQ" description="Data read request"/> 8 <event event="0x3" title="L2 Cache" name="DRREQ" description="Data read request"/>
9 <event event="0x4" title="L2 Cache" name="DWHIT" description="Data write hit"/> 9 <event event="0x4" title="L2 Cache" name="DWHIT" description="Data write hit"/>
10 <event event="0x5" title="L2 Cache" name="DWREQ" description="Data write request"/> 10 <event event="0x5" title="L2 Cache" name="DWREQ" description="Data write request"/>
11 <event event="0x6" title="L2 Cache" name="DWTREQ" description="Data write request with write-through attribute"/> 11 <event event="0x6" title="L2 Cache" name="DWTREQ" description="Data write request with write-through attribute"/>
12 <event event="0x7" title="L2 Cache" name="IRHIT" description="Instruction read hit"/> 12 <event event="0x7" title="L2 Cache" name="IRHIT" description="Instruction read hit"/>
13 <event event="0x8" title="L2 Cache" name="IRREQ" description="Instruction read request"/> 13 <event event="0x8" title="L2 Cache" name="IRREQ" description="Instruction read request"/>
14 <event event="0x9" title="L2 Cache" name="WA" description="Write allocate"/> 14 <event event="0x9" title="L2 Cache" name="WA" description="Write allocate"/>
15 <event event="0xa" title="L2 Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/> 15 <event event="0xa" title="L2 Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
16 <event event="0xb" title="L2 Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/> 16 <event event="0xb" title="L2 Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>
17 <event event="0xc" title="L2 Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/> 17 <event event="0xc" title="L2 Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>
18 <event event="0xd" title="L2 Cache" name="SRRCVD" description="Speculative read received"/> 18 <event event="0xd" title="L2 Cache" name="SRRCVD" description="Speculative read received"/>
19 <event event="0xe" title="L2 Cache" name="SRCONF" description="Speculative read confirmed"/> 19 <event event="0xe" title="L2 Cache" name="SRCONF" description="Speculative read confirmed"/>
20 <event event="0xf" title="L2 Cache" name="EPFRCVD" description="Prefetch hint received"/> 20 <event event="0xf" title="L2 Cache" name="EPFRCVD" description="Prefetch hint received"/>
21 </category> 21 </category>
diff --git a/daemon/events-Linux.xml b/daemon/events-Linux.xml
index 85ce63c..3f626b3 100644
--- a/daemon/events-Linux.xml
+++ b/daemon/events-Linux.xml
@@ -1,17 +1,17 @@
1 <category name="Linux"> 1 <category name="Linux">
2 <event counter="Linux_cpuload_user" title="CPU Load" name="User" per_cpu="yes" description="Scheduler CPU Load of User Application"/> 2 <event counter="Linux_cpuload_user" title="CPU Load" name="User" per_cpu="yes" description="Scheduler CPU Load of User Application"/>
3 <event counter="Linux_cpuload_system" title="CPU Load" name="System" per_cpu="yes" description="Scheduler CPU Load of System Behavior"/> 3 <event counter="Linux_cpuload_system" title="CPU Load" name="System" per_cpu="yes" description="Scheduler CPU Load of System Behavior"/>
4 <event counter="Linux_irq_softirq" title="Interrupts" name="SoftIRQ" per_cpu="yes" description="Linux SoftIRQ taken"/> 4 <event counter="Linux_irq_softirq" title="Interrupts" name="SoftIRQ" per_cpu="yes" description="Linux SoftIRQ taken"/>
5 <event counter="Linux_irq_irq" title="Interrupts" name="IRQ" per_cpu="yes" description="Linux IRQ taken"/> 5 <event counter="Linux_irq_irq" title="Interrupts" name="IRQ" per_cpu="yes" description="Linux IRQ taken"/>
6 <event counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/> 6 <event counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/>
7 <event counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/> 7 <event counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/>
8 <event counter="Linux_net_rx" title="Network" name="Receive" units="B" description="Receive network traffic, excluding effect from Streamline"/> 8 <event counter="Linux_net_rx" title="Network" name="Receive" units="B" description="Receive network traffic, including effect from Streamline"/>
9 <event counter="Linux_net_tx" title="Network" name="Transmit" units="B" description="Transmit network traffic, excluding effect from Streamline"/> 9 <event counter="Linux_net_tx" title="Network" name="Transmit" units="B" description="Transmit network traffic, including effect from Streamline"/>
10 <event counter="Linux_sched_switch" title="Scheduler" name="Switch" description="Context switch events"/> 10 <event counter="Linux_sched_switch" title="Scheduler" name="Switch" description="Context switch events"/>
11 <event counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/> 11 <event counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/>
12 <event counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/> 12 <event counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/>
13 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" display="maximum" units="B" average_selection="yes" description="Memory used by buffers"/> 13 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" display="maximum" units="B" average_selection="yes" description="Memory used by buffers"/>
14 <event counter="Linux_power_cpu_freq" title="Clock" name="DVFS" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Target frequency of the CPU"/> 14 <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Frequency setting of the CPU"/>
15 <event counter="Linux_power_cpu_idle" title="Power" name="Idle" per_cpu="yes" display="maximum" average_selection="yes" description="CPU Idle State, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/> 15 <event counter="Linux_power_cpu_idle" title="Power" name="Idle" per_cpu="yes" display="maximum" average_selection="yes" description="CPU Idle State, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
16 </category> 16 </category>
17 17
diff --git a/daemon/events-Mali-400.xml b/daemon/events-Mali-400.xml
index 895d0c8..cb1c6b4 100644
--- a/daemon/events-Mali-400.xml
+++ b/daemon/events-Mali-400.xml
@@ -1,397 +1,403 @@
1 <counter_set name="ARM_Mali-400_VP_cntX"> 1 <counter_set name="ARM_Mali-400_VP_cntX">
2 <counter name="ARM_Mali-400_VP_cnt0"/> 2 <counter name="ARM_Mali-400_VP_cnt0"/>
3 <counter name="ARM_Mali-400_VP_cnt1"/> 3 <counter name="ARM_Mali-400_VP_cnt1"/>
4 </counter_set> 4 </counter_set>
5 <counter_set name="ARM_Mali-400_FP0_cntX"> 5 <counter_set name="ARM_Mali-400_FP0_cntX">
6 <counter name="ARM_Mali-400_FP0_cnt0"/> 6 <counter name="ARM_Mali-400_FP0_cnt0"/>
7 <counter name="ARM_Mali-400_FP0_cnt1"/> 7 <counter name="ARM_Mali-400_FP0_cnt1"/>
8 </counter_set> 8 </counter_set>
9 <counter_set name="ARM_Mali-400_FP1_cntX"> 9 <counter_set name="ARM_Mali-400_FP1_cntX">
10 <counter name="ARM_Mali-400_FP1_cnt0"/> 10 <counter name="ARM_Mali-400_FP1_cnt0"/>
11 <counter name="ARM_Mali-400_FP1_cnt1"/> 11 <counter name="ARM_Mali-400_FP1_cnt1"/>
12 </counter_set> 12 </counter_set>
13 <counter_set name="ARM_Mali-400_FP2_cntX"> 13 <counter_set name="ARM_Mali-400_FP2_cntX">
14 <counter name="ARM_Mali-400_FP2_cnt0"/> 14 <counter name="ARM_Mali-400_FP2_cnt0"/>
15 <counter name="ARM_Mali-400_FP2_cnt1"/> 15 <counter name="ARM_Mali-400_FP2_cnt1"/>
16 </counter_set> 16 </counter_set>
17 <counter_set name="ARM_Mali-400_FP3_cntX"> 17 <counter_set name="ARM_Mali-400_FP3_cntX">
18 <counter name="ARM_Mali-400_FP3_cnt0"/> 18 <counter name="ARM_Mali-400_FP3_cnt0"/>
19 <counter name="ARM_Mali-400_FP3_cnt1"/> 19 <counter name="ARM_Mali-400_FP3_cnt1"/>
20 </counter_set> 20 </counter_set>
21 <counter_set name="ARM_Mali-400_L2_cntX"> 21 <counter_set name="ARM_Mali-400_L2_cntX">
22 <counter name="ARM_Mali-400_L2_cnt0"/> 22 <counter name="ARM_Mali-400_L2_cnt0"/>
23 <counter name="ARM_Mali-400_L2_cnt1"/> 23 <counter name="ARM_Mali-400_L2_cnt1"/>
24 </counter_set> 24 </counter_set>
25 <counter_set name="ARM_Mali-400_SW_cntX"> 25 <counter_set name="ARM_Mali-400_SW_cntX">
26 </counter_set> 26 </counter_set>
27 <counter_set name="ARM_Mali-400_Filmstrip_cntX"> 27 <counter_set name="ARM_Mali-400_Filmstrip_cntX">
28 <counter name="ARM_Mali-400_Filmstrip"/> 28 <counter name="ARM_Mali-400_Filmstrip"/>
29 </counter_set> 29 </counter_set>
30 <category name="Mali-400-VP" counter_set="ARM_Mali-400_VP_cntX" per_cpu="no"> 30 <category name="Mali-400-VP" counter_set="ARM_Mali-400_VP_cntX" per_cpu="no">
31 <event event="0x01" title="Mali GPU Vertex Processor" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active"/> 31 <event event="0x01" title="Mali GPU Vertex Processor" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active."/>
32 <event event="0x02" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active"/> 32 <event event="0x02" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active."/>
33 <event event="0x03" title="Mali GPU Vertex Processor" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active"/> 33 <event event="0x03" title="Mali GPU Vertex Processor" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active."/>
34 <event event="0x04" title="Mali GPU Vertex Processor" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active"/> 34 <event event="0x04" title="Mali GPU Vertex Processor" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active."/>
35 <event event="0x05" title="Mali GPU Vertex Processor" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader"/> 35 <event event="0x05" title="Mali GPU Vertex Processor" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader."/>
36 <event event="0x06" title="Mali GPU Vertex Processor" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame"/> 36 <event event="0x06" title="Mali GPU Vertex Processor" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame."/>
37 <event event="0x07" title="Mali GPU Vertex Processor" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame"/> 37 <event event="0x07" title="Mali GPU Vertex Processor" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame."/>
38 <event event="0x08" title="Mali GPU Vertex Processor" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame"/> 38 <event event="0x08" title="Mali GPU Vertex Processor" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame."/>
39 <event event="0x09" title="Mali GPU Vertex Processor" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame"/> 39 <event event="0x09" title="Mali GPU Vertex Processor" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame."/>
40 <event event="0x0a" title="Mali GPU Vertex Processor" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame"/> 40 <event event="0x0a" title="Mali GPU Vertex Processor" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame."/>
41 <event event="0x0b" title="Mali GPU Vertex Processor" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame"/> 41 <event event="0x0b" title="Mali GPU Vertex Processor" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame."/>
42 <event event="0x0c" title="Mali GPU Vertex Processor" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame"/> 42 <event event="0x0c" title="Mali GPU Vertex Processor" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame."/>
43 <event event="0x0e" title="Mali GPU Vertex Processor" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen"/> 43 <event event="0x0e" title="Mali GPU Vertex Processor" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen."/>
44 <event event="0x0f" title="Mali GPU Vertex Processor" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame"/> 44 <event event="0x0f" title="Mali GPU Vertex Processor" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame."/>
45 <event event="0x10" title="Mali GPU Vertex Processor" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame "/> 45 <event event="0x10" title="Mali GPU Vertex Processor" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame ."/>
46 <event event="0x13" title="Mali GPU Vertex Processor" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame"/> 46 <event event="0x13" title="Mali GPU Vertex Processor" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame."/>
47 <event event="0x16" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/> 47 <event event="0x16" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/>
48 <event event="0x17" title="Mali GPU Vertex Processor" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores"/> 48 <event event="0x17" title="Mali GPU Vertex Processor" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores."/>
49 <event event="0x18" title="Mali GPU Vertex Processor" name="Number of cycles per frame the MaliGP2 PLBU output unit was active (Writing the Mali200 input data structure). This includes time spent waiting on the bus" description="MALI_CINSTR_GP_ACTIVE_CYCLES_PLBU_LIST_WRITER"/> 49 <event event="0x18" title="Mali GPU Vertex Processor" name="MaliGP2 PLBU cycles per frame" description="Number of cycles per frame the MaliGP2 PLBU output unit was active. This includes time spent waiting on the bus."/>
50 <event event="0x19" title="Mali GPU Vertex Processor" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus"/> 50 <event event="0x19" title="Mali GPU Vertex Processor" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus."/>
51 <event event="0x1b" title="Mali GPU Vertex Processor" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus"/> 51 <event event="0x1b" title="Mali GPU Vertex Processor" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus."/>
52 <event event="0x1c" title="Mali GPU Vertex Processor" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus"/> 52 <event event="0x1c" title="Mali GPU Vertex Processor" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus."/>
53 <event event="0x1e" title="Mali GPU Vertex Processor" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus"/> 53 <event event="0x1e" title="Mali GPU Vertex Processor" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
54 <event event="0x20" title="Mali GPU Vertex Processor" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoringi. This includes time spent waiting on the bus"/> 54 <event event="0x20" title="Mali GPU Vertex Processor" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoringi. This includes time spent waiting on the bus."/>
55 <event event="0x21" title="Mali GPU Vertex Processor" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus"/> 55 <event event="0x21" title="Mali GPU Vertex Processor" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
56 </category> 56 </category>
57 <category name="Mali-400-FP0" counter_set="ARM_Mali-400_FP0_cntX" per_cpu="no"> 57 <category name="Mali-400-FP0" counter_set="ARM_Mali-400_FP0_cntX" per_cpu="no">
58 <event event="0x00" title="Mali GPU Fragment Processor 0" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/> 58 <event event="0x00" title="Mali GPU Fragment Processor 0" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
59 <event event="0x02" title="Mali GPU Fragment Processor 0" name="Total bus reads" description="Total number of 64-bit words read from the bus"/> 59 <event event="0x02" title="Mali GPU Fragment Processor 0" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
60 <event event="0x03" title="Mali GPU Fragment Processor 0" name="Total bus writes" description="Total number of 64-bit words written to the bus"/> 60 <event event="0x03" title="Mali GPU Fragment Processor 0" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
61 <event event="0x04" title="Mali GPU Fragment Processor 0" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/> 61 <event event="0x04" title="Mali GPU Fragment Processor 0" name="Bus read request cycles" description="Number of cycles during which the bus read request signal was HIGH."/>
62 <event event="0x05" title="Mali GPU Fragment Processor 0" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/> 62 <event event="0x05" title="Mali GPU Fragment Processor 0" name="Bus write request cycles" description="Number of cycles during which the bus write request signal was HIGH."/>
63 <event event="0x06" title="Mali GPU Fragment Processor 0" name="Bus read transactions count" description="Number of read requests accepted by the bus"/> 63 <event event="0x06" title="Mali GPU Fragment Processor 0" name="Bus read transactions count" description="Number of read requests accepted by the bus."/>
64 <event event="0x07" title="Mali GPU Fragment Processor 0" name="Bus write transactions" description="Number of write requests accepted by the bus"/> 64 <event event="0x07" title="Mali GPU Fragment Processor 0" name="Bus write transactions" description="Number of write requests accepted by the bus."/>
65 <event event="0x09" title="Mali GPU Fragment Processor 0" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/> 65 <event event="0x09" title="Mali GPU Fragment Processor 0" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit."/>
66 <event event="0x0a" title="Mali GPU Fragment Processor 0" name="Store unit writes" description="64-bit words written to the bus by the store unit"/> 66 <event event="0x0a" title="Mali GPU Fragment Processor 0" name="Store unit writes" description="64-bit words written to the bus by the store unit."/>
67 <event event="0x0d" title="Mali GPU Fragment Processor 0" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/> 67 <event event="0x0d" title="Mali GPU Fragment Processor 0" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache."/>
68 <event event="0x0e" title="Mali GPU Fragment Processor 0" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/> 68 <event event="0x0e" title="Mali GPU Fragment Processor 0" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader."/>
69 <event event="0x0f" title="Mali GPU Fragment Processor 0" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/> 69 <event event="0x0f" title="Mali GPU Fragment Processor 0" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register."/>
70 <event event="0x10" title="Mali GPU Fragment Processor 0" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/> 70 <event event="0x10" title="Mali GPU Fragment Processor 0" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache."/>
71 <event event="0x11" title="Mali GPU Fragment Processor 0" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/> 71 <event event="0x11" title="Mali GPU Fragment Processor 0" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table."/>
72 <event event="0x12" title="Mali GPU Fragment Processor 0" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/> 72 <event event="0x12" title="Mali GPU Fragment Processor 0" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache."/>
73 <event event="0x13" title="Mali GPU Fragment Processor 0" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/> 73 <event event="0x13" title="Mali GPU Fragment Processor 0" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus."/>
74 <event event="0x14" title="Mali GPU Fragment Processor 0" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/> 74 <event event="0x14" title="Mali GPU Fragment Processor 0" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus."/>
75 <event event="0x15" title="Mali GPU Fragment Processor 0" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/> 75 <event event="0x15" title="Mali GPU Fragment Processor 0" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table."/>
76 <event event="0x17" title="Mali GPU Fragment Processor 0" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/> 76 <event event="0x17" title="Mali GPU Fragment Processor 0" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction."/>
77 <event event="0x18" title="Mali GPU Fragment Processor 0" name="Polygon count" description="Number of triangles read from the polygon list"/> 77 <event event="0x18" title="Mali GPU Fragment Processor 0" name="Polygon count" description="Number of triangles read from the polygon list."/>
78 <event event="0x19" title="Mali GPU Fragment Processor 0" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/> 78 <event event="0x19" title="Mali GPU Fragment Processor 0" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list."/>
79 <event event="0x1a" title="Mali GPU Fragment Processor 0" name="Lines count" description="Number of lines read from the polygon list"/> 79 <event event="0x1a" title="Mali GPU Fragment Processor 0" name="Lines count" description="Number of lines read from the polygon list."/>
80 <event event="0x1b" title="Mali GPU Fragment Processor 0" name="Points count" description="Number of points read from the polygon list"/> 80 <event event="0x1b" title="Mali GPU Fragment Processor 0" name="Points count" description="Number of points read from the polygon list."/>
81 <event event="0x1c" title="Mali GPU Fragment Processor 0" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/> 81 <event event="0x1c" title="Mali GPU Fragment Processor 0" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected."/>
82 <event event="0x1d" title="Mali GPU Fragment Processor 0" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/> 82 <event event="0x1d" title="Mali GPU Fragment Processor 0" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input."/>
83 <event event="0x1e" title="Mali GPU Fragment Processor 0" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/> 83 <event event="0x1e" title="Mali GPU Fragment Processor 0" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer."/>
84 <event event="0x1f" title="Mali GPU Fragment Processor 0" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/> 84 <event event="0x1f" title="Mali GPU Fragment Processor 0" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad."/>
85 <event event="0x20" title="Mali GPU Fragment Processor 0" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/> 85 <event event="0x20" title="Mali GPU Fragment Processor 0" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed."/>
86 <event event="0x21" title="Mali GPU Fragment Processor 0" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/> 86 <event event="0x21" title="Mali GPU Fragment Processor 0" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill."/>
87 <event event="0x22" title="Mali GPU Fragment Processor 0" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/> 87 <event event="0x22" title="Mali GPU Fragment Processor 0" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test."/>
88 <event event="0x23" title="Mali GPU Fragment Processor 0" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/> 88 <event event="0x23" title="Mali GPU Fragment Processor 0" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels."/>
89 <event event="0x24" title="Mali GPU Fragment Processor 0" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/> 89 <event event="0x24" title="Mali GPU Fragment Processor 0" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection."/>
90 <event event="0x25" title="Mali GPU Fragment Processor 0" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/> 90 <event event="0x25" title="Mali GPU Fragment Processor 0" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs."/>
91 <event event="0x26" title="Mali GPU Fragment Processor 0" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/> 91 <event event="0x26" title="Mali GPU Fragment Processor 0" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous."/>
92 <event event="0x27" title="Mali GPU Fragment Processor 0" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/> 92 <event event="0x27" title="Mali GPU Fragment Processor 0" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation."/>
93 <event event="0x28" title="Mali GPU Fragment Processor 0" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/> 93 <event event="0x28" title="Mali GPU Fragment Processor 0" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation."/>
94 <event event="0x29" title="Mali GPU Fragment Processor 0" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/> 94 <event event="0x29" title="Mali GPU Fragment Processor 0" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation."/>
95 <event event="0x2a" title="Mali GPU Fragment Processor 0" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/> 95 <event event="0x2a" title="Mali GPU Fragment Processor 0" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer."/>
96 <event event="0x2b" title="Mali GPU Fragment Processor 0" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/> 96 <event event="0x2b" title="Mali GPU Fragment Processor 0" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation."/>
97 <event event="0x2c" title="Mali GPU Fragment Processor 0" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/> 97 <event event="0x2c" title="Mali GPU Fragment Processor 0" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported."/>
98 <event event="0x2d" title="Mali GPU Fragment Processor 0" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/> 98 <event event="0x2d" title="Mali GPU Fragment Processor 0" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active."/>
99 <event event="0x2e" title="Mali GPU Fragment Processor 0" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/> 99 <event event="0x2e" title="Mali GPU Fragment Processor 0" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed."/>
100 <event event="0x2f" title="Mali GPU Fragment Processor 0" name="Texture mapper cycle count" description="Number of texture operation cycles"/> 100 <event event="0x2f" title="Mali GPU Fragment Processor 0" name="Texture mapper cycle count" description="Number of texture operation cycles."/>
101 <event event="0x30" title="Mali GPU Fragment Processor 0" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/> 101 <event event="0x30" title="Mali GPU Fragment Processor 0" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)."/>
102 <event event="0x31" title="Mali GPU Fragment Processor 0" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/> 102 <event event="0x31" title="Mali GPU Fragment Processor 0" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)."/>
103 <event event="0x32" title="Mali GPU Fragment Processor 0" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/> 103 <event event="0x32" title="Mali GPU Fragment Processor 0" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)."/>
104 <event event="0x33" title="Mali GPU Fragment Processor 0" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/> 104 <event event="0x33" title="Mali GPU Fragment Processor 0" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)."/>
105 <event event="0x34" title="Mali GPU Fragment Processor 0" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 105 <event event="0x34" title="Mali GPU Fragment Processor 0" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
106 <event event="0x35" title="Mali GPU Fragment Processor 0" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/> 106 <event event="0x35" title="Mali GPU Fragment Processor 0" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)."/>
107 <event event="0x36" title="Mali GPU Fragment Processor 0" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/> 107 <event event="0x36" title="Mali GPU Fragment Processor 0" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)."/>
108 <event event="0x37" title="Mali GPU Fragment Processor 0" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 108 <event event="0x37" title="Mali GPU Fragment Processor 0" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
109 <event event="0x38" title="Mali GPU Fragment Processor 0" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/> 109 <event event="0x38" title="Mali GPU Fragment Processor 0" name="Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>
110 <event event="0x39" title="Mali GPU Fragment Processor 0" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/> 110 <event event="0x39" title="Mali GPU Fragment Processor 0" name="Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>
111 <event event="0x3a" title="Mali GPU Fragment Processor 0" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/> 111 <event event="0x3a" title="Mali GPU Fragment Processor 0" name="Load/Store cache hit count" description="Number of hits in the load/store cache."/>
112 <event event="0x3b" title="Mali GPU Fragment Processor 0" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/> 112 <event event="0x3b" title="Mali GPU Fragment Processor 0" name="Load/Store cache miss count" description="Number of misses in the load/store cache."/>
113 <event event="0x3c" title="Mali GPU Fragment Processor 0" name="Program cache hit count" description="Number of hits in the program cache"/> 113 <event event="0x3c" title="Mali GPU Fragment Processor 0" name="Program cache hit count" description="Number of hits in the program cache."/>
114 <event event="0x3d" title="Mali GPU Fragment Processor 0" name="Program cache miss count" description="Number of misses in the program cache"/> 114 <event event="0x3d" title="Mali GPU Fragment Processor 0" name="Program cache miss count" description="Number of misses in the program cache."/>
115 </category> 115 </category>
116 <category name="Mali-400-FP1" counter_set="ARM_Mali-400_FP1_cntX" per_cpu="no"> 116 <category name="Mali-400-FP1" counter_set="ARM_Mali-400_FP1_cntX" per_cpu="no">
117 <event event="0x00" title="Mali GPU Fragment Processor 1" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/> 117 <event event="0x00" title="Mali GPU Fragment Processor 1" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
118 <event event="0x02" title="Mali GPU Fragment Processor 1" name="Total bus reads" description="Total number of 64-bit words read from the bus"/> 118 <event event="0x02" title="Mali GPU Fragment Processor 1" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
119 <event event="0x03" title="Mali GPU Fragment Processor 1" name="Total bus writes" description="Total number of 64-bit words written to the bus"/> 119 <event event="0x03" title="Mali GPU Fragment Processor 1" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
120 <event event="0x04" title="Mali GPU Fragment Processor 1" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/> 120 <event event="0x04" title="Mali GPU Fragment Processor 1" name="Bus read request cycles" description="Number of cycles during which the bus read request signal was HIGH."/>
121 <event event="0x05" title="Mali GPU Fragment Processor 1" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/> 121 <event event="0x05" title="Mali GPU Fragment Processor 1" name="Bus write request cycles" description="Number of cycles during which the bus write request signal was HIGH."/>
122 <event event="0x06" title="Mali GPU Fragment Processor 1" name="Bus read transactions count" description="Number of read requests accepted by the bus"/> 122 <event event="0x06" title="Mali GPU Fragment Processor 1" name="Bus read transactions count" description="Number of read requests accepted by the bus."/>
123 <event event="0x07" title="Mali GPU Fragment Processor 1" name="Bus write transactions" description="Number of write requests accepted by the bus"/> 123 <event event="0x07" title="Mali GPU Fragment Processor 1" name="Bus write transactions" description="Number of write requests accepted by the bus."/>
124 <event event="0x09" title="Mali GPU Fragment Processor 1" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/> 124 <event event="0x09" title="Mali GPU Fragment Processor 1" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit."/>
125 <event event="0x0a" title="Mali GPU Fragment Processor 1" name="Store unit writes" description="64-bit words written to the bus by the store unit"/> 125 <event event="0x0a" title="Mali GPU Fragment Processor 1" name="Store unit writes" description="64-bit words written to the bus by the store unit."/>
126 <event event="0x0d" title="Mali GPU Fragment Processor 1" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/> 126 <event event="0x0d" title="Mali GPU Fragment Processor 1" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache."/>
127 <event event="0x0e" title="Mali GPU Fragment Processor 1" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/> 127 <event event="0x0e" title="Mali GPU Fragment Processor 1" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader."/>
128 <event event="0x0f" title="Mali GPU Fragment Processor 1" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/> 128 <event event="0x0f" title="Mali GPU Fragment Processor 1" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register."/>
129 <event event="0x10" title="Mali GPU Fragment Processor 1" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/> 129 <event event="0x10" title="Mali GPU Fragment Processor 1" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache."/>
130 <event event="0x11" title="Mali GPU Fragment Processor 1" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/> 130 <event event="0x11" title="Mali GPU Fragment Processor 1" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table."/>
131 <event event="0x12" title="Mali GPU Fragment Processor 1" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/> 131 <event event="0x12" title="Mali GPU Fragment Processor 1" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache."/>
132 <event event="0x13" title="Mali GPU Fragment Processor 1" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/> 132 <event event="0x13" title="Mali GPU Fragment Processor 1" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus."/>
133 <event event="0x14" title="Mali GPU Fragment Processor 1" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/> 133 <event event="0x14" title="Mali GPU Fragment Processor 1" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus."/>
134 <event event="0x15" title="Mali GPU Fragment Processor 1" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/> 134 <event event="0x15" title="Mali GPU Fragment Processor 1" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table."/>
135 <event event="0x17" title="Mali GPU Fragment Processor 1" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/> 135 <event event="0x17" title="Mali GPU Fragment Processor 1" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction."/>
136 <event event="0x18" title="Mali GPU Fragment Processor 1" name="Polygon count" description="Number of triangles read from the polygon list"/> 136 <event event="0x18" title="Mali GPU Fragment Processor 1" name="Polygon count" description="Number of triangles read from the polygon list."/>
137 <event event="0x19" title="Mali GPU Fragment Processor 1" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/> 137 <event event="0x19" title="Mali GPU Fragment Processor 1" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list."/>
138 <event event="0x1a" title="Mali GPU Fragment Processor 1" name="Lines count" description="Number of lines read from the polygon list"/> 138 <event event="0x1a" title="Mali GPU Fragment Processor 1" name="Lines count" description="Number of lines read from the polygon list."/>
139 <event event="0x1b" title="Mali GPU Fragment Processor 1" name="Points count" description="Number of points read from the polygon list"/> 139 <event event="0x1b" title="Mali GPU Fragment Processor 1" name="Points count" description="Number of points read from the polygon list."/>
140 <event event="0x1c" title="Mali GPU Fragment Processor 1" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/> 140 <event event="0x1c" title="Mali GPU Fragment Processor 1" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected."/>
141 <event event="0x1d" title="Mali GPU Fragment Processor 1" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/> 141 <event event="0x1d" title="Mali GPU Fragment Processor 1" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input."/>
142 <event event="0x1e" title="Mali GPU Fragment Processor 1" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/> 142 <event event="0x1e" title="Mali GPU Fragment Processor 1" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer."/>
143 <event event="0x1f" title="Mali GPU Fragment Processor 1" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/> 143 <event event="0x1f" title="Mali GPU Fragment Processor 1" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad."/>
144 <event event="0x20" title="Mali GPU Fragment Processor 1" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/> 144 <event event="0x20" title="Mali GPU Fragment Processor 1" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed."/>
145 <event event="0x21" title="Mali GPU Fragment Processor 1" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/> 145 <event event="0x21" title="Mali GPU Fragment Processor 1" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill."/>
146 <event event="0x22" title="Mali GPU Fragment Processor 1" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/> 146 <event event="0x22" title="Mali GPU Fragment Processor 1" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test."/>
147 <event event="0x23" title="Mali GPU Fragment Processor 1" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/> 147 <event event="0x23" title="Mali GPU Fragment Processor 1" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels."/>
148 <event event="0x24" title="Mali GPU Fragment Processor 1" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/> 148 <event event="0x24" title="Mali GPU Fragment Processor 1" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection."/>
149 <event event="0x25" title="Mali GPU Fragment Processor 1" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/> 149 <event event="0x25" title="Mali GPU Fragment Processor 1" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs."/>
150 <event event="0x26" title="Mali GPU Fragment Processor 1" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/> 150 <event event="0x26" title="Mali GPU Fragment Processor 1" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous."/>
151 <event event="0x27" title="Mali GPU Fragment Processor 1" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/> 151 <event event="0x27" title="Mali GPU Fragment Processor 1" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation."/>
152 <event event="0x28" title="Mali GPU Fragment Processor 1" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/> 152 <event event="0x28" title="Mali GPU Fragment Processor 1" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation."/>
153 <event event="0x29" title="Mali GPU Fragment Processor 1" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/> 153 <event event="0x29" title="Mali GPU Fragment Processor 1" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation."/>
154 <event event="0x2a" title="Mali GPU Fragment Processor 1" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/> 154 <event event="0x2a" title="Mali GPU Fragment Processor 1" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer."/>
155 <event event="0x2b" title="Mali GPU Fragment Processor 1" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/> 155 <event event="0x2b" title="Mali GPU Fragment Processor 1" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation."/>
156 <event event="0x2c" title="Mali GPU Fragment Processor 1" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/> 156 <event event="0x2c" title="Mali GPU Fragment Processor 1" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported."/>
157 <event event="0x2d" title="Mali GPU Fragment Processor 1" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/> 157 <event event="0x2d" title="Mali GPU Fragment Processor 1" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active."/>
158 <event event="0x2e" title="Mali GPU Fragment Processor 1" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/> 158 <event event="0x2e" title="Mali GPU Fragment Processor 1" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed."/>
159 <event event="0x2f" title="Mali GPU Fragment Processor 1" name="Texture mapper cycle count" description="Number of texture operation cycles"/> 159 <event event="0x2f" title="Mali GPU Fragment Processor 1" name="Texture mapper cycle count" description="Number of texture operation cycles."/>
160 <event event="0x30" title="Mali GPU Fragment Processor 1" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/> 160 <event event="0x30" title="Mali GPU Fragment Processor 1" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)."/>
161 <event event="0x31" title="Mali GPU Fragment Processor 1" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/> 161 <event event="0x31" title="Mali GPU Fragment Processor 1" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)."/>
162 <event event="0x32" title="Mali GPU Fragment Processor 1" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/> 162 <event event="0x32" title="Mali GPU Fragment Processor 1" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)."/>
163 <event event="0x33" title="Mali GPU Fragment Processor 1" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/> 163 <event event="0x33" title="Mali GPU Fragment Processor 1" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)."/>
164 <event event="0x34" title="Mali GPU Fragment Processor 1" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 164 <event event="0x34" title="Mali GPU Fragment Processor 1" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
165 <event event="0x35" title="Mali GPU Fragment Processor 1" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/> 165 <event event="0x35" title="Mali GPU Fragment Processor 1" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)."/>
166 <event event="0x36" title="Mali GPU Fragment Processor 1" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/> 166 <event event="0x36" title="Mali GPU Fragment Processor 1" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)."/>
167 <event event="0x37" title="Mali GPU Fragment Processor 1" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 167 <event event="0x37" title="Mali GPU Fragment Processor 1" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
168 <event event="0x38" title="Mali GPU Fragment Processor 1" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/> 168 <event event="0x38" title="Mali GPU Fragment Processor 1" name="Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>
169 <event event="0x39" title="Mali GPU Fragment Processor 1" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/> 169 <event event="0x39" title="Mali GPU Fragment Processor 1" name="Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>
170 <event event="0x3a" title="Mali GPU Fragment Processor 1" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/> 170 <event event="0x3a" title="Mali GPU Fragment Processor 1" name="Load/Store cache hit count" description="Number of hits in the load/store cache."/>
171 <event event="0x3b" title="Mali GPU Fragment Processor 1" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/> 171 <event event="0x3b" title="Mali GPU Fragment Processor 1" name="Load/Store cache miss count" description="Number of misses in the load/store cache."/>
172 <event event="0x3c" title="Mali GPU Fragment Processor 1" name="Program cache hit count" description="Number of hits in the program cache"/> 172 <event event="0x3c" title="Mali GPU Fragment Processor 1" name="Program cache hit count" description="Number of hits in the program cache."/>
173 <event event="0x3d" title="Mali GPU Fragment Processor 1" name="Program cache miss count" description="Number of misses in the program cache"/> 173 <event event="0x3d" title="Mali GPU Fragment Processor 1" name="Program cache miss count" description="Number of misses in the program cache."/>
174 </category> 174 </category>
175 <category name="Mali-400-FP2" counter_set="ARM_Mali-400_FP2_cntX" per_cpu="no"> 175 <category name="Mali-400-FP2" counter_set="ARM_Mali-400_FP2_cntX" per_cpu="no">
176 <event event="0x00" title="Mali GPU Fragment Processor 2" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/> 176 <event event="0x00" title="Mali GPU Fragment Processor 2" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
177 <event event="0x02" title="Mali GPU Fragment Processor 2" name="Total bus reads" description="Total number of 64-bit words read from the bus"/> 177 <event event="0x02" title="Mali GPU Fragment Processor 2" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
178 <event event="0x03" title="Mali GPU Fragment Processor 2" name="Total bus writes" description="Total number of 64-bit words written to the bus"/> 178 <event event="0x03" title="Mali GPU Fragment Processor 2" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
179 <event event="0x04" title="Mali GPU Fragment Processor 2" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/> 179 <event event="0x04" title="Mali GPU Fragment Processor 2" name="Bus read request cycles" description="Number of cycles during which the bus read request signal was HIGH."/>
180 <event event="0x05" title="Mali GPU Fragment Processor 2" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/> 180 <event event="0x05" title="Mali GPU Fragment Processor 2" name="Bus write request cycles" description="Number of cycles during which the bus write request signal was HIGH."/>
181 <event event="0x06" title="Mali GPU Fragment Processor 2" name="Bus read transactions count" description="Number of read requests accepted by the bus"/> 181 <event event="0x06" title="Mali GPU Fragment Processor 2" name="Bus read transactions count" description="Number of read requests accepted by the bus."/>
182 <event event="0x07" title="Mali GPU Fragment Processor 2" name="Bus write transactions" description="Number of write requests accepted by the bus"/> 182 <event event="0x07" title="Mali GPU Fragment Processor 2" name="Bus write transactions" description="Number of write requests accepted by the bus."/>
183 <event event="0x09" title="Mali GPU Fragment Processor 2" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/> 183 <event event="0x09" title="Mali GPU Fragment Processor 2" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit."/>
184 <event event="0x0a" title="Mali GPU Fragment Processor 2" name="Store unit writes" description="64-bit words written to the bus by the store unit"/> 184 <event event="0x0a" title="Mali GPU Fragment Processor 2" name="Store unit writes" description="64-bit words written to the bus by the store unit."/>
185 <event event="0x0d" title="Mali GPU Fragment Processor 2" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/> 185 <event event="0x0d" title="Mali GPU Fragment Processor 2" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache."/>
186 <event event="0x0e" title="Mali GPU Fragment Processor 2" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/> 186 <event event="0x0e" title="Mali GPU Fragment Processor 2" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader."/>
187 <event event="0x0f" title="Mali GPU Fragment Processor 2" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/> 187 <event event="0x0f" title="Mali GPU Fragment Processor 2" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register."/>
188 <event event="0x10" title="Mali GPU Fragment Processor 2" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/> 188 <event event="0x10" title="Mali GPU Fragment Processor 2" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache."/>
189 <event event="0x11" title="Mali GPU Fragment Processor 2" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/> 189 <event event="0x11" title="Mali GPU Fragment Processor 2" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table."/>
190 <event event="0x12" title="Mali GPU Fragment Processor 2" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/> 190 <event event="0x12" title="Mali GPU Fragment Processor 2" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache."/>
191 <event event="0x13" title="Mali GPU Fragment Processor 2" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/> 191 <event event="0x13" title="Mali GPU Fragment Processor 2" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus."/>
192 <event event="0x14" title="Mali GPU Fragment Processor 2" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/> 192 <event event="0x14" title="Mali GPU Fragment Processor 2" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus."/>
193 <event event="0x15" title="Mali GPU Fragment Processor 2" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/> 193 <event event="0x15" title="Mali GPU Fragment Processor 2" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table."/>
194 <event event="0x17" title="Mali GPU Fragment Processor 2" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/> 194 <event event="0x17" title="Mali GPU Fragment Processor 2" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction."/>
195 <event event="0x18" title="Mali GPU Fragment Processor 2" name="Polygon count" description="Number of triangles read from the polygon list"/> 195 <event event="0x18" title="Mali GPU Fragment Processor 2" name="Polygon count" description="Number of triangles read from the polygon list."/>
196 <event event="0x19" title="Mali GPU Fragment Processor 2" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/> 196 <event event="0x19" title="Mali GPU Fragment Processor 2" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list."/>
197 <event event="0x1a" title="Mali GPU Fragment Processor 2" name="Lines count" description="Number of lines read from the polygon list"/> 197 <event event="0x1a" title="Mali GPU Fragment Processor 2" name="Lines count" description="Number of lines read from the polygon list."/>
198 <event event="0x1b" title="Mali GPU Fragment Processor 2" name="Points count" description="Number of points read from the polygon list"/> 198 <event event="0x1b" title="Mali GPU Fragment Processor 2" name="Points count" description="Number of points read from the polygon list."/>
199 <event event="0x1c" title="Mali GPU Fragment Processor 2" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/> 199 <event event="0x1c" title="Mali GPU Fragment Processor 2" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected."/>
200 <event event="0x1d" title="Mali GPU Fragment Processor 2" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/> 200 <event event="0x1d" title="Mali GPU Fragment Processor 2" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input."/>
201 <event event="0x1e" title="Mali GPU Fragment Processor 2" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/> 201 <event event="0x1e" title="Mali GPU Fragment Processor 2" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer."/>
202 <event event="0x1f" title="Mali GPU Fragment Processor 2" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/> 202 <event event="0x1f" title="Mali GPU Fragment Processor 2" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad."/>
203 <event event="0x20" title="Mali GPU Fragment Processor 2" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/> 203 <event event="0x20" title="Mali GPU Fragment Processor 2" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed."/>
204 <event event="0x21" title="Mali GPU Fragment Processor 2" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/> 204 <event event="0x21" title="Mali GPU Fragment Processor 2" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill."/>
205 <event event="0x22" title="Mali GPU Fragment Processor 2" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/> 205 <event event="0x22" title="Mali GPU Fragment Processor 2" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test."/>
206 <event event="0x23" title="Mali GPU Fragment Processor 2" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/> 206 <event event="0x23" title="Mali GPU Fragment Processor 2" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels."/>
207 <event event="0x24" title="Mali GPU Fragment Processor 2" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/> 207 <event event="0x24" title="Mali GPU Fragment Processor 2" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection."/>
208 <event event="0x25" title="Mali GPU Fragment Processor 2" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/> 208 <event event="0x25" title="Mali GPU Fragment Processor 2" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs."/>
209 <event event="0x26" title="Mali GPU Fragment Processor 2" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/> 209 <event event="0x26" title="Mali GPU Fragment Processor 2" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous."/>
210 <event event="0x27" title="Mali GPU Fragment Processor 2" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/> 210 <event event="0x27" title="Mali GPU Fragment Processor 2" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation."/>
211 <event event="0x28" title="Mali GPU Fragment Processor 2" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/> 211 <event event="0x28" title="Mali GPU Fragment Processor 2" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation."/>
212 <event event="0x29" title="Mali GPU Fragment Processor 2" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/> 212 <event event="0x29" title="Mali GPU Fragment Processor 2" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation."/>
213 <event event="0x2a" title="Mali GPU Fragment Processor 2" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/> 213 <event event="0x2a" title="Mali GPU Fragment Processor 2" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer."/>
214 <event event="0x2b" title="Mali GPU Fragment Processor 2" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/> 214 <event event="0x2b" title="Mali GPU Fragment Processor 2" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation."/>
215 <event event="0x2c" title="Mali GPU Fragment Processor 2" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/> 215 <event event="0x2c" title="Mali GPU Fragment Processor 2" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported."/>
216 <event event="0x2d" title="Mali GPU Fragment Processor 2" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/> 216 <event event="0x2d" title="Mali GPU Fragment Processor 2" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active."/>
217 <event event="0x2e" title="Mali GPU Fragment Processor 2" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/> 217 <event event="0x2e" title="Mali GPU Fragment Processor 2" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed."/>
218 <event event="0x2f" title="Mali GPU Fragment Processor 2" name="Texture mapper cycle count" description="Number of texture operation cycles"/> 218 <event event="0x2f" title="Mali GPU Fragment Processor 2" name="Texture mapper cycle count" description="Number of texture operation cycles."/>
219 <event event="0x30" title="Mali GPU Fragment Processor 2" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/> 219 <event event="0x30" title="Mali GPU Fragment Processor 2" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)."/>
220 <event event="0x31" title="Mali GPU Fragment Processor 2" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/> 220 <event event="0x31" title="Mali GPU Fragment Processor 2" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)."/>
221 <event event="0x32" title="Mali GPU Fragment Processor 2" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/> 221 <event event="0x32" title="Mali GPU Fragment Processor 2" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)."/>
222 <event event="0x33" title="Mali GPU Fragment Processor 2" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/> 222 <event event="0x33" title="Mali GPU Fragment Processor 2" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)."/>
223 <event event="0x34" title="Mali GPU Fragment Processor 2" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 223 <event event="0x34" title="Mali GPU Fragment Processor 2" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
224 <event event="0x35" title="Mali GPU Fragment Processor 2" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/> 224 <event event="0x35" title="Mali GPU Fragment Processor 2" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)."/>
225 <event event="0x36" title="Mali GPU Fragment Processor 2" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/> 225 <event event="0x36" title="Mali GPU Fragment Processor 2" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)."/>
226 <event event="0x37" title="Mali GPU Fragment Processor 2" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 226 <event event="0x37" title="Mali GPU Fragment Processor 2" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
227 <event event="0x38" title="Mali GPU Fragment Processor 2" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/> 227 <event event="0x38" title="Mali GPU Fragment Processor 2" name="Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>
228 <event event="0x39" title="Mali GPU Fragment Processor 2" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/> 228 <event event="0x39" title="Mali GPU Fragment Processor 2" name="Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>
229 <event event="0x3a" title="Mali GPU Fragment Processor 2" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/> 229 <event event="0x3a" title="Mali GPU Fragment Processor 2" name="Load/Store cache hit count" description="Number of hits in the load/store cache."/>
230 <event event="0x3b" title="Mali GPU Fragment Processor 2" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/> 230 <event event="0x3b" title="Mali GPU Fragment Processor 2" name="Load/Store cache miss count" description="Number of misses in the load/store cache."/>
231 <event event="0x3c" title="Mali GPU Fragment Processor 2" name="Program cache hit count" description="Number of hits in the program cache"/> 231 <event event="0x3c" title="Mali GPU Fragment Processor 2" name="Program cache hit count" description="Number of hits in the program cache."/>
232 <event event="0x3d" title="Mali GPU Fragment Processor 2" name="Program cache miss count" description="Number of misses in the program cache"/> 232 <event event="0x3d" title="Mali GPU Fragment Processor 2" name="Program cache miss count" description="Number of misses in the program cache."/>
233 </category> 233 </category>
234 <category name="Mali-400-FP3" counter_set="ARM_Mali-400_FP3_cntX" per_cpu="no"> 234 <category name="Mali-400-FP3" counter_set="ARM_Mali-400_FP3_cntX" per_cpu="no">
235 <event event="0x00" title="Mali GPU Fragment Processor 3" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/> 235 <event event="0x00" title="Mali GPU Fragment Processor 3" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
236 <event event="0x02" title="Mali GPU Fragment Processor 3" name="Total bus reads" description="Total number of 64-bit words read from the bus"/> 236 <event event="0x02" title="Mali GPU Fragment Processor 3" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
237 <event event="0x03" title="Mali GPU Fragment Processor 3" name="Total bus writes" description="Total number of 64-bit words written to the bus"/> 237 <event event="0x03" title="Mali GPU Fragment Processor 3" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
238 <event event="0x04" title="Mali GPU Fragment Processor 3" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/> 238 <event event="0x04" title="Mali GPU Fragment Processor 3" name="Bus read request cycles" description="Number of cycles during which the bus read request signal was HIGH."/>
239 <event event="0x05" title="Mali GPU Fragment Processor 3" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/> 239 <event event="0x05" title="Mali GPU Fragment Processor 3" name="Bus write request cycles" description="Number of cycles during which the bus write request signal was HIGH."/>
240 <event event="0x06" title="Mali GPU Fragment Processor 3" name="Bus read transactions count" description="Number of read requests accepted by the bus"/> 240 <event event="0x06" title="Mali GPU Fragment Processor 3" name="Bus read transactions count" description="Number of read requests accepted by the bus."/>
241 <event event="0x07" title="Mali GPU Fragment Processor 3" name="Bus write transactions" description="Number of write requests accepted by the bus"/> 241 <event event="0x07" title="Mali GPU Fragment Processor 3" name="Bus write transactions" description="Number of write requests accepted by the bus."/>
242 <event event="0x09" title="Mali GPU Fragment Processor 3" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/> 242 <event event="0x09" title="Mali GPU Fragment Processor 3" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit."/>
243 <event event="0x0a" title="Mali GPU Fragment Processor 3" name="Store unit writes" description="64-bit words written to the bus by the store unit"/> 243 <event event="0x0a" title="Mali GPU Fragment Processor 3" name="Store unit writes" description="64-bit words written to the bus by the store unit."/>
244 <event event="0x0d" title="Mali GPU Fragment Processor 3" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/> 244 <event event="0x0d" title="Mali GPU Fragment Processor 3" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache."/>
245 <event event="0x0e" title="Mali GPU Fragment Processor 3" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/> 245 <event event="0x0e" title="Mali GPU Fragment Processor 3" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader."/>
246 <event event="0x0f" title="Mali GPU Fragment Processor 3" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/> 246 <event event="0x0f" title="Mali GPU Fragment Processor 3" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register."/>
247 <event event="0x10" title="Mali GPU Fragment Processor 3" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/> 247 <event event="0x10" title="Mali GPU Fragment Processor 3" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache."/>
248 <event event="0x11" title="Mali GPU Fragment Processor 3" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/> 248 <event event="0x11" title="Mali GPU Fragment Processor 3" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table."/>
249 <event event="0x12" title="Mali GPU Fragment Processor 3" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/> 249 <event event="0x12" title="Mali GPU Fragment Processor 3" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache."/>
250 <event event="0x13" title="Mali GPU Fragment Processor 3" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/> 250 <event event="0x13" title="Mali GPU Fragment Processor 3" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus."/>
251 <event event="0x14" title="Mali GPU Fragment Processor 3" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/> 251 <event event="0x14" title="Mali GPU Fragment Processor 3" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus."/>
252 <event event="0x15" title="Mali GPU Fragment Processor 3" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/> 252 <event event="0x15" title="Mali GPU Fragment Processor 3" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table."/>
253 <event event="0x17" title="Mali GPU Fragment Processor 3" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/> 253 <event event="0x17" title="Mali GPU Fragment Processor 3" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction."/>
254 <event event="0x18" title="Mali GPU Fragment Processor 3" name="Polygon count" description="Number of triangles read from the polygon list"/> 254 <event event="0x18" title="Mali GPU Fragment Processor 3" name="Polygon count" description="Number of triangles read from the polygon list."/>
255 <event event="0x19" title="Mali GPU Fragment Processor 3" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/> 255 <event event="0x19" title="Mali GPU Fragment Processor 3" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list."/>
256 <event event="0x1a" title="Mali GPU Fragment Processor 3" name="Lines count" description="Number of lines read from the polygon list"/> 256 <event event="0x1a" title="Mali GPU Fragment Processor 3" name="Lines count" description="Number of lines read from the polygon list."/>
257 <event event="0x1b" title="Mali GPU Fragment Processor 3" name="Points count" description="Number of points read from the polygon list"/> 257 <event event="0x1b" title="Mali GPU Fragment Processor 3" name="Points count" description="Number of points read from the polygon list."/>
258 <event event="0x1c" title="Mali GPU Fragment Processor 3" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/> 258 <event event="0x1c" title="Mali GPU Fragment Processor 3" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected."/>
259 <event event="0x1d" title="Mali GPU Fragment Processor 3" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/> 259 <event event="0x1d" title="Mali GPU Fragment Processor 3" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input."/>
260 <event event="0x1e" title="Mali GPU Fragment Processor 3" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/> 260 <event event="0x1e" title="Mali GPU Fragment Processor 3" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer."/>
261 <event event="0x1f" title="Mali GPU Fragment Processor 3" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/> 261 <event event="0x1f" title="Mali GPU Fragment Processor 3" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad."/>
262 <event event="0x20" title="Mali GPU Fragment Processor 3" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/> 262 <event event="0x20" title="Mali GPU Fragment Processor 3" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed."/>
263 <event event="0x21" title="Mali GPU Fragment Processor 3" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/> 263 <event event="0x21" title="Mali GPU Fragment Processor 3" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill."/>
264 <event event="0x22" title="Mali GPU Fragment Processor 3" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/> 264 <event event="0x22" title="Mali GPU Fragment Processor 3" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test."/>
265 <event event="0x23" title="Mali GPU Fragment Processor 3" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/> 265 <event event="0x23" title="Mali GPU Fragment Processor 3" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels."/>
266 <event event="0x24" title="Mali GPU Fragment Processor 3" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/> 266 <event event="0x24" title="Mali GPU Fragment Processor 3" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection."/>
267 <event event="0x25" title="Mali GPU Fragment Processor 3" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/> 267 <event event="0x25" title="Mali GPU Fragment Processor 3" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs."/>
268 <event event="0x26" title="Mali GPU Fragment Processor 3" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/> 268 <event event="0x26" title="Mali GPU Fragment Processor 3" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous."/>
269 <event event="0x27" title="Mali GPU Fragment Processor 3" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/> 269 <event event="0x27" title="Mali GPU Fragment Processor 3" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation."/>
270 <event event="0x28" title="Mali GPU Fragment Processor 3" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/> 270 <event event="0x28" title="Mali GPU Fragment Processor 3" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation."/>
271 <event event="0x29" title="Mali GPU Fragment Processor 3" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/> 271 <event event="0x29" title="Mali GPU Fragment Processor 3" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation."/>
272 <event event="0x2a" title="Mali GPU Fragment Processor 3" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/> 272 <event event="0x2a" title="Mali GPU Fragment Processor 3" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer."/>
273 <event event="0x2b" title="Mali GPU Fragment Processor 3" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/> 273 <event event="0x2b" title="Mali GPU Fragment Processor 3" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation."/>
274 <event event="0x2c" title="Mali GPU Fragment Processor 3" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/> 274 <event event="0x2c" title="Mali GPU Fragment Processor 3" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported."/>
275 <event event="0x2d" title="Mali GPU Fragment Processor 3" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/> 275 <event event="0x2d" title="Mali GPU Fragment Processor 3" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active."/>
276 <event event="0x2e" title="Mali GPU Fragment Processor 3" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/> 276 <event event="0x2e" title="Mali GPU Fragment Processor 3" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed."/>
277 <event event="0x2f" title="Mali GPU Fragment Processor 3" name="Texture mapper cycle count" description="Number of texture operation cycles"/> 277 <event event="0x2f" title="Mali GPU Fragment Processor 3" name="Texture mapper cycle count" description="Number of texture operation cycles."/>
278 <event event="0x30" title="Mali GPU Fragment Processor 3" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/> 278 <event event="0x30" title="Mali GPU Fragment Processor 3" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)."/>
279 <event event="0x31" title="Mali GPU Fragment Processor 3" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/> 279 <event event="0x31" title="Mali GPU Fragment Processor 3" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)."/>
280 <event event="0x32" title="Mali GPU Fragment Processor 3" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/> 280 <event event="0x32" title="Mali GPU Fragment Processor 3" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)."/>
281 <event event="0x33" title="Mali GPU Fragment Processor 3" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/> 281 <event event="0x33" title="Mali GPU Fragment Processor 3" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)."/>
282 <event event="0x34" title="Mali GPU Fragment Processor 3" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 282 <event event="0x34" title="Mali GPU Fragment Processor 3" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
283 <event event="0x35" title="Mali GPU Fragment Processor 3" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/> 283 <event event="0x35" title="Mali GPU Fragment Processor 3" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)."/>
284 <event event="0x36" title="Mali GPU Fragment Processor 3" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/> 284 <event event="0x36" title="Mali GPU Fragment Processor 3" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)."/>
285 <event event="0x37" title="Mali GPU Fragment Processor 3" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/> 285 <event event="0x37" title="Mali GPU Fragment Processor 3" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
286 <event event="0x38" title="Mali GPU Fragment Processor 3" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/> 286 <event event="0x38" title="Mali GPU Fragment Processor 3" name="Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>
287 <event event="0x39" title="Mali GPU Fragment Processor 3" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/> 287 <event event="0x39" title="Mali GPU Fragment Processor 3" name="Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>
288 <event event="0x3a" title="Mali GPU Fragment Processor 3" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/> 288 <event event="0x3a" title="Mali GPU Fragment Processor 3" name="Load/Store cache hit count" description="Number of hits in the load/store cache."/>
289 <event event="0x3b" title="Mali GPU Fragment Processor 3" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/> 289 <event event="0x3b" title="Mali GPU Fragment Processor 3" name="Load/Store cache miss count" description="Number of misses in the load/store cache."/>
290 <event event="0x3c" title="Mali GPU Fragment Processor 3" name="Program cache hit count" description="Number of hits in the program cache"/> 290 <event event="0x3c" title="Mali GPU Fragment Processor 3" name="Program cache hit count" description="Number of hits in the program cache."/>
291 <event event="0x3d" title="Mali GPU Fragment Processor 3" name="Program cache miss count" description="Number of misses in the program cache"/> 291 <event event="0x3d" title="Mali GPU Fragment Processor 3" name="Program cache miss count" description="Number of misses in the program cache."/>
292 </category> 292 </category>
293 <category name="Mali-400-L2" counter_set="ARM_Mali-400_L2_cntX" per_cpu="no"> 293 <category name="Mali-400-L2" counter_set="ARM_Mali-400_L2_cntX" per_cpu="no">
294 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/> 294 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles."/>
295 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles" /> 295 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles." />
296 <event event="0x08" title="Mali L2 Cache" name="Read transactions, master" description="Read transactions, master" /> 296 <event event="0x08" title="Mali L2 Cache" name="Read transactions, master" description="Read transactions, master." />
297 <event event="0x09" title="Mali L2 Cache" name="Write transactions, master" description="Write transactions, master" /> 297 <event event="0x09" title="Mali L2 Cache" name="Write transactions, master" description="Write transactions, master." />
298 <event event="0x0a" title="Mali L2 Cache" name="Words read, master" description="Words read, master" /> 298 <event event="0x0a" title="Mali L2 Cache" name="Words read, master" description="Words read, master." />
299 <event event="0x0b" title="Mali L2 Cache" name="Words written, master" description="Words written, master" /> 299 <event event="0x0b" title="Mali L2 Cache" name="Words written, master" description="Words written, master." />
300 <event event="0x10" title="Mali L2 Cache" name="Read transactions, all slaves" description="Read transactions, all slaves" /> 300 <event event="0x10" title="Mali L2 Cache" name="Read transactions, all slaves" description="Read transactions, all slaves." />
301 <event event="0x11" title="Mali L2 Cache" name="Write transactions, all slaves" description="Write transactions, all slaves" /> 301 <event event="0x11" title="Mali L2 Cache" name="Write transactions, all slaves" description="Write transactions, all slaves." />
302 <event event="0x12" title="Mali L2 Cache" name="Words read, all slaves" description="Words read, all slaves" /> 302 <event event="0x12" title="Mali L2 Cache" name="Words read, all slaves" description="Words read, all slaves." />
303 <event event="0x13" title="Mali L2 Cache" name="Words written, all slaves" description="Words written, all slaves" /> 303 <event event="0x13" title="Mali L2 Cache" name="Words written, all slaves" description="Words written, all slaves." />
304 <event event="0x14" title="Mali L2 Cache" name="Read hits, all slaves" description="Read hits, all slaves" /> 304 <event event="0x14" title="Mali L2 Cache" name="Read hits, all slaves" description="Read hits, all slaves." />
305 <event event="0x15" title="Mali L2 Cache" name="Read misses, all slaves" description="Read misses, all slaves" /> 305 <event event="0x15" title="Mali L2 Cache" name="Read misses, all slaves" description="Read misses, all slaves." />
306 <event event="0x16" title="Mali L2 Cache" name="Write invalidates, all slaves" description="Write invalidates, all slaves" /> 306 <event event="0x16" title="Mali L2 Cache" name="Write invalidates, all slaves" description="Write invalidates, all slaves." />
307 <event event="0x17" title="Mali L2 Cache" name="Read invalidates, all slaves" description="Read invalidates, all slaves" /> 307 <event event="0x17" title="Mali L2 Cache" name="Read invalidates, all slaves" description="Read invalidates, all slaves." />
308 <event event="0x18" title="Mali L2 Cache" name="Cacheable read transactions, all slaves" description="Cacheable read transactions, all slaves" /> 308 <event event="0x18" title="Mali L2 Cache" name="Cacheable read transactions, all slaves" description="Cacheable read transactions, all slaves." />
309 <event event="0x20" title="Mali L2 Cache" name="Read transactions, slave 0" description="Read transactions, slave 0" /> 309 <event event="0x20" title="Mali L2 Cache" name="Read transactions, slave 0" description="Read transactions, slave 0." />
310 <event event="0x21" title="Mali L2 Cache" name="Write transactions, slave 0" description="Write transactions, slave 0" /> 310 <event event="0x21" title="Mali L2 Cache" name="Write transactions, slave 0" description="Write transactions, slave 0." />
311 <event event="0x22" title="Mali L2 Cache" name="Words read, slave 0" description="Words read, slave 0" /> 311 <event event="0x22" title="Mali L2 Cache" name="Words read, slave 0" description="Words read, slave 0." />
312 <event event="0x23" title="Mali L2 Cache" name="Words written, slave 0" description="Words written, slave 0" /> 312 <event event="0x23" title="Mali L2 Cache" name="Words written, slave 0" description="Words written, slave 0." />
313 <event event="0x24" title="Mali L2 Cache" name="Read hits, slave 0" description="Read hits, slave 0" /> 313 <event event="0x24" title="Mali L2 Cache" name="Read hits, slave 0" description="Read hits, slave 0." />
314 <event event="0x25" title="Mali L2 Cache" name="Read misses, slave 0" description="Read misses, slave 0" /> 314 <event event="0x25" title="Mali L2 Cache" name="Read misses, slave 0" description="Read misses, slave 0." />
315 <event event="0x26" title="Mali L2 Cache" name="Write invalidates, slave 0" description="Write invalidates, slave 0" /> 315 <event event="0x26" title="Mali L2 Cache" name="Write invalidates, slave 0" description="Write invalidates, slave 0." />
316 <event event="0x27" title="Mali L2 Cache" name="Read invalidates, slave 0" description="Read invalidates, slave 0" /> 316 <event event="0x27" title="Mali L2 Cache" name="Read invalidates, slave 0" description="Read invalidates, slave 0." />
317 <event event="0x28" title="Mali L2 Cache" name="Cacheable read transactions, slave 0" description="Cacheable read transactions, slave 0" /> 317 <event event="0x28" title="Mali L2 Cache" name="Cacheable read transactions, slave 0" description="Cacheable read transactions, slave 0." />
318 <event event="0x30" title="Mali L2 Cache" name="Read transactions, slave 1" description="Read transactions, slave 1" /> 318 <event event="0x30" title="Mali L2 Cache" name="Read transactions, slave 1" description="Read transactions, slave 1." />
319 <event event="0x31" title="Mali L2 Cache" name="Write transactions, slave 1" description="Write transactions, slave 1" /> 319 <event event="0x31" title="Mali L2 Cache" name="Write transactions, slave 1" description="Write transactions, slave 1." />
320 <event event="0x32" title="Mali L2 Cache" name="Words read, slave 1" description="Words read, slave 1" /> 320 <event event="0x32" title="Mali L2 Cache" name="Words read, slave 1" description="Words read, slave 1." />
321 <event event="0x33" title="Mali L2 Cache" name="Words written, slave 1" description="Words written, slave 1" /> 321 <event event="0x33" title="Mali L2 Cache" name="Words written, slave 1" description="Words written, slave 1." />
322 <event event="0x34" title="Mali L2 Cache" name="Read hits, slave 1" description="Read hits, slave 1" /> 322 <event event="0x34" title="Mali L2 Cache" name="Read hits, slave 1" description="Read hits, slave 1." />
323 <event event="0x35" title="Mali L2 Cache" name="Read misses, slave 1" description="Read misses, slave 1" /> 323 <event event="0x35" title="Mali L2 Cache" name="Read misses, slave 1" description="Read misses, slave 1." />
324 <event event="0x36" title="Mali L2 Cache" name="Write invalidates, slave 1" description="Write invalidates, slave 1" /> 324 <event event="0x36" title="Mali L2 Cache" name="Write invalidates, slave 1" description="Write invalidates, slave 1." />
325 <event event="0x37" title="Mali L2 Cache" name="Read invalidates, slave 1" description="Read invalidates, slave 1" /> 325 <event event="0x37" title="Mali L2 Cache" name="Read invalidates, slave 1" description="Read invalidates, slave 1." />
326 <event event="0x38" title="Mali L2 Cache" name="Cacheable read transactions, slave 1" description="Cacheable read transactions, slave 1" /> 326 <event event="0x38" title="Mali L2 Cache" name="Cacheable read transactions, slave 1" description="Cacheable read transactions, slave 1." />
327 <event event="0x40" title="Mali L2 Cache" name="Read transactions, slave 2" description="Read transactions, slave 2" /> 327 <event event="0x40" title="Mali L2 Cache" name="Read transactions, slave 2" description="Read transactions, slave 2." />
328 <event event="0x41" title="Mali L2 Cache" name="Write transactions, slave 2" description="Write transactions, slave 2" /> 328 <event event="0x41" title="Mali L2 Cache" name="Write transactions, slave 2" description="Write transactions, slave 2." />
329 <event event="0x42" title="Mali L2 Cache" name="Words read, slave 2" description="Words read, slave 2" /> 329 <event event="0x42" title="Mali L2 Cache" name="Words read, slave 2" description="Words read, slave 2." />
330 <event event="0x43" title="Mali L2 Cache" name="Words written, slave 2" description="Words written, slave 2" /> 330 <event event="0x43" title="Mali L2 Cache" name="Words written, slave 2" description="Words written, slave 2." />
331 <event event="0x44" title="Mali L2 Cache" name="Read hits, slave 2" description="Read hits, slave 2" /> 331 <event event="0x44" title="Mali L2 Cache" name="Read hits, slave 2" description="Read hits, slave 2." />
332 <event event="0x45" title="Mali L2 Cache" name="Read misses, slave 2" description="Read misses, slave 2" /> 332 <event event="0x45" title="Mali L2 Cache" name="Read misses, slave 2" description="Read misses, slave 2." />
333 <event event="0x46" title="Mali L2 Cache" name="Write invalidates, slave 2" description="Write invalidates, slave 2" /> 333 <event event="0x46" title="Mali L2 Cache" name="Write invalidates, slave 2" description="Write invalidates, slave 2." />
334 <event event="0x47" title="Mali L2 Cache" name="Read invalidates, slave 2" description="Read invalidates, slave 2" /> 334 <event event="0x47" title="Mali L2 Cache" name="Read invalidates, slave 2" description="Read invalidates, slave 2." />
335 <event event="0x48" title="Mali L2 Cache" name="Cacheable read transactions, slave 2" description="Cacheable read transactions, slave 2" /> 335 <event event="0x48" title="Mali L2 Cache" name="Cacheable read transactions, slave 2" description="Cacheable read transactions, slave 2." />
336 <event event="0x50" title="Mali L2 Cache" name="Read transactions, slave 3" description="Read transactions, slave 3" /> 336 <event event="0x50" title="Mali L2 Cache" name="Read transactions, slave 3" description="Read transactions, slave 3." />
337 <event event="0x51" title="Mali L2 Cache" name="Write transactions, slave 3" description="Write transactions, slave 3" /> 337 <event event="0x51" title="Mali L2 Cache" name="Write transactions, slave 3" description="Write transactions, slave 3." />
338 <event event="0x52" title="Mali L2 Cache" name="Words read, slave 3" description="Words read, slave 3" /> 338 <event event="0x52" title="Mali L2 Cache" name="Words read, slave 3" description="Words read, slave 3." />
339 <event event="0x53" title="Mali L2 Cache" name="Words written, slave 3" description="Words written, slave 3" /> 339 <event event="0x53" title="Mali L2 Cache" name="Words written, slave 3" description="Words written, slave 3." />
340 <event event="0x54" title="Mali L2 Cache" name="Read hits, slave 3" description="Read hits, slave 3" /> 340 <event event="0x54" title="Mali L2 Cache" name="Read hits, slave 3" description="Read hits, slave 3." />
341 <event event="0x55" title="Mali L2 Cache" name="Read misses, slave 3" description="Read misses, slave 3" /> 341 <event event="0x55" title="Mali L2 Cache" name="Read misses, slave 3" description="Read misses, slave 3." />
342 <event event="0x56" title="Mali L2 Cache" name="Write invalidates, slave 3" description="Write invalidates, slave 3" /> 342 <event event="0x56" title="Mali L2 Cache" name="Write invalidates, slave 3" description="Write invalidates, slave 3." />
343 <event event="0x57" title="Mali L2 Cache" name="Read invalidates, slave 3" description="Read invalidates, slave 3" /> 343 <event event="0x57" title="Mali L2 Cache" name="Read invalidates, slave 3" description="Read invalidates, slave 3." />
344 <event event="0x58" title="Mali L2 Cache" name="Cacheable read transactions, slave 3" description="Cacheable read transactions, slave 3" /> 344 <event event="0x58" title="Mali L2 Cache" name="Cacheable read transactions, slave 3" description="Cacheable read transactions, slave 3." />
345 <event event="0x60" title="Mali L2 Cache" name="Read transactions, slave 4" description="Read transactions, slave 4" /> 345 <event event="0x60" title="Mali L2 Cache" name="Read transactions, slave 4" description="Read transactions, slave 4." />
346 <event event="0x61" title="Mali L2 Cache" name="Write transactions, slave 4" description="Write transactions, slave 4" /> 346 <event event="0x61" title="Mali L2 Cache" name="Write transactions, slave 4" description="Write transactions, slave 4." />
347 <event event="0x62" title="Mali L2 Cache" name="Words read, slave 4" description="Words read, slave 4" /> 347 <event event="0x62" title="Mali L2 Cache" name="Words read, slave 4" description="Words read, slave 4." />
348 <event event="0x63" title="Mali L2 Cache" name="Words written, slave 4" description="Words written, slave 4" /> 348 <event event="0x63" title="Mali L2 Cache" name="Words written, slave 4" description="Words written, slave 4." />
349 <event event="0x64" title="Mali L2 Cache" name="Read hits, slave 4" description="Read hits, slave 4" /> 349 <event event="0x64" title="Mali L2 Cache" name="Read hits, slave 4" description="Read hits, slave 4." />
350 <event event="0x65" title="Mali L2 Cache" name="Read misses, slave 4" description="Read misses, slave 4" /> 350 <event event="0x65" title="Mali L2 Cache" name="Read misses, slave 4" description="Read misses, slave 4." />
351 <event event="0x66" title="Mali L2 Cache" name="Write invalidates, slave 4" description="Write invalidates, slave 4" /> 351 <event event="0x66" title="Mali L2 Cache" name="Write invalidates, slave 4" description="Write invalidates, slave 4." />
352 <event event="0x67" title="Mali L2 Cache" name="Read invalidates, slave 4" description="Read invalidates, slave 4" /> 352 <event event="0x67" title="Mali L2 Cache" name="Read invalidates, slave 4" description="Read invalidates, slave 4." />
353 <event event="0x68" title="Mali L2 Cache" name="Cacheable read transactions, slave 4" description="Cacheable read transactions, slave 4" /> 353 <event event="0x68" title="Mali L2 Cache" name="Cacheable read transactions, slave 4" description="Cacheable read transactions, slave 4." />
354 </category> 354 </category>
355 <category name="ARM_Mali-400_Filmstrip" counter_set="ARM_Mali-400_Filmstrip_cntX" per_cpu="no"> 355 <category name="ARM_Mali-400_Filmstrip" counter_set="ARM_Mali-400_Filmstrip_cntX" per_cpu="no">
356 <event event="0x040a" title="ARM_Mali-400_Filmstrip" name="Freq 1:10" description="Scaled framebuffer captures every 10th frame" /> 356 <event event="0x040a" title="ARM_Mali-400_Filmstrip" name="Freq 1:10" description="Scaled framebuffer captures every 10th frame." />
357 <event event="0x041e" title="ARM_Mali-400_Filmstrip" name="Freq 1:30" description="Scaled framebuffer captures every 30th frame" /> 357 <event event="0x041e" title="ARM_Mali-400_Filmstrip" name="Freq 1:30" description="Scaled framebuffer captures every 30th frame." />
358 <event event="0x043c" title="ARM_Mali-400_Filmstrip" name="Freq 1:60" description="Scaled framebuffer captures every 60th frame" /> 358 <event event="0x043c" title="ARM_Mali-400_Filmstrip" name="Freq 1:60" description="Scaled framebuffer captures every 60th frame." />
359 </category> 359 </category>
360 <category name="Mali-400-SW" counter_set="ARM_Mali-400_SW_cntX" per_cpu="no"> 360 <category name="ARM_Mali-400_Voltage" per_cpu="no">
361 <!-- EGL Counters --> 361 <event counter="ARM_Mali-400_Voltage" title="Mali GPU Voltage" name="Voltage" display="average" average_selection="yes" units="mV" description="GPU core voltage."/>
362 <event counter="ARM_Mali-400_SW_17" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the the framebuffer from video memory to framebuffer"/> 362 </category>
363 <!-- glDrawElements Counters --> 363 <category name="ARM_Mali-400_Frequency" per_cpu="no">
364 <event counter="ARM_Mali-400_SW_18" title="glDrawElements Statistics" name="Calls to glDrawElements" description="Number of calls to glDrawElements"/> 364 <event counter="ARM_Mali-400_Frequency" title="Mali GPU Frequency" name="Frequency" display="average" average_selection="yes" units="MHz" description="GPU core frequency."/>
365 <event counter="ARM_Mali-400_SW_19" title="glDrawElements Statistics" name="Indices to glDrawElements" description="Number of indicies to glDrawElements"/> 365 </category>
366 <event counter="ARM_Mali-400_SW_20" title="glDrawElements Statistics" name="Transformed by glDrawElements" description="Number of vertices transformed by glDrawElements"/> 366 <category name="Mali-400-SW" counter_set="ARM_Mali-400_SW_cntX" per_cpu="no">
367 <!-- glDrawArrays Counters --> 367 <!-- EGL Counters -->
368 <event counter="ARM_Mali-400_SW_21" title="glDrawArrays Statistics" name="Calls to glDrawArrays" description="Number of calls to glDrawArrays"/> 368 <event counter="ARM_Mali-400_SW_17" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the the framebuffer from video memory to framebuffer."/>
369 <event counter="ARM_Mali-400_SW_22" title="glDrawArrays Statistics" name="Transformed by glDrawArrays" description="Number of vertices transformed by glDrawArrays"/> 369 <!-- glDrawElements Counters -->
370 <!-- Draw Call Counters --> 370 <event counter="ARM_Mali-400_SW_18" title="glDrawElements Statistics" name="Calls to glDrawElements" description="Number of calls to glDrawElements."/>
371 <event counter="ARM_Mali-400_SW_23" title="Drawcall Statistics" name="Points" description="Number of calls to glDraw* with parameter GL_POINTS"/> 371 <event counter="ARM_Mali-400_SW_19" title="glDrawElements Statistics" name="Indices to glDrawElements" description="Number of indicies to glDrawElements."/>
372 <event counter="ARM_Mali-400_SW_24" title="Drawcall Statistics" name="Lines" description="Number of calls to glDraw* with parameter GL_LINES"/> 372 <event counter="ARM_Mali-400_SW_20" title="glDrawElements Statistics" name="Transformed by glDrawElements" description="Number of vertices transformed by glDrawElements."/>
373 <event counter="ARM_Mali-400_SW_25" title="Drawcall Statistics" name="Lineloop" description="Number of calls to glDraw* with parameter GL_LINE_LOOP"/> 373 <!-- glDrawArrays Counters -->
374 <event counter="ARM_Mali-400_SW_26" title="Drawcall Statistics" name="Linestrip" description="Number of calls to glDraw* with parameter GL_LINE_STRIP"/> 374 <event counter="ARM_Mali-400_SW_21" title="glDrawArrays Statistics" name="Calls to glDrawArrays" description="Number of calls to glDrawArrays."/>
375 <event counter="ARM_Mali-400_SW_27" title="Drawcall Statistics" name="Triangles" description="Number of calls to glDraw* with parameter GL_TRIANGLES"/> 375 <event counter="ARM_Mali-400_SW_22" title="glDrawArrays Statistics" name="Transformed by glDrawArrays" description="Number of vertices transformed by glDrawArrays."/>
376 <event counter="ARM_Mali-400_SW_28" title="Drawcall Statistics" name="Trianglestrip" description="Number of calls to glDraw* with parameter GL_TRIANGLE_STRIP"/> 376 <!-- Draw Call Counters -->
377 <event counter="ARM_Mali-400_SW_29" title="Drawcall Statistics" name="Trianglefan" description="Number of calls to glDraw* with parameter GL_TRIANGLE_FAN"/> 377 <event counter="ARM_Mali-400_SW_23" title="Drawcall Statistics" name="Points" description="Number of calls to glDraw* with parameter GL_POINTS."/>
378 <event counter="ARM_Mali-400_SW_30" title="Drawcall Statistics" name="Vertex Upload Time (us)" description="Time spent uploading vertex attributes and faceindex data not present in a VBO"/> 378 <event counter="ARM_Mali-400_SW_24" title="Drawcall Statistics" name="Lines" description="Number of calls to glDraw* with parameter GL_LINES."/>
379 <event counter="ARM_Mali-400_SW_31" title="Drawcall Statistics" name="Uniform Bytes Copied (bytes)" description="Number of bytes copied to Mali memory as a result of uniforms update"/> 379 <event counter="ARM_Mali-400_SW_25" title="Drawcall Statistics" name="Lineloop" description="Number of calls to glDraw* with parameter GL_LINE_LOOP."/>
380 <!-- Buffer Profiling Counters --> 380 <event counter="ARM_Mali-400_SW_26" title="Drawcall Statistics" name="Linestrip" description="Number of calls to glDraw* with parameter GL_LINE_STRIP."/>
381 <event counter="ARM_Mali-400_SW_32" title="Buffer Profiling" name="Texture Upload Time (ms)" description="Time spent uploading textures"/> 381 <event counter="ARM_Mali-400_SW_27" title="Drawcall Statistics" name="Triangles" description="Number of calls to glDraw* with parameter GL_TRIANGLES."/>
382 <event counter="ARM_Mali-400_SW_33" title="Buffer Profiling" name="VBO Upload Time (ms)" description="Time spent uploading vertex buffer objects"/> 382 <event counter="ARM_Mali-400_SW_28" title="Drawcall Statistics" name="Trianglestrip" description="Number of calls to glDraw* with parameter GL_TRIANGLE_STRIP."/>
383 <event counter="ARM_Mali-400_SW_34" title="Buffer Profiling" name="FBO Flushes" description="Number of flushed on framebuffer attachement"/> 383 <event counter="ARM_Mali-400_SW_29" title="Drawcall Statistics" name="Trianglefan" description="Number of calls to glDraw* with parameter GL_TRIANGLE_FAN."/>
384 <!-- OpenGL ES 1.1 Emulation --> 384 <event counter="ARM_Mali-400_SW_30" title="Drawcall Statistics" name="Vertex Upload Time (us)" description="Time spent uploading vertex attributes and faceindex data not present in a VBO."/>
385 <event counter="ARM_Mali-400_SW_35" title="Fixed-function Emulation" name="# Vertex Shaders Generated" description="Number of vertex shaders generated"/> 385 <event counter="ARM_Mali-400_SW_31" title="Drawcall Statistics" name="Uniform Bytes Copied (bytes)" description="Number of bytes copied to Mali memory as a result of uniforms update."/>
386 <event counter="ARM_Mali-400_SW_36" title="Fixed-function Emulation" name="# Fragment Shaders Generated" description="Number of fragment shaders generated"/> 386 <!-- Buffer Profiling Counters -->
387 <!-- Geometry Statistics --> 387 <event counter="ARM_Mali-400_SW_32" title="Buffer Profiling" name="Texture Upload Time (ms)" description="Time spent uploading textures."/>
388 <event counter="ARM_Mali-400_SW_50" title="Geometry Statistics" name="Triangles" description="The total number of triangles passed to GLES per-frame"/> 388 <event counter="ARM_Mali-400_SW_33" title="Buffer Profiling" name="VBO Upload Time (ms)" description="Time spent uploading vertex buffer objects."/>
389 <event counter="ARM_Mali-400_SW_51" title="Geometry Statistics" name="Independent Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLES"/> 389 <event counter="ARM_Mali-400_SW_34" title="Buffer Profiling" name="FBO Flushes" description="Number of flushed on framebuffer attachement."/>
390 <event counter="ARM_Mali-400_SW_52" title="Geometry Statistics" name="Strip Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_STRIP"/> 390 <!-- OpenGL ES 1.1 Emulation -->
391 <event counter="ARM_Mali-400_SW_53" title="Geometry Statistics" name="Fan Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_FAN"/> 391 <event counter="ARM_Mali-400_SW_35" title="Fixed-function Emulation" name="# Vertex Shaders Generated" description="Number of vertex shaders generated."/>
392 <event counter="ARM_Mali-400_SW_54" title="Geometry Statistics" name="Lines" description="Number of lines passed to GLES per-frame"/> 392 <event counter="ARM_Mali-400_SW_36" title="Fixed-function Emulation" name="# Fragment Shaders Generated" description="Number of fragment shaders generated."/>
393 <event counter="ARM_Mali-400_SW_55" title="Geometry Statistics" name="Independent Lines" description="Number of lines passed to GLES using the mode GL_LINES"/> 393 <!-- Geometry Statistics -->
394 <event counter="ARM_Mali-400_SW_56" title="Geometry Statistics" name="Strip Lines" description="Number of lines passed to GLES using the mode GL_LINE_STRIP"/> 394 <event counter="ARM_Mali-400_SW_50" title="Geometry Statistics" name="Triangles" description="The total number of triangles passed to GLES per-frame."/>
395 <event counter="ARM_Mali-400_SW_57" title="Geometry Statistics" name="Loop Lines" description="Number of lines passed to GLES using the mode GL_LINE_LOOP"/> 395 <event counter="ARM_Mali-400_SW_51" title="Geometry Statistics" name="Independent Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLES."/>
396 </category> 396 <event counter="ARM_Mali-400_SW_52" title="Geometry Statistics" name="Strip Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_STRIP."/>
397 397 <event counter="ARM_Mali-400_SW_53" title="Geometry Statistics" name="Fan Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_FAN."/>
398 <event counter="ARM_Mali-400_SW_54" title="Geometry Statistics" name="Lines" description="Number of lines passed to GLES per-frame."/>
399 <event counter="ARM_Mali-400_SW_55" title="Geometry Statistics" name="Independent Lines" description="Number of lines passed to GLES using the mode GL_LINES."/>
400 <event counter="ARM_Mali-400_SW_56" title="Geometry Statistics" name="Strip Lines" description="Number of lines passed to GLES using the mode GL_LINE_STRIP."/>
401 <event counter="ARM_Mali-400_SW_57" title="Geometry Statistics" name="Loop Lines" description="Number of lines passed to GLES using the mode GL_LINE_LOOP."/>
402 </category>
403
diff --git a/daemon/events-Mali-T6xx.xml b/daemon/events-Mali-T6xx.xml
new file mode 100644
index 0000000..5237e30
--- /dev/null
+++ b/daemon/events-Mali-T6xx.xml
@@ -0,0 +1,38 @@
1
2 <category name="Mali-T6xx-SW-counters" per_cpu="no">
3 <event counter="ARM_Mali-T6xx_TOTAL_ALLOC_PAGES" title="Mali Total Alloc Pages" name="Total number of allocated pages" description="Mali total number of allocated pages."/>
4 </category>
5
6 <category name="Mali-T6xx-PMShader" per_cpu="no">
7 <event counter="ARM_Mali-T6xx_PM_SHADER_0" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
8 <event counter="ARM_Mali-T6xx_PM_SHADER_1" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
9 <event counter="ARM_Mali-T6xx_PM_SHADER_2" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
10 <event counter="ARM_Mali-T6xx_PM_SHADER_3" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/>
11 <event counter="ARM_Mali-T6xx_PM_SHADER_4" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/>
12 <event counter="ARM_Mali-T6xx_PM_SHADER_5" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/>
13 <event counter="ARM_Mali-T6xx_PM_SHADER_6" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
14 <event counter="ARM_Mali-T6xx_PM_SHADER_7" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
15 </category>
16
17 <category name="Mali-T6xx-PMTiler" per_cpu="no">
18 <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" units="%" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
19 </category>
20
21 <category name="Mali-T6xx-PML2" per_cpu="no">
22 <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" units="%" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
23 <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" units="%" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
24 </category>
25
26 <category name="Mali-T6xx-MMU_AS" per_cpu="no">
27 <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
28 <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
29 <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
30 <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
31 </category>
32
33 <category name="Mali-T6xx-MMU_page_fault" per_cpu="no">
34 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_0" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 0" description="Reports the number of newly allocated pages after a MMU page fault in address space 0."/>
35 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_1" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 1" description="Reports the number of newly allocated pages after a MMU page fault in address space 1."/>
36 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_2" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 2" description="Reports the number of newly allocated pages after a MMU page fault in address space 2."/>
37 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_3" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 3" description="Reports the number of newly allocated pages after a MMU page fault in address space 3."/>
38 </category>
diff --git a/daemon/events-Mali-T6xx_hw.xml b/daemon/events-Mali-T6xx_hw.xml
new file mode 100644
index 0000000..77f7aec
--- /dev/null
+++ b/daemon/events-Mali-T6xx_hw.xml
@@ -0,0 +1,278 @@
1
2 <category name="Mali-T6xx-JobManager" per_cpu="no">
3 <event counter="ARM_Mali-T6xx_MESSAGES_SENT" title="Mali GPU Job Manager" name="Job Manager messages sent" description="Number of JCB messages sent by the Job Manager."/>
4 <event counter="ARM_Mali-T6xx_MESSAGES_RECEIVED" title="Mali GPU Job Manager" name="Job Manager messages received " description="Number of JCB messages received by the Job Manager."/>
5 <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali GPU Job Manager" name="GPU active cycles" description="Number of cycles the GPU was active."/>
6 <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali GPU Job Manager" name="IRQ active cycles" description="Number of cycles with active interrupts."/>
7
8 <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali GPU Job Manager" name="Job Slot 0 jobs complete" description="Number of jobs completed in Job Slot 0."/>
9 <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali GPU Job Manager" name="Job Slot 0 tasks complete" description="Number of tasks completed in Job Slot 0."/>
10 <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 0 active" description="Number of cycles Job Slot 0 was active."/>
11 <event counter="ARM_Mali-T6xx_JS0_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 0 wait read" description="Number of cycles Job Slot 0 stalled waiting for descriptors to be read."/>
12 <event counter="ARM_Mali-T6xx_JS0_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 0 wait issue" description="Number of cycles Job Slot 0 stalled unable to issue tasks because all available cores were full."/>
13 <event counter="ARM_Mali-T6xx_JS0_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 0 wait depend" description="Number of cycles Job Slot 0 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
14 <event counter="ARM_Mali-T6xx_JS0_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 0 wait finish" description="Number of cycles Job Slot 0 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
15
16 <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali GPU Job Manager" name="Job Slot 1 jobs complete" description="Number of jobs completed in Job Slot 1."/>
17 <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali GPU Job Manager" name="Job Slot 1 tasks complete" description="Number of tasks completed in Job Slot 1."/>
18 <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 1 active" description="Number of cycles Job Slot 1 was active."/>
19 <event counter="ARM_Mali-T6xx_JS1_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 1 wait read" description="Number of cycles Job Slot 1 stalled waiting for descriptors to be read."/>
20 <event counter="ARM_Mali-T6xx_JS1_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 1 wait issue" description="Number of cycles Job Slot 1 stalled unable to issue tasks because all available cores were full."/>
21 <event counter="ARM_Mali-T6xx_JS1_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 1 wait depend" description="Number of cycles Job Slot 1 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
22 <event counter="ARM_Mali-T6xx_JS1_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 1 wait finish" description="Number of cycles Job Slot 1 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
23
24 <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali GPU Job Manager" name="Job Slot 2 jobs complete" description="Number of jobs completed in Job Slot 2."/>
25 <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali GPU Job Manager" name="Job Slot 2 tasks complete" description="Number of tasks completed in Job Slot 2."/>
26 <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 2 active" description="Number of cycles Job Slot 2 was active."/>
27 <event counter="ARM_Mali-T6xx_JS2_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 2 wait read" description="Number of cycles Job Slot 2 stalled waiting for descriptors to be read."/>
28 <event counter="ARM_Mali-T6xx_JS2_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 2 wait issue" description="Number of cycles Job Slot 2 stalled unable to issue tasks because all available cores were full."/>
29 <event counter="ARM_Mali-T6xx_JS2_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 2 wait depend" description="Number of cycles Job Slot 2 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
30 <event counter="ARM_Mali-T6xx_JS2_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 2 wait finish" description="Number of cycles Job Slot 2 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
31<!--
32 <event counter="ARM_Mali-T6xx_JS3_JOBS" title="Mali GPU Job Manager" name="Job Slot 3 jobs complete" description="Number of jobs completed in Job Slot 3."/>
33 <event counter="ARM_Mali-T6xx_JS3_TASKS" title="Mali GPU Job Manager" name="Job Slot 3 tasks complete" description="Number of tasks completed in Job Slot 3."/>
34 <event counter="ARM_Mali-T6xx_JS3_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 3 active" description="Number of cycles Job Slot 3 was active."/>
35 <event counter="ARM_Mali-T6xx_JS3_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 3 wait read" description="Number of cycles Job Slot 3 stalled waiting for descriptors to be read."/>
36 <event counter="ARM_Mali-T6xx_JS3_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 3 wait issue" description="Number of cycles Job Slot 3 stalled unable to issue tasks because all available cores were full."/>
37 <event counter="ARM_Mali-T6xx_JS3_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 3 wait depend" description="Number of cycles Job Slot 3 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
38 <event counter="ARM_Mali-T6xx_JS3_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 3 wait finish" description="Number of cycles Job Slot 3 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
39
40 <event counter="ARM_Mali-T6xx_JS4_JOBS" title="Mali GPU Job Manager" name="Job Slot 4 jobs complete" description="Number of jobs completed in Job Slot 4."/>
41 <event counter="ARM_Mali-T6xx_JS4_TASKS" title="Mali GPU Job Manager" name="Job Slot 4 tasks complete" description="Number of tasks completed in Job Slot 4."/>
42 <event counter="ARM_Mali-T6xx_JS4_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 4 active" description="Number of cycles Job Slot 4 was active."/>
43 <event counter="ARM_Mali-T6xx_JS4_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 4 wait read" description="Number of cycles Job Slot 4 stalled waiting for descriptors to be read."/>
44 <event counter="ARM_Mali-T6xx_JS4_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 4 wait issue" description="Number of cycles Job Slot 4 stalled unable to issue tasks because all available cores were full."/>
45 <event counter="ARM_Mali-T6xx_JS4_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 4 wait depend" description="Number of cycles Job Slot 4 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
46 <event counter="ARM_Mali-T6xx_JS4_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 4 wait finish" description="Number of cycles Job Slot 4 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
47
48 <event counter="ARM_Mali-T6xx_JS5_JOBS" title="Mali GPU Job Manager" name="Job Slot 5 jobs complete" description="Number of jobs completed in Job Slot 5."/>
49 <event counter="ARM_Mali-T6xx_JS5_TASKS" title="Mali GPU Job Manager" name="Job Slot 5 tasks complete" description="Number of tasks completed in Job Slot 5."/>
50 <event counter="ARM_Mali-T6xx_JS5_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 5 active" description="Number of cycles Job Slot 5 was active."/>
51 <event counter="ARM_Mali-T6xx_JS5_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 5 wait read" description="Number of cycles Job Slot 5 stalled waiting for descriptors to be read."/>
52 <event counter="ARM_Mali-T6xx_JS5_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 5 wait issue" description="Number of cycles Job Slot 5 stalled unable to issue tasks because all available cores were full."/>
53 <event counter="ARM_Mali-T6xx_JS5_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 5 wait depend" description="Number of cycles Job Slot 5 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
54 <event counter="ARM_Mali-T6xx_JS5_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 5 wait finish" description="Number of cycles Job Slot 5 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
55
56 <event counter="ARM_Mali-T6xx_JS6_JOBS" title="Mali GPU Job Manager" name="Job Slot 6 jobs complete" description="Number of jobs completed in Job Slot 6."/>
57 <event counter="ARM_Mali-T6xx_JS6_TASKS" title="Mali GPU Job Manager" name="Job Slot 6 tasks complete" description="Number of tasks completed in Job Slot 6."/>
58 <event counter="ARM_Mali-T6xx_JS6_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 6 active" description="Number of cycles Job Slot 6 was active."/>
59 <event counter="ARM_Mali-T6xx_JS6_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 6 wait read" description="Number of cycles Job Slot 6 stalled waiting for descriptors to be read."/>
60 <event counter="ARM_Mali-T6xx_JS6_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 6 wait issue" description="Number of cycles Job Slot 6 stalled unable to issue tasks because all available cores were full."/>
61 <event counter="ARM_Mali-T6xx_JS6_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 6 wait depend" description="Number of cycles Job Slot 6 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
62 <event counter="ARM_Mali-T6xx_JS6_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 6 wait finish" description="Number of cycles Job Slot 6 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
63-->
64 </category>
65
66 <category name="Mali-T6xx-Tiler" per_cpu="no">
67<!--
68 <event counter="ARM_Mali-T6xx_JOBS_PROCESSED" title="Mali GPU Tiler" name="Jobs processed" description="Number of jobs processed."/>
69-->
70 <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali GPU Tiler" name="Triangles processed" description="Number of triangles processed."/>
71 <event counter="ARM_Mali-T6xx_QUADS" title="Mali GPU Tiler" name="Quads processed" description="Number of quads processed."/>
72 <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali GPU Tiler" name="Polygons processed" description="Number of polygons processed."/>
73 <event counter="ARM_Mali-T6xx_POINTS" title="Mali GPU Tiler" name="Points processed" description="Number of points processed."/>
74
75 <event counter="ARM_Mali-T6xx_LINES" title="Mali GPU Tiler" name="Lines processed" description="Number of lines processed."/>
76 <event counter="ARM_Mali-T6xx_VCACHE_HIT" title="Mali GPU Tiler" name="Vertex cache hits" description="Number of vertex cache hits."/>
77 <event counter="ARM_Mali-T6xx_VCACHE_MISS" title="Mali GPU Tiler" name="Vertex cache misses" description="Number of vertex cache misses."/>
78 <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali GPU Tiler" name="Front facing primitives" description="Number of front facing primitives."/>
79
80 <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali GPU Tiler" name="Back facing primitives" description="Number of back facing primitives."/>
81 <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali GPU Tiler" name="Visible primitives" description="Number of visible primitives."/>
82 <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali GPU Tiler" name="Culled primitives" description="Number of culled primitives."/>
83 <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali GPU Tiler" name="Clipped primitives" description="Number of clipped primitives."/>
84
85 <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali GPU Tiler" name="Level 0 primitives" description="Number of primitives tiled to hierarchy level 0."/>
86 <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali GPU Tiler" name="Level 1 primitives" description="Number of primitives tiled to hierarchy level 1."/>
87 <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali GPU Tiler" name="Level 2 primitives" description="Number of primitives tiled to hierarchy level 2."/>
88 <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali GPU Tiler" name="Level 3 primitives" description="Number of primitives tiled to hierarchy level 3."/>
89
90 <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali GPU Tiler" name="Level 4 primitives" description="Number of primitives tiled to hierarchy level 4."/>
91 <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali GPU Tiler" name="Level 5 primitives" description="Number of primitives tiled to hierarchy level 5."/>
92 <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali GPU Tiler" name="Level 6 primitives" description="Number of primitives tiled to hierarchy level 6."/>
93 <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali GPU Tiler" name="Level 7 primitives" description="Number of primitives tiled to hierarchy level 7."/>
94
95 <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali GPU Tiler" name="Primitives tiled to 1 command" description="Number of primitives producing 1 command in tile list."/>
96 <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali GPU Tiler" name="Primitives tiled to 2 commands" description="Number of primitives producing 2 commands in tile list."/>
97 <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali GPU Tiler" name="Primitives tiled to 3 commands" description="Number of primitives producing 3 commands in tile list."/>
98 <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali GPU Tiler" name="Primitives tiled to 4 commands" description="Number of primitives producing 4 commands in tile list."/>
99
100 <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali GPU Tiler" name="Primitives tiled to 4-7 commands" description="Number of primitives producing 4-7 commands in tile list."/>
101 <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali GPU Tiler" name="Primitives tiled to 8-15 commands" description="Number of primitives producing 8-15 commands in tile list."/>
102 <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali GPU Tiler" name="Primitives tiled to 16-63 commands" description="Number of primitives producing 16-63 commands in tile list."/>
103 <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali GPU Tiler" name="Primitives tiled to >= 64 commands" description="Number of primitives producing >= 64 commands in tile list."/>
104
105 <event counter="ARM_Mali-T6xx_COMPRESS_IN" title="Mali GPU Tiler" name="Commands entering compressor" description="Number of commands entering compressor."/>
106 <event counter="ARM_Mali-T6xx_COMPRESS_OUT" title="Mali GPU Tiler" name="Compressed commands from compressor" description="Number of compressed commands produced by compressor."/>
107 <event counter="ARM_Mali-T6xx_COMPRESS_FLUSH" title="Mali GPU Tiler" name="Compressor state flushes" description="Number of compressor state flushes."/>
108 <event counter="ARM_Mali-T6xx_TIMESTAMPS" title="Mali GPU Tiler" name="Timestamps emitted" description="Number of timestamps emitted."/>
109
110 <event counter="ARM_Mali-T6xx_PCACHE_HIT" title="Mali GPU Tiler" name="Pointer-cache hits" description="Number of pointer-cache hits."/>
111 <event counter="ARM_Mali-T6xx_PCACHE_MISS" title="Mali GPU Tiler" name="Pointer-cache misses" description="Number of pointer-cache misses."/>
112 <event counter="ARM_Mali-T6xx_PCACHE_LINE" title="Mali GPU Tiler" name="Pointer-cache line-fils" description="Number of pointer-cache line-fills."/>
113 <event counter="ARM_Mali-T6xx_PCACHE_STALL" title="Mali GPU Tiler" name="Pointer-cache stalls" description="Number of pointer-cache stalls."/>
114
115 <event counter="ARM_Mali-T6xx_WRBUF_HIT" title="Mali GPU Tiler" name="Write-buffer hits" description="Number of write-buffer hits."/>
116 <event counter="ARM_Mali-T6xx_WRBUF_MISS" title="Mali GPU Tiler" name="Write-buffer misses" description="Number of write-buffer misses."/>
117 <event counter="ARM_Mali-T6xx_WRBUF_LINE" title="Mali GPU Tiler" name="Write-buffer full-lines written out" description="Number of complete cache lines written out from the write buffer."/>
118 <event counter="ARM_Mali-T6xx_WRBUF_PARTIAL" title="Mali GPU Tiler" name="Write-buffer partial-lines written out" description="Number of incomplete cache lines written out from the write buffer."/>
119
120 <event counter="ARM_Mali-T6xx_WRBUF_STALL" title="Mali GPU Tiler" name="Write-buffer stalls" description="Number of write-buffer stalls."/>
121 <event counter="ARM_Mali-T6xx_ACTIVE" title="Mali GPU Tiler" name="Tiler active cycles" description="Number of cycles the tiler is active."/>
122 <event counter="ARM_Mali-T6xx_LOADING_DESC" title="Mali GPU Tiler" name="Cycles loading descriptors" description="Number of cycle spent loading descriptors while the tiler frontend is otherwise idle."/>
123 <event counter="ARM_Mali-T6xx_INDEX_WAIT" title="Mali GPU Tiler" name="Cycles index fetch miss" description="Number of cycles the vertex cache could accept an index, but due to a miss, the index fetcher could not provide one."/>
124
125 <event counter="ARM_Mali-T6xx_INDEX_RANGE_WAIT" title="Mali GPU Tiler" name="Cycles index out of range" description="Number of cycles the index fetcher provides an index, but the index is outside the range of currently shaded vertices. Only relevant for fused jobs."/>
126 <event counter="ARM_Mali-T6xx_VERTEX_WAIT" title="Mali GPU Tiler" name="Cycles vertex cache miss" description="Number of cycles the primitive assembly could accept a vertex, but due to a vertex cache miss, the vertex fetcher is unable to provide a vertex."/>
127 <event counter="ARM_Mali-T6xx_PCACHE_WAIT" title="Mali GPU Tiler" name="Cycles pointer cache miss" description="Number of cycles the command compressor could accept a command, but due to a cache miss, the pointer cache is unable to provide the polygon list pointer."/>
128 <event counter="ARM_Mali-T6xx_WRBUF_WAIT" title="Mali GPU Tiler" name="Cycles no write buffer entry" description="Number of cycles a command could be written to the write buffer, but no write buffer entry is available."/>
129
130 <event counter="ARM_Mali-T6xx_BUS_READ" title="Mali GPU Tiler" name="Data beats from L2 cache read." description="Number of data beats (64-bit) on read from the L2 cache."/>
131 <event counter="ARM_Mali-T6xx_BUS_WRITE" title="Mali GPU Tiler" name="Data beats from L2 chache write" description="Number of data beats (64-bit) on written to the L2 cache."/>
132
133 <event counter="ARM_Mali-T6xx_UTLB_STALL" title="Mali GPU Tiler" name="uTLB cycles stall" description="uTLB: Cycles with stall on input AXI address channel."/>
134
135 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_MISS" title="Mali GPU Tiler" name="uTLB replay buffer cache misses" description="uTLB: Number of cache misses on accesses from replay buffer."/>
136 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_FULL" title="Mali GPU Tiler" name="uTLB cycle reply buffer full" description="uTLB: Number of cycles replay buffer is full."/>
137 <event counter="ARM_Mali-T6xx_UTLB_NEW_MISS" title="Mali GPU Tiler" name="uTLB cache misses on new request" description="uTLB: Number of cache misses on new requests."/>
138 <event counter="ARM_Mali-T6xx_UTLB_HIT" title="Mali GPU Tiler" name="uTLB cache hits" description="uTLB: Number of cache hits."/>
139 </category>
140
141 <category name="Mali-T6xx-ShaderCore" per_cpu="no">
142<!--
143 <event counter="ARM_Mali-T6xx_SHADER_CORE_ACTIVE" title="Mali GPU Shader Core" name="Shader core active cycles" description="Number of cycles the shader core active."/>
144-->
145 <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Fragment" name="Fragment active cycles" description="Number of cycles fragment processing was active."/>
146 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Fragment" name="Primitives" description="Number of primitives."/>
147 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Fragment" name="Primitives dropped" description="Primitives dropped due to Polygon List Reader coverage."/>
148 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_DESC" title="Fragment" name="Stall: Waiting for descriptors" description="Number of cycles spent waiting for descriptors / 2."/>
149
150 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_PLR" title="Fragment" name="Stall: Waiting for PLR" description="Cycles spent waiting for Polygon List Reader."/>
151 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_VERT" title="Fragment" name="Stall: Waiting for vertices" description="Cycles spent waiting for vertices."/>
152 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_TRISETUP" title="Fragment" name="Stall: Waiting for trisetup" description="Cycles spent waiting for trisetup."/>
153 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_RAST" title="Fragment" name="Stall: Waiting for rasterizer" description="Cycles spent waiting for rasterizer."/>
154
155 <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Fragment" name="Fragment threads started" description="Number of fragment threads started."/>
156 <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Fragment" name="Dummy threads started" description="Number of dummy threads started."/>
157 <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Fragment" name="Quads rasterized" description="Number of quads rasterized."/>
158 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Fragment" name="Quads doing early ZS test" description="Number of quads doing early ZS test."/>
159
160 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Fragment" name="Quads killed early ZS test" description="Number of quads killed in early ZS test."/>
161 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Fragment" name="Threads doing late ZS test" description="Number of threads doing in late ZS test."/>
162 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Fragment" name="Threads killed late ZS test" description="Number of threads killed in late ZS test."/>
163 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Fragment" name="cycles waiting for physical tile buffers" description="Number of cycles spent waiting while no physical tile buffers were available for rendering."/>
164
165 <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Fragment" name="Tiles rendered" description="Number of tiles rendered."/>
166 <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Fragment" name="Transaction elimination signature matches" description="Transaction elimination signature matches."/>
167 <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Compute" name="Compute active cycles" description="Number of cycles compute processing was active."/>
168 <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Compute" name="Tasks" description="Number of tasks."/>
169
170 <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Compute" name="Compute threads started" description="Number of compute threads started."/>
171 <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Compute" name="Stall: Waiting for descriptors" description="Number of cycles spent waiting for descriptors."/>
172 <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Tripipe" name="Tripipe active cycles" description="Number of cycles the Tripipe was active."/>
173 <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Arithmetic Pipeline" name="Instructions per pipe" description="Number of instruction words in the arithmethic pipelines, divided by the number of arithmethic pipelines."/>
174
175 <event counter="ARM_Mali-T6xx_ARITH_CYCLES_REG" title="Arithmetic Pipeline" name="Stall: Register scheduling" description="Number of cycles lost in the arithmethic pipelines due to register scheduling, divided by the number of arithmethic pipelines."/>
176 <event counter="ARM_Mali-T6xx_ARITH_CYCLES_L0" title="Arithmetic Pipeline" name="Stall: Icache miss per pipe" description="Number of cycles lost in the arithmethic pipelines due to L0 instruction cache misses, divided by the number of arithmethic pipelines."/>
177 <event counter="ARM_Mali-T6xx_ARITH_FRAG_DEPEND" title="Arithmetic Pipeline" name="Stall: Fragment dependency fails per pipe" description="Number of fragment dependency check failures in the arithmethic pipelines, divided by the number of arithmethic pipelines."/>
178 <event counter="ARM_Mali-T6xx_LS_WORDS" title="Load/Store Pipeline" name="Load/Store instruction words completed" description="Number of instruction words completed in the Load/Store pipeline."/>
179
180 <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Load/Store Pipeline" name="Full pipeline issues" description="Number of full pipeline issues in the Load/Store pipeline."/>
181 <event counter="ARM_Mali-T6xx_LS_RESTARTS" title="Load/Store Pipeline" name="Stall: Unpairable instruction" description="Number of restarts due to unpairable instructions in the Load/Store pipeline."/>
182 <event counter="ARM_Mali-T6xx_LS_REISSUES_MISS" title="Load/Store Pipeline" name="Stall: Cache misses" description="Number of full pipe re-issues due to cache misses or TLB misses in the Load/Store pipeline."/>
183 <event counter="ARM_Mali-T6xx_LS_REISSUES_VD" title="Load/Store Pipeline" name="Stall: Varying misses" description="Number of full pipe re-issues due to varying data being unavailable in the Load/Store pipeline."/>
184
185 <event counter="ARM_Mali-T6xx_LS_REISSUE_ATTRIB_MISS" title="Load/Store Pipeline" name="Stall: Attribute cache misses" description="Number of full pipe re-issues due to attribute cache misses in the Load/Store pipeline."/>
186 <event counter="ARM_Mali-T6xx_LS_NO_WB" title="Load/Store Pipeline" name="Writeback not used, pause buffer used" description="Writeback not used, and something into pause buffer in the Load/Store pipeline."/>
187 <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Texturing Pipeline" name="Texturing pipeline instruction words completed" description="Number of instruction words completed in the texturing pipeline."/>
188 <event counter="ARM_Mali-T6xx_TEX_BUBBLES" title="Texturing Pipeline" name="Stall: Waiting for barrier" description="Number of bubbles with threads waiting for barrier in the texturing pipeline."/>
189
190 <event counter="ARM_Mali-T6xx_TEX_WORDS_L0" title="Texturing Pipeline" name="Stall: Icache misses" description="Number of instruction words in the texturing pipeline restart loop 1 due to L0 instruction cache miss."/>
191 <event counter="ARM_Mali-T6xx_TEX_WORDS_DESC" title="Texturing Pipeline" name="Stall: Descriptor misses" description="Number of instruction words in the texturing pipeline restart loop 1 due to descriptor misses."/>
192 <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Texturing Pipeline" name="Threads in loop 2" description="Number of threads in the texturing pipeline through loop 2 address calculation."/>
193 <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Texturing Pipeline" name="Stall: Texture cache misses" description="Number of instructions in the texturing pipeline recirculated due to complete texture cache miss."/>
194
195 <event counter="ARM_Mali-T6xx_TEX_RECIRC_DESC" title="Texturing Pipeline" name="Stall: Surface Descriptor misses" description="Number of instructions in the texturing pipeline recirculated due to surface descriptor miss."/>
196 <event counter="ARM_Mali-T6xx_TEX_RECIRC_MULTI" title="Texturing Pipeline" name="Reissue: multipass" description="Number of instructions in the texturing pipeline recirculated due to multipass."/>
197 <event counter="ARM_Mali-T6xx_TEX_RECIRC_PMISS" title="Texturing Pipeline" name="Stall: Partial misses" description="Number of instructions in the texturing pipeline recirculated due to partial cache miss."/>
198 <event counter="ARM_Mali-T6xx_TEX_RECIRC_CONF" title="Texturing Pipeline" name="Stall: Bank conflict" description="Number of instructions in the texturing pipeline recirculated due to texture cache bank conflict."/>
199
200 <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store Cache."/>
201 <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store Cache."/>
202 <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store Cache."/>
203 <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store Cache."/>
204
205 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store Cache."/>
206 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store Cache."/>
207 <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store Cache."/>
208 <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store Cache."/>
209
210 <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Load/Store Cache" name="Snoops in LSC" description="Snoops in the Load/Store Cache."/>
211 <event counter="ARM_Mali-T6xx_AXI_TLB_STALL" title="AXI uTLB" name="Stall: TLB AXI address channel" description="AXI address channel stall generated."/>
212 <event counter="ARM_Mali-T6xx_AXI_TLB_MIESS" title="AXI uTLB" name="Stall: TLB Cache misses" description="New request cache miss."/>
213 <event counter="ARM_Mali-T6xx_AXI_TLB_TRANSACTION" title="AXI uTLB" name="AXI transactions" description="Number of AXI transactions."/>
214
215 <event counter="ARM_Mali-T6xx_LS_TLB_MISS" title="LS uTLB" name="Cache misses per interface" description="Number of cache misses / number of interfaces."/>
216 <event counter="ARM_Mali-T6xx_LS_TLB_HIT" title="LS uTLB" name="Cache hits per interface" description="Number of cache hits / number of interfaces."/>
217 <event counter="ARM_Mali-T6xx_AXI_BEATS_READ" title="AXI" name="Beats read" description="Number of beats read."/>
218 <event counter="ARM_Mali-T6xx_AXI_BEATS_WRITTEN" title="AXI" name="Beats written" description="Number of beats written."/>
219 </category>
220
221 <category name="Mali-T6xx-L2AndMMU" per_cpu="no">
222 <event counter="ARM_Mali-T6xx_MMU_TABLE_WALK" title="MMU" name="Page table walks" description="Number of page table walks started."/>
223 <event counter="ARM_Mali-T6xx_MMU_REPLAY_MISS" title="MMU" name="Cache misses from replay buffer" description="Number of cache misses on accesses from replay buffer."/>
224 <event counter="ARM_Mali-T6xx_MMU_REPLAY_FULL" title="MMU" name="MMU full replay buffer (cycles)" description="Number of cycles replay buffer is full."/>
225 <event counter="ARM_Mali-T6xx_MMU_NEW_MISS" title="MMU" name="Cache misses on new requests" description="Number of cache misses on new requests."/>
226
227 <event counter="ARM_Mali-T6xx_MMU_HIT" title="MMU" name="MMU cache hits" description="Number of cache hits."/>
228
229 <event counter="ARM_Mali-T6xx_UTLB_STALL" title="uTLB" name="Stall on input AXI (cycles)" description="Cycles with stall on input AXI address channel."/>
230 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_MISS" title="uTLB" name="Cache misses from replay buffer" description="Number of cache misses on accesses from replay buffer."/>
231 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_FULL" title="uTLB" name="uTLB full replay buffer (cycles)" description="Number of cycles replay buffer is full."/>
232 <event counter="ARM_Mali-T6xx_UTLB_NEW_MISS" title="uTLB" name="Cache misses on new requests" description="Number of cache misses on new requests."/>
233
234 <event counter="ARM_Mali-T6xx_UTLB_HIT" title="uTLB" name="uTLB cache hits" description="Number of cache hits."/>
235
236 <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="L2 Cache" name="External bus write beats" description="External bus write beats."/>
237 <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="L2 Cache" name="External bus read beats" description="External bus read beats."/>
238
239 <event counter="ARM_Mali-T6xx_L2_ANY_LOOKUP" title="L2 Cache" name="Transaction/snoop tag lookups" description="A transaction or a snoop response completes the tag lookup."/>
240 <event counter="ARM_Mali-T6xx_L2_READ_LOOKUP" title="L2 Cache" name="Read transaction tag lookups" description="Any read transaction completes the tag lookup."/>
241 <event counter="ARM_Mali-T6xx_L2_SREAD_LOOKUP" title="L2 Cache" name="Shareable read transaction tag lookups" description="Shareable read transaction tag lookup."/>
242 <event counter="ARM_Mali-T6xx_L2_READ_REPLAY" title="L2 Cache" name="Replayed read transactions" description="Any read transaction is replayed (not serialized)."/>
243
244 <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="L2 Cache" name="Read transaction snoops" description="Read transaction issues a snoop."/>
245 <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="L2 Cache" name="L2 Cache read hits" description="A read hits in the L2 Cache."/>
246 <event counter="ARM_Mali-T6xx_L2_CLEAN_MISS" title="L2 Cache" name="CleanUnique misses" description="A CleanUnique misses in the L2 Cache, line allocated without a linefill."/>
247 <event counter="ARM_Mali-T6xx_L2_WRITE_LOOKUP" title="L2 Cache" name="Write transaction tag lookups" description="Any write transaction completes the tag lookup."/>
248
249 <event counter="ARM_Mali-T6xx_L2_SWRITE_LOOKUP" title="L2 write" name="Shareable write transaction tag lookup" description="Shareable write transaction tag lookup."/>
250 <event counter="ARM_Mali-T6xx_L2_WRITE_REPLAY" title="L2 write" name="Replayed write transaction" description="Any write transaction is replayed (not serialized)."/>
251 <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="L2 write" name="Write transaction snoops" description="Write transaction issues a snoop."/>
252 <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="L2 write" name="L2 write hits" description="A write hits in the L2 Cache."/>
253
254 <event counter="ARM_Mali-T6xx_L2_EXT_READ_FULL" title="L2 Cache" name="External read attempted with full BIU" description="External read attempted, but the BIU read buffer is full."/>
255 <event counter="ARM_Mali-T6xx_L2_EXT_READ_HALF" title="L2 Cache" name="External read requested with more then half full BIU" description="External read requested when the BIU read buffer is more than half full."/>
256 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_FULL" title="L2 Cache" name="External write attempted with full BIU" description="External write attempted, but the BIU write buffer is full."/>
257 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_HALF" title="L2 Cache" name="External write requested with more then half full BIU" description="External write requested when the BIU write buffer is more than half full."/>
258
259 <event counter="ARM_Mali-T6xx_L2_EXT_READ" title="L2 Cache" name="External read" description="External read."/>
260 <event counter="ARM_Mali-T6xx_L2_EXT_READ_LINE" title="L2 Cache" name="External read - linefill" description="External read - linefill."/>
261 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE" title="L2 Cache" name="External write." description="External write."/>
262 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_LINE" title="L2 Cache" name="External write - writeback." description="External write - writeback."/>
263
264 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_SMALL" title="L2 Cache" name="External write - burst size less than 64B" description="External write - burst size less than 64B."/>
265 <event counter="ARM_Mali-T6xx_L2_EXT_BARRIER" title="L2 Cache" name="External barrier" description="External barrier (even if disabled)."/>
266 <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="L2 Cache" name="External interconnect stalls (AR)" description="A valid read address (AR) is stalled by the external interconnect."/>
267 <event counter="ARM_Mali-T6xx_L2_EXT_R_BUF_FULL" title="L2 Cache" name="External read stalls (full buffer)" description="External read stalled due to the response buffer being full."/>
268
269 <event counter="ARM_Mali-T6xx_L2_EXT_RD_BUF_FULL" title="L2 Cache" name="External read not allocated" description="External read could not allocate an entry in the read data buffer."/>
270 <event counter="ARM_Mali-T6xx_L2_EXT_R_RAW" title="L2 Cache" name="External read stalled (RAW)" description="External read stalled due to the RAW hazard."/>
271 <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="L2 Cache" name="External interconnect stalls (W channel)" description="Valid write data (W channel) is stalled by the external interconnect."/>
272 <event counter="ARM_Mali-T6xx_L2_EXT_W_BUF_FULL" title="L2 Cache" name="External write stalls (full buffer)" description="External write stalled due to the response buffer being full."/>
273
274 <event counter="ARM_Mali-T6xx_L2_EXT_R_W_HAZARD" title="L2 Cache" name="External read stalled (WAW or WAR)" description="External read stalled due to the WAW or WAR hazard."/>
275 <event counter="ARM_Mali-T6xx_L2_TAG_HAZARD" title="L2 Cache" name="Replayed transactions due to tag hazard" description="A transaction will be replayed due to a tag hazard."/>
276 <event counter="ARM_Mali-T6xx_L2_SNOOP_FULL" title="L2 Cache" name="Cycles with full snoop buffer" description="Counts every cycle when the snoop buffer is full."/>
277 <event counter="ARM_Mali-T6xx_L2_REPLAY_FULL" title="L2 Cache" name="Cycles with full replay buffer" description="Counts every cycle when the replay buffer is full."/>
278 </category>
diff --git a/daemon/events-Scorpion.xml b/daemon/events-Scorpion.xml
index 6c2b6f8..51ed937 100644
--- a/daemon/events-Scorpion.xml
+++ b/daemon/events-Scorpion.xml
@@ -1,112 +1,112 @@
1 <counter_set name="Scorpion_cntX"> 1 <counter_set name="Scorpion_cntX">
2 <counter name="Scorpion_cnt0"/> 2 <counter name="Scorpion_cnt0"/>
3 <counter name="Scorpion_cnt1"/> 3 <counter name="Scorpion_cnt1"/>
4 <counter name="Scorpion_cnt2"/> 4 <counter name="Scorpion_cnt2"/>
5 <counter name="Scorpion_cnt3"/> 5 <counter name="Scorpion_cnt3"/>
6 </counter_set> 6 </counter_set>
7 <category name="Scorpion" counter_set="Scorpion_cntX" per_cpu="yes"> 7 <category name="Scorpion" counter_set="Scorpion_cntX" per_cpu="yes">
8 <event counter="Scorpion_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 8 <event counter="Scorpion_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
15 <event event="0x06" title="Instruction" name="Memory read" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 15 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
16 <event event="0x07" title="Instruction" name="Memory write" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 16 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
17 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/> 21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/> 23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
24 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 24 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
25 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 25 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
26 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
27 <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/> 27 <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>
28 <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/> 28 <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>
29 <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/> 29 <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>
30 <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/> 30 <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>
31 <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/> 31 <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>
32 <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/> 32 <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>
33 <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/> 33 <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>
34 <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/> 34 <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>
35 <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/> 35 <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>
36 <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/> 36 <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>
37 <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/> 37 <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>
38 <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/> 38 <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>
39 <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/> 39 <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>
40 <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/> 40 <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>
41 <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/> 41 <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>
42 <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/> 42 <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>
43 <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/> 43 <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>
44 <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/> 44 <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>
45 <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/> 45 <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>
46 <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/> 46 <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>
47 <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/> 47 <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>
48 <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/> 48 <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>
49 <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/> 49 <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>
50 <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/> 50 <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>
51 <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/> 51 <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>
52 <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/> 52 <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>
53 <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/> 53 <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>
54 <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/> 54 <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>
55 <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/> 55 <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>
56 <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/> 56 <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>
57 <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/> 57 <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>
58 <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/> 58 <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>
59 <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/> 59 <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>
60 <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/> 60 <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>
61 <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/> 61 <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>
62 <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/> 62 <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>
63 <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/> 63 <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>
64 <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/> 64 <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>
65 <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/> 65 <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>
66 <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/> 66 <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>
67 <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/> 67 <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>
68 <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/> 68 <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>
69 <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/> 69 <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>
70 <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/> 70 <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>
71 <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/> 71 <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>
72 <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/> 72 <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>
73 <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/> 73 <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>
74 <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/> 74 <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>
75 <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/> 75 <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>
76 <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/> 76 <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>
77 <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/> 77 <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>
78 <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/> 78 <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>
79 <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/> 79 <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>
80 <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/> 80 <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>
81 <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/> 81 <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>
82 <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/> 82 <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>
83 <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/> 83 <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>
84 <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/> 84 <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>
85 <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/> 85 <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>
86 <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/> 86 <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>
87 <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/> 87 <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>
88 <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/> 88 <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>
89 <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/> 89 <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>
90 <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/> 90 <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>
91 <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/> 91 <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>
92 <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/> 92 <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>
93 <event event="0x8e" title="Scorpion" name="BANK_AB_HIT" description="L2 hit rates bank A/B hits"/> 93 <event event="0x8e" title="Scorpion" name="BANK_AB_HIT" description="L2 hit rates bank A/B hits"/>
94 <event event="0x8f" title="Scorpion" name="BANK_AB_ACCESS" description="L2 hit rates bank A/B accesses"/> 94 <event event="0x8f" title="Scorpion" name="BANK_AB_ACCESS" description="L2 hit rates bank A/B accesses"/>
95 <event event="0x90" title="Scorpion" name="BANK_CD_HIT" description="L2 hit rates bank C/D hits"/> 95 <event event="0x90" title="Scorpion" name="BANK_CD_HIT" description="L2 hit rates bank C/D hits"/>
96 <event event="0x91" title="Scorpion" name="BANK_CD_ACCESS" description="L2 hit rates bank C/D accesses"/> 96 <event event="0x91" title="Scorpion" name="BANK_CD_ACCESS" description="L2 hit rates bank C/D accesses"/>
97 <event event="0x92" title="Scorpion" name="BANK_AB_DSIDE_HIT" description="L2 hit rates bank A/B d-side hits"/> 97 <event event="0x92" title="Scorpion" name="BANK_AB_DSIDE_HIT" description="L2 hit rates bank A/B d-side hits"/>
98 <event event="0x93" title="Scorpion" name="BANK_AB_DSIDE_ACCESS" description="L2 hit rates bank A/B d-side accesses"/> 98 <event event="0x93" title="Scorpion" name="BANK_AB_DSIDE_ACCESS" description="L2 hit rates bank A/B d-side accesses"/>
99 <event event="0x94" title="Scorpion" name="BANK_CD_DSIDE_HIT" description="L2 hit rates bank C/D d-side hits"/> 99 <event event="0x94" title="Scorpion" name="BANK_CD_DSIDE_HIT" description="L2 hit rates bank C/D d-side hits"/>
100 <event event="0x95" title="Scorpion" name="BANK_CD_DSIDE_ACCESS" description="L2 hit rates bank C/D d-side accesses"/> 100 <event event="0x95" title="Scorpion" name="BANK_CD_DSIDE_ACCESS" description="L2 hit rates bank C/D d-side accesses"/>
101 <event event="0x96" title="Scorpion" name="BANK_AB_ISIDE_HIT" description="L2 hit rates bank A/B i-side hits"/> 101 <event event="0x96" title="Scorpion" name="BANK_AB_ISIDE_HIT" description="L2 hit rates bank A/B i-side hits"/>
102 <event event="0x97" title="Scorpion" name="BANK_AB_ISIDE_ACCESS" description="L2 hit rates bank A/B i-side accesses"/> 102 <event event="0x97" title="Scorpion" name="BANK_AB_ISIDE_ACCESS" description="L2 hit rates bank A/B i-side accesses"/>
103 <event event="0x98" title="Scorpion" name="BANK_CD_ISIDE_HIT" description="L2 hit rates bank C/D i-side hits"/> 103 <event event="0x98" title="Scorpion" name="BANK_CD_ISIDE_HIT" description="L2 hit rates bank C/D i-side hits"/>
104 <event event="0x99" title="Scorpion" name="BANK_CD_ISIDE_ACCESS" description="L2 hit rates bank C/D i-side accesses"/> 104 <event event="0x99" title="Scorpion" name="BANK_CD_ISIDE_ACCESS" description="L2 hit rates bank C/D i-side accesses"/>
105 <event event="0x9a" title="Scorpion" name="ISIDE_RD_WAIT" description="fills and castouts cycles that i-side RD requests wait on data from bus"/> 105 <event event="0x9a" title="Scorpion" name="ISIDE_RD_WAIT" description="fills and castouts cycles that i-side RD requests wait on data from bus"/>
106 <event event="0x9b" title="Scorpion" name="DSIDE_RD_WAIT" description="fills and castouts cycles that d-side RD requests wait on data from bus"/> 106 <event event="0x9b" title="Scorpion" name="DSIDE_RD_WAIT" description="fills and castouts cycles that d-side RD requests wait on data from bus"/>
107 <event event="0x9c" title="Scorpion" name="BANK_BYPASS_WRITE" description="fills and castouts bank bypass writes"/> 107 <event event="0x9c" title="Scorpion" name="BANK_BYPASS_WRITE" description="fills and castouts bank bypass writes"/>
108 <event event="0x9d" title="Scorpion" name="BANK_AB_NON_CASTOUT" description="fills and castouts bank A/B non-castout writes to bus"/> 108 <event event="0x9d" title="Scorpion" name="BANK_AB_NON_CASTOUT" description="fills and castouts bank A/B non-castout writes to bus"/>
109 <event event="0x9e" title="Scorpion" name="BANK_AB_L2_CASTOUT" description="fills and castouts bank A/B L2 castouts (granules)"/> 109 <event event="0x9e" title="Scorpion" name="BANK_AB_L2_CASTOUT" description="fills and castouts bank A/B L2 castouts (granules)"/>
110 <event event="0x9f" title="Scorpion" name="BANK_CD_NON_CASTOUT" description="fills and castouts bank C/D non-castout writes to bus"/> 110 <event event="0x9f" title="Scorpion" name="BANK_CD_NON_CASTOUT" description="fills and castouts bank C/D non-castout writes to bus"/>
111 <event event="0xa0" title="Scorpion" name="BANK_CD_L2_CASTOUT" description="fills and castouts bank C/D L2 castouts (granules)"/> 111 <event event="0xa0" title="Scorpion" name="BANK_CD_L2_CASTOUT" description="fills and castouts bank C/D L2 castouts (granules)"/>
112 </category> 112 </category>
diff --git a/daemon/events-ScorpionMP.xml b/daemon/events-ScorpionMP.xml
index 87f5657..d3dd430 100644
--- a/daemon/events-ScorpionMP.xml
+++ b/daemon/events-ScorpionMP.xml
@@ -1,95 +1,95 @@
1 <counter_set name="ScorpionMP_cntX"> 1 <counter_set name="ScorpionMP_cntX">
2 <counter name="ScorpionMP_cnt0"/> 2 <counter name="ScorpionMP_cnt0"/>
3 <counter name="ScorpionMP_cnt1"/> 3 <counter name="ScorpionMP_cnt1"/>
4 <counter name="ScorpionMP_cnt2"/> 4 <counter name="ScorpionMP_cnt2"/>
5 <counter name="ScorpionMP_cnt3"/> 5 <counter name="ScorpionMP_cnt3"/>
6 </counter_set> 6 </counter_set>
7 <category name="ScorpionMP" counter_set="ScorpionMP_cntX" per_cpu="yes"> 7 <category name="ScorpionMP" counter_set="ScorpionMP_cntX" per_cpu="yes">
8 <event counter="ScorpionMP_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 8 <event counter="ScorpionMP_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
15 <event event="0x06" title="Instruction" name="Memory read" alias="MemoryRead" description="Memory-reading instruction architecturally executed"/> 15 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
16 <event event="0x07" title="Instruction" name="Memory write" alias="MemoryWrite" description="Memory-writing instruction architecturally executed"/> 16 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
17 <event event="0x08" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instruction architecturally executed"/> 17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/> 21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/> 22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/> 23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
24 <event event="0x0f" title="Memory" name="Unaligned access" alias="UnalignedAccess" description="Unaligned access architecturally executed"/> 24 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
25 <event event="0x10" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mispredicted or not predicted"/> 25 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
26 <event event="0x12" title="Branch" name="Potential prediction" alias="PotentialPrediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
27 <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/> 27 <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>
28 <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/> 28 <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>
29 <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/> 29 <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>
30 <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/> 30 <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>
31 <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/> 31 <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>
32 <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/> 32 <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>
33 <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/> 33 <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>
34 <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/> 34 <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>
35 <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/> 35 <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>
36 <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/> 36 <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>
37 <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/> 37 <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>
38 <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/> 38 <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>
39 <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/> 39 <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>
40 <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/> 40 <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>
41 <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/> 41 <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>
42 <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/> 42 <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>
43 <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/> 43 <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>
44 <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/> 44 <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>
45 <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/> 45 <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>
46 <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/> 46 <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>
47 <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/> 47 <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>
48 <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/> 48 <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>
49 <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/> 49 <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>
50 <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/> 50 <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>
51 <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/> 51 <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>
52 <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/> 52 <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>
53 <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/> 53 <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>
54 <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/> 54 <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>
55 <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/> 55 <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>
56 <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/> 56 <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>
57 <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/> 57 <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>
58 <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/> 58 <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>
59 <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/> 59 <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>
60 <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/> 60 <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>
61 <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/> 61 <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>
62 <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/> 62 <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>
63 <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/> 63 <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>
64 <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/> 64 <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>
65 <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/> 65 <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>
66 <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/> 66 <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>
67 <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/> 67 <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>
68 <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/> 68 <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>
69 <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/> 69 <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>
70 <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/> 70 <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>
71 <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/> 71 <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>
72 <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/> 72 <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>
73 <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/> 73 <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>
74 <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/> 74 <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>
75 <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/> 75 <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>
76 <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/> 76 <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>
77 <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/> 77 <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>
78 <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/> 78 <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>
79 <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/> 79 <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>
80 <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/> 80 <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>
81 <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/> 81 <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>
82 <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/> 82 <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>
83 <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/> 83 <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>
84 <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/> 84 <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>
85 <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/> 85 <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>
86 <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/> 86 <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>
87 <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/> 87 <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>
88 <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/> 88 <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>
89 <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/> 89 <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>
90 <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/> 90 <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>
91 <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/> 91 <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>
92 <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/> 92 <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>
93 <event event="0x8e" title="ScorpionMP" name="NUM_BARRIERS" description="Barriers"/> 93 <event event="0x8e" title="ScorpionMP" name="NUM_BARRIERS" description="Barriers"/>
94 <event event="0x8f" title="ScorpionMP" name="BARRIER_CYCLES" description="Barrier cycles"/> 94 <event event="0x8f" title="ScorpionMP" name="BARRIER_CYCLES" description="Barrier cycles"/>
95 </category> 95 </category>
diff --git a/daemon/main.cpp b/daemon/main.cpp
index df6913b..d972913 100644
--- a/daemon/main.cpp
+++ b/daemon/main.cpp
@@ -195,8 +195,16 @@ struct cmdline_t parseCommandLine(int argc, char** argv) {
195 struct cmdline_t cmdline; 195 struct cmdline_t cmdline;
196 cmdline.port = 8080; 196 cmdline.port = 8080;
197 cmdline.module = NULL; 197 cmdline.module = NULL;
198 char version_string[256]; // arbitrary length to hold the version information
198 int c; 199 int c;
199 200
201 // build the version string
202 if (PROTOCOL_VERSION < PROTOCOL_DEV) {
203 snprintf(version_string, sizeof(version_string), "Streamline gatord version %d (DS-5 v5.%d)", PROTOCOL_VERSION, PROTOCOL_VERSION + 1);
204 } else {
205 snprintf(version_string, sizeof(version_string), "Streamline gatord development version %d", PROTOCOL_VERSION);
206 }
207
200 while ((c = getopt(argc, argv, "hvp:s:c:e:m:")) != -1) { 208 while ((c = getopt(argc, argv, "hvp:s:c:e:m:")) != -1) {
201 switch(c) { 209 switch(c) {
202 case 'c': 210 case 'c':
@@ -217,19 +225,19 @@ struct cmdline_t parseCommandLine(int argc, char** argv) {
217 case 'h': 225 case 'h':
218 case '?': 226 case '?':
219 logg->logError(__FILE__, __LINE__, 227 logg->logError(__FILE__, __LINE__,
220 "Streamline gatord version %d. All parameters are optional:\n" 228 "%s. All parameters are optional:\n"
221 "-c config_xml\tpath and filename of the configuration.xml to use\n" 229 "-c config_xml path and filename of the configuration.xml to use\n"
222 "-e events_xml\tpath and filename of the events.xml to use\n" 230 "-e events_xml path and filename of the events.xml to use\n"
223 "-h\t\tthis help page\n" 231 "-h this help page\n"
224 "-m module\tpath and filename of gator.ko\n" 232 "-m module path and filename of gator.ko\n"
225 "-p port_number\tport upon which the server listens; default is 8080\n" 233 "-p port_number port upon which the server listens; default is 8080\n"
226 "-s session_xml\tpath and filename of a session xml used for local capture\n" 234 "-s session_xml path and filename of a session xml used for local capture\n"
227 "-v\t\tversion information\n" 235 "-v version information\n"
228 , PROTOCOL_VERSION); 236 , version_string);
229 handleException(); 237 handleException();
230 break; 238 break;
231 case 'v': 239 case 'v':
232 logg->logError(__FILE__, __LINE__, "Streamline gatord version %d", PROTOCOL_VERSION); 240 logg->logError(__FILE__, __LINE__, version_string);
233 handleException(); 241 handleException();
234 break; 242 break;
235 } 243 }
@@ -255,7 +263,7 @@ int main(int argc, char** argv, char* envp[]) {
255 logg = new Logging(DEBUG); // Set up global thread-safe logging 263 logg = new Logging(DEBUG); // Set up global thread-safe logging
256 util = new OlyUtility(); // Set up global utility class 264 util = new OlyUtility(); // Set up global utility class
257 265
258 prctl(PR_SET_NAME, (unsigned int)&"gatord-main", 0, 0, 0); 266 prctl(PR_SET_NAME, (unsigned long)&"gatord-main", 0, 0, 0);
259 pthread_mutex_init(&numSessions_mutex, NULL); 267 pthread_mutex_init(&numSessions_mutex, NULL);
260 268
261 signal(SIGINT, handler); 269 signal(SIGINT, handler);
diff --git a/daemon/mxml/mxml-file.c b/daemon/mxml/mxml-file.c
index 9927040..7860ee5 100644
--- a/daemon/mxml/mxml-file.c
+++ b/daemon/mxml/mxml-file.c
@@ -1287,7 +1287,8 @@ mxml_file_getc(void *p, /* I - Pointer to file */
1287 * Multi-word UTF-16 char... 1287 * Multi-word UTF-16 char...
1288 */ 1288 */
1289 1289
1290 int lch = (getc(fp) << 8) | getc(fp); 1290 int lch = (getc(fp) << 8);
1291 lch |= getc(fp);
1291 1292
1292 if (lch < 0xdc00 || lch >= 0xdfff) 1293 if (lch < 0xdc00 || lch >= 0xdfff)
1293 return (EOF); 1294 return (EOF);
@@ -1315,7 +1316,8 @@ mxml_file_getc(void *p, /* I - Pointer to file */
1315 * Multi-word UTF-16 char... 1316 * Multi-word UTF-16 char...
1316 */ 1317 */
1317 1318
1318 int lch = getc(fp) | (getc(fp) << 8); 1319 int lch = getc(fp);
1320 lch |= (getc(fp) << 8);
1319 1321
1320 if (lch < 0xdc00 || lch >= 0xdfff) 1322 if (lch < 0xdc00 || lch >= 0xdfff)
1321 return (EOF); 1323 return (EOF);
diff --git a/driver/Makefile b/driver/Makefile
index 667637e..025dd9e 100644
--- a/driver/Makefile
+++ b/driver/Makefile
@@ -17,10 +17,13 @@ gator-y += gator_events_mmaped.o
17 17
18ifneq ($(GATOR_WITH_MALI_SUPPORT),) 18ifneq ($(GATOR_WITH_MALI_SUPPORT),)
19ifeq ($(GATOR_WITH_MALI_SUPPORT),MALI_T6xx) 19ifeq ($(GATOR_WITH_MALI_SUPPORT),MALI_T6xx)
20gator-y += gator_events_mali_t6xx.o 20gator-y += gator_events_mali_t6xx.o \
21 gator_events_mali_t6xx_hw.o
22include $(M)/mali_t6xx.mk
21else 23else
22gator-y += gator_events_mali.o 24gator-y += gator_events_mali_400.o
23endif 25endif
26gator-y += gator_events_mali_common.o
24EXTRA_CFLAGS += -DMALI_SUPPORT=$(GATOR_WITH_MALI_SUPPORT) 27EXTRA_CFLAGS += -DMALI_SUPPORT=$(GATOR_WITH_MALI_SUPPORT)
25endif 28endif
26 29
diff --git a/driver/gator_annotate.c b/driver/gator_annotate.c
index b2288b3..b444789 100644
--- a/driver/gator_annotate.c
+++ b/driver/gator_annotate.c
@@ -43,9 +43,9 @@ static ssize_t annotate_write(struct file *file, char const __user *buf, size_t
43 if (*offset) 43 if (*offset)
44 return -EINVAL; 44 return -EINVAL;
45 45
46 if (!collect_annotations) { 46 if (!collect_annotations)
47 // Not collecting annotations, tell the caller everything was written
47 return count_orig; 48 return count_orig;
48 }
49 49
50 cpu = 0; // Annotation only uses a single per-cpu buffer as the data must be in order to the engine 50 cpu = 0; // Annotation only uses a single per-cpu buffer as the data must be in order to the engine
51 51
@@ -64,6 +64,8 @@ static ssize_t annotate_write(struct file *file, char const __user *buf, size_t
64 size = count < available ? count : available; 64 size = count < available ? count : available;
65 65
66 if (size <= 0) { 66 if (size <= 0) {
67 // Buffer is full but don't return an error. Instead return 0 so the
68 // caller knows nothing was written and they can try again.
67 size = 0; 69 size = 0;
68 goto annotate_write_out; 70 goto annotate_write_out;
69 } 71 }
@@ -115,8 +117,9 @@ static int annotate_release(struct inode *inode, struct file *file)
115 // synchronize between cores 117 // synchronize between cores
116 spin_lock(&annotate_lock); 118 spin_lock(&annotate_lock);
117 119
118 if (per_cpu(gator_buffer, cpu)[ANNOTATE_BUF] && buffer_check_space(cpu, ANNOTATE_BUF, MAXSIZE_PACK64 + 2 * MAXSIZE_PACK32)) { 120 if (per_cpu(gator_buffer, cpu)[ANNOTATE_BUF] && buffer_check_space(cpu, ANNOTATE_BUF, MAXSIZE_PACK64 + 3 * MAXSIZE_PACK32)) {
119 uint32_t tid = current->pid; 121 uint32_t tid = current->pid;
122 gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, smp_processor_id());
120 gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, tid); 123 gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, tid);
121 gator_buffer_write_packed_int64(cpu, ANNOTATE_BUF, 0); // time 124 gator_buffer_write_packed_int64(cpu, ANNOTATE_BUF, 0); // time
122 gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, 0); // size 125 gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, 0); // size
diff --git a/driver/gator_cookies.c b/driver/gator_cookies.c
index df14d09..d7d8e84 100644
--- a/driver/gator_cookies.c
+++ b/driver/gator_cookies.c
@@ -27,8 +27,6 @@ static void wq_cookie_handler(struct work_struct *unused);
27DECLARE_WORK(cookie_work, wq_cookie_handler); 27DECLARE_WORK(cookie_work, wq_cookie_handler);
28static struct timer_list app_process_wake_up_timer; 28static struct timer_list app_process_wake_up_timer;
29static void app_process_wake_up_handler(unsigned long unused_data); 29static void app_process_wake_up_handler(unsigned long unused_data);
30static struct timer_list app_process_wake_up_timer;
31static void app_process_wake_up_handler(unsigned long unused_data);
32 30
33static uint32_t cookiemap_code(uint64_t value64) { 31static uint32_t cookiemap_code(uint64_t value64) {
34 uint32_t value = (uint32_t)((value64 >> 32) + value64); 32 uint32_t value = (uint32_t)((value64 >> 32) + value64);
@@ -172,6 +170,7 @@ static int translate_app_process(char** text, int cpu, struct task_struct * task
172 170
173 translate_buffer_write_int(cpu, (unsigned int)task); 171 translate_buffer_write_int(cpu, (unsigned int)task);
174 translate_buffer_write_int(cpu, (unsigned int)vma); 172 translate_buffer_write_int(cpu, (unsigned int)vma);
173
175 mod_timer(&app_process_wake_up_timer, jiffies + 1); 174 mod_timer(&app_process_wake_up_timer, jiffies + 1);
176 goto out; 175 goto out;
177 } 176 }
@@ -382,7 +381,7 @@ static int cookies_initialize(void)
382 gator_crc32_table[i] = crc; 381 gator_crc32_table[i] = crc;
383 } 382 }
384 383
385 setup_timer(&app_process_wake_up_timer, app_process_wake_up_handler, 0); 384 setup_timer(&app_process_wake_up_timer, app_process_wake_up_handler, 0);
386 385
387cookie_setup_error: 386cookie_setup_error:
388 return err; 387 return err;
diff --git a/driver/gator_ebs.c b/driver/gator_ebs.c
index 1208d69..6abdfa4 100644
--- a/driver/gator_ebs.c
+++ b/driver/gator_ebs.c
@@ -23,10 +23,8 @@ extern unsigned long pmnc_event[];
23extern unsigned long pmnc_count[]; 23extern unsigned long pmnc_count[];
24extern unsigned long pmnc_key[]; 24extern unsigned long pmnc_key[];
25 25
26static DEFINE_PER_CPU(struct perf_event *, pevent);
27static DEFINE_PER_CPU(struct perf_event_attr *, pevent_attr); 26static DEFINE_PER_CPU(struct perf_event_attr *, pevent_attr);
28static DEFINE_PER_CPU(int, key); 27static DEFINE_PER_CPU(int, key);
29static DEFINE_PER_CPU(unsigned int, prev_value);
30 28
31#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0) 29#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
32static void ebs_overflow_handler(struct perf_event *event, int unused, struct perf_sample_data *data, struct pt_regs *regs) 30static void ebs_overflow_handler(struct perf_event *event, int unused, struct perf_sample_data *data, struct pt_regs *regs)
@@ -36,7 +34,7 @@ static void ebs_overflow_handler(struct perf_event *event, struct perf_sample_da
36{ 34{
37 int cpu = smp_processor_id(); 35 int cpu = smp_processor_id();
38 36
39 if (event != per_cpu(pevent, cpu)) 37 if (event != per_cpu(pevent_ebs, cpu))
40 return; 38 return;
41 39
42 // Output backtrace 40 // Output backtrace
@@ -54,9 +52,9 @@ static void gator_event_sampling_online_dispatch(int cpu)
54 return; 52 return;
55 53
56#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0) 54#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
57 ev = per_cpu(pevent, cpu) = perf_event_create_kernel_counter(per_cpu(pevent_attr, cpu), cpu, 0, ebs_overflow_handler); 55