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authorJon Medhurst2013-06-17 07:29:43 -0500
committerJon Medhurst2013-06-17 07:29:43 -0500
commit567aa4e79aa4450eb32528b6acda62f18ae76596 (patch)
tree747c381b968e6d044cdaefa4a64c5295566e2764
parent4187fbf69e3cd436cfd3c93948492296e99e918c (diff)
parentf15a1807ecf7af6dd0cac9e175ff00bf06d7c304 (diff)
downloadarm-ds5-gator-567aa4e79aa4450eb32528b6acda62f18ae76596.tar.gz
arm-ds5-gator-567aa4e79aa4450eb32528b6acda62f18ae76596.tar.xz
arm-ds5-gator-567aa4e79aa4450eb32528b6acda62f18ae76596.zip
Merge branch 'master' into android
-rwxr-xr-x[-rw-r--r--]README_Streamline.txt4
-rw-r--r--daemon/Android.mk1
-rw-r--r--daemon/Buffer.cpp199
-rw-r--r--daemon/CapturedXML.cpp22
-rw-r--r--daemon/Child.cpp11
-rw-r--r--daemon/ConfigurationXML.cpp48
-rw-r--r--daemon/Counter.h36
-rw-r--r--daemon/EventsXML.cpp70
-rw-r--r--daemon/EventsXML.h18
-rw-r--r--daemon/Fifo.cpp149
-rw-r--r--daemon/Fifo.h39
-rw-r--r--daemon/Hwmon.cpp61
-rw-r--r--daemon/KMod.cpp22
-rw-r--r--daemon/LocalCapture.cpp5
-rw-r--r--daemon/OlySocket.cpp4
-rw-r--r--daemon/OlyUtility.cpp4
-rw-r--r--daemon/OlyUtility.h2
-rw-r--r--daemon/SessionData.h4
-rw-r--r--daemon/StreamlineSetup.cpp74
-rw-r--r--daemon/StreamlineSetup.h2
-rw-r--r--daemon/common.mk2
-rw-r--r--daemon/configuration.xml102
-rw-r--r--daemon/escape.c10
-rw-r--r--daemon/events-ARM11.xml2
-rw-r--r--daemon/events-ARM11MPCore.xml2
-rw-r--r--daemon/events-CCI-400.xml2
-rw-r--r--daemon/events-Cortex-A15.xml2
-rw-r--r--daemon/events-Cortex-A5.xml2
-rw-r--r--daemon/events-Cortex-A53.xml152
-rw-r--r--daemon/events-Cortex-A57.xml154
-rw-r--r--daemon/events-Cortex-A7.xml2
-rw-r--r--daemon/events-Cortex-A8.xml4
-rw-r--r--daemon/events-Cortex-A9.xml2
-rw-r--r--daemon/events-Krait-architected.xml2
-rw-r--r--daemon/events-Linux.xml6
-rw-r--r--daemon/events-Mali-T6xx.xml30
-rw-r--r--daemon/events-Mali-T6xx_hw.xml349
-rw-r--r--daemon/events-Scorpion.xml2
-rw-r--r--daemon/events-ScorpionMP.xml2
-rw-r--r--driver/gator_backtrace.c76
-rw-r--r--driver/gator_events_l2c-310.c21
-rw-r--r--driver/gator_events_mali_t6xx_hw.c40
-rw-r--r--driver/gator_events_perf_pmu.c18
-rw-r--r--driver/gator_iks.c20
-rw-r--r--driver/gator_main.c126
-rw-r--r--driver/gator_marshaling.c12
-rw-r--r--driver/gator_pack.c195
-rw-r--r--driver/gator_trace_gpu.c5
-rw-r--r--driver/gator_trace_sched.c48
49 files changed, 984 insertions, 1181 deletions
diff --git a/README_Streamline.txt b/README_Streamline.txt
index 5472c07..6a55f60 100644..100755
--- a/README_Streamline.txt
+++ b/README_Streamline.txt
@@ -30,7 +30,6 @@ menuconfig options (depending on the kernel version, the location of these confi
30 - CPU Frequency scaling 30 - CPU Frequency scaling
31 - [*] CPU Frequency scaling (enables CONFIG_CPU_FREQ) 31 - [*] CPU Frequency scaling (enables CONFIG_CPU_FREQ)
32- Kernel hacking 32- Kernel hacking
33 - [*] Mutex debugging: basic checks (optional, enables CONFIG_DEBUG_MUTEXES)
34 - [*] Compile the kernel with debug info (optional, enables CONFIG_DEBUG_INFO) 33 - [*] Compile the kernel with debug info (optional, enables CONFIG_DEBUG_INFO)
35 - [*] Tracers 34 - [*] Tracers
36 - [*] Trace process context switches and events (#) 35 - [*] Trace process context switches and events (#)
@@ -43,7 +42,6 @@ CONFIG_PROFILING
43CONFIG_HIGH_RES_TIMERS 42CONFIG_HIGH_RES_TIMERS
44CONFIG_LOCAL_TIMERS (for SMP systems) 43CONFIG_LOCAL_TIMERS (for SMP systems)
45CONFIG_PERF_EVENTS and CONFIG_HW_PERF_EVENTS (kernel versions 3.0 and greater) 44CONFIG_PERF_EVENTS and CONFIG_HW_PERF_EVENTS (kernel versions 3.0 and greater)
46CONFIG_DEBUG_MUTEXES (optional, provides 'mutex' as a reason code when a thread stops running)
47CONFIG_DEBUG_INFO (optional, used for analyzing the kernel) 45CONFIG_DEBUG_INFO (optional, used for analyzing the kernel)
48CONFIG_CPU_FREQ (optional, provides frequency setting of the CPU) 46CONFIG_CPU_FREQ (optional, provides frequency setting of the CPU)
49 47
@@ -101,7 +99,7 @@ Further, the l2c-310 counter can be disabled by providing an offset of zero, ex:
101*** Compiling an application or shared library *** 99*** Compiling an application or shared library ***
102 100
103Recommended compiler settings: 101Recommended compiler settings:
104 "-g": Debug symbols needed for best analysis results. 102 "-g": Debug information, such as line numbers, needed for best analysis results.
105 "-fno-inline": Speed improvement when processing the image files and most accurate analysis results. 103 "-fno-inline": Speed improvement when processing the image files and most accurate analysis results.
106 "-fno-omit-frame-pointer": ARM EABI frame pointers (Code Sourcery cross compiler) allow recording of the call stack with each sample taken when in ARM state (i.e. not -mthumb). 104 "-fno-omit-frame-pointer": ARM EABI frame pointers (Code Sourcery cross compiler) allow recording of the call stack with each sample taken when in ARM state (i.e. not -mthumb).
107 "-marm": This option is required if your compiler is configured with --with-mode=thumb, otherwise call stack unwinding will not work. 105 "-marm": This option is required if your compiler is configured with --with-mode=thumb, otherwise call stack unwinding will not work.
diff --git a/daemon/Android.mk b/daemon/Android.mk
index 86483f3..4798a0a 100644
--- a/daemon/Android.mk
+++ b/daemon/Android.mk
@@ -12,6 +12,7 @@ LOCAL_SRC_FILES := \
12 Collector.cpp \ 12 Collector.cpp \
13 ConfigurationXML.cpp \ 13 ConfigurationXML.cpp \
14 Driver.cpp \ 14 Driver.cpp \
15 EventsXML.cpp \
15 Fifo.cpp \ 16 Fifo.cpp \
16 Hwmon.cpp \ 17 Hwmon.cpp \
17 KMod.cpp \ 18 KMod.cpp \
diff --git a/daemon/Buffer.cpp b/daemon/Buffer.cpp
index ee391bc..56cf42c 100644
--- a/daemon/Buffer.cpp
+++ b/daemon/Buffer.cpp
@@ -140,173 +140,46 @@ void Buffer::check (const uint64_t time) {
140 } 140 }
141} 141}
142 142
143void Buffer::packInt (const int32_t x) { 143void Buffer::packInt (int32_t x) {
144 const int write0 = (writePos + 0) & mask; 144 int packedBytes = 0;
145 const int write1 = (writePos + 1) & mask; 145 int more = true;
146 146 while (more) {
147 if ((x & 0xffffff80) == 0) { 147 // low order 7 bits of x
148 buf[write0] = x & 0x7f; 148 char b = x & 0x7f;
149 writePos = write1; 149 x >>= 7;
150 } else if ((x & 0xffffc000) == 0) { 150
151 const int write2 = (writePos + 2) & mask; 151 if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
152 buf[write0] = x | 0x80; 152 more = false;
153 buf[write1] = (x >> 7) & 0x7f; 153 } else {
154 writePos = write2; 154 b |= 0x80;
155 } else if ((x & 0xffe00000) == 0) { 155 }
156 const int write2 = (writePos + 2) & mask; 156
157 const int write3 = (writePos + 3) & mask; 157 buf[(writePos + packedBytes) & mask] = b;
158 buf[write0] = x | 0x80; 158 packedBytes++;
159 buf[write1] = (x >> 7) | 0x80;
160 buf[write2] = (x >> 14) & 0x7f;
161 writePos = write3;
162 } else if ((x & 0xf0000000) == 0) {
163 const int write2 = (writePos + 2) & mask;
164 const int write3 = (writePos + 3) & mask;
165 const int write4 = (writePos + 4) & mask;
166 buf[write0] = x | 0x80;
167 buf[write1] = (x >> 7) | 0x80;
168 buf[write2] = (x >> 14) | 0x80;
169 buf[write3] = (x >> 21) & 0x7f;
170 writePos = write4;
171 } else {
172 const int write2 = (writePos + 2) & mask;
173 const int write3 = (writePos + 3) & mask;
174 const int write4 = (writePos + 4) & mask;
175 const int write5 = (writePos + 5) & mask;
176 buf[write0] = x | 0x80;
177 buf[write1] = (x >> 7) | 0x80;
178 buf[write2] = (x >> 14) | 0x80;
179 buf[write3] = (x >> 21) | 0x80;
180 buf[write4] = (x >> 28) & 0x0f;
181 writePos = write5;
182 } 159 }
160
161 writePos = (writePos + packedBytes) & mask;
183} 162}
184 163
185void Buffer::packInt64 (const int64_t x) { 164void Buffer::packInt64 (int64_t x) {
186 const int write0 = (writePos + 0) & mask; 165 int packedBytes = 0;
187 const int write1 = (writePos + 1) & mask; 166 int more = true;
188 167 while (more) {
189 if ((x & 0xffffffffffffff80LL) == 0) { 168 // low order 7 bits of x
190 buf[write0] = x & 0x7f; 169 char b = x & 0x7f;
191 writePos = write1; 170 x >>= 7;
192 } else if ((x & 0xffffffffffffc000LL) == 0) { 171
193 const int write2 = (writePos + 2) & mask; 172 if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
194 buf[write0] = x | 0x80; 173 more = false;
195 buf[write1] = (x >> 7) & 0x7f; 174 } else {
196 writePos = write2; 175 b |= 0x80;
197 } else if ((x & 0xffffffffffe00000LL) == 0) { 176 }
198 const int write2 = (writePos + 2) & mask; 177
199 const int write3 = (writePos + 3) & mask; 178 buf[(writePos + packedBytes) & mask] = b;
200 buf[write0] = x | 0x80; 179 packedBytes++;
201 buf[write1] = (x >> 7) | 0x80;
202 buf[write2] = (x >> 14) & 0x7f;
203 writePos = write3;
204 } else if ((x & 0xfffffffff0000000LL) == 0) {
205 const int write2 = (writePos + 2) & mask;
206 const int write3 = (writePos + 3) & mask;
207 const int write4 = (writePos + 4) & mask;
208 buf[write0] = x | 0x80;
209 buf[write1] = (x >> 7) | 0x80;
210 buf[write2] = (x >> 14) | 0x80;
211 buf[write3] = (x >> 21) & 0x7f;
212 writePos = write4;
213 } else if ((x & 0xfffffff800000000LL) == 0) {
214 const int write2 = (writePos + 2) & mask;
215 const int write3 = (writePos + 3) & mask;
216 const int write4 = (writePos + 4) & mask;
217 const int write5 = (writePos + 5) & mask;
218 buf[write0] = x | 0x80;
219 buf[write1] = (x >> 7) | 0x80;
220 buf[write2] = (x >> 14) | 0x80;
221 buf[write3] = (x >> 21) | 0x80;
222 buf[write4] = (x >> 28) & 0x7f;
223 writePos = write5;
224 } else if ((x & 0xfffffc0000000000LL) == 0) {
225 const int write2 = (writePos + 2) & mask;
226 const int write3 = (writePos + 3) & mask;
227 const int write4 = (writePos + 4) & mask;
228 const int write5 = (writePos + 5) & mask;
229 const int write6 = (writePos + 6) & mask;
230 buf[write0] = x | 0x80;
231 buf[write1] = (x >> 7) | 0x80;
232 buf[write2] = (x >> 14) | 0x80;
233 buf[write3] = (x >> 21) | 0x80;
234 buf[write4] = (x >> 28) | 0x80;
235 buf[write5] = (x >> 35) & 0x7f;
236 writePos = write6;
237 } else if ((x & 0xfffe000000000000LL) == 0) {
238 const int write2 = (writePos + 2) & mask;
239 const int write3 = (writePos + 3) & mask;
240 const int write4 = (writePos + 4) & mask;
241 const int write5 = (writePos + 5) & mask;
242 const int write6 = (writePos + 6) & mask;
243 const int write7 = (writePos + 7) & mask;
244 buf[write0] = x | 0x80;
245 buf[write1] = (x >> 7) | 0x80;
246 buf[write2] = (x >> 14) | 0x80;
247 buf[write3] = (x >> 21) | 0x80;
248 buf[write4] = (x >> 28) | 0x80;
249 buf[write5] = (x >> 35) | 0x80;
250 buf[write6] = (x >> 42) & 0x7f;
251 writePos = write7;
252 } else if ((x & 0xff00000000000000LL) == 0) {
253 const int write2 = (writePos + 2) & mask;
254 const int write3 = (writePos + 3) & mask;
255 const int write4 = (writePos + 4) & mask;
256 const int write5 = (writePos + 5) & mask;
257 const int write6 = (writePos + 6) & mask;
258 const int write7 = (writePos + 7) & mask;
259 const int write8 = (writePos + 8) & mask;
260 buf[write0] = x | 0x80;
261 buf[write1] = (x >> 7) | 0x80;
262 buf[write2] = (x >> 14) | 0x80;
263 buf[write3] = (x >> 21) | 0x80;
264 buf[write4] = (x >> 28) | 0x80;
265 buf[write5] = (x >> 35) | 0x80;
266 buf[write6] = (x >> 42) | 0x80;
267 buf[write7] = (x >> 49) & 0x7f;
268 writePos = write8;
269 } else if ((x & 0x8000000000000000LL) == 0) {
270 const int write2 = (writePos + 2) & mask;
271 const int write3 = (writePos + 3) & mask;
272 const int write4 = (writePos + 4) & mask;
273 const int write5 = (writePos + 5) & mask;
274 const int write6 = (writePos + 6) & mask;
275 const int write7 = (writePos + 7) & mask;
276 const int write8 = (writePos + 8) & mask;
277 const int write9 = (writePos + 9) & mask;
278 buf[write0] = x | 0x80;
279 buf[write1] = (x >> 7) | 0x80;
280 buf[write2] = (x >> 14) | 0x80;
281 buf[write3] = (x >> 21) | 0x80;
282 buf[write4] = (x >> 28) | 0x80;
283 buf[write5] = (x >> 35) | 0x80;
284 buf[write6] = (x >> 42) | 0x80;
285 buf[write7] = (x >> 49) | 0x80;
286 buf[write8] = (x >> 56) & 0x7f;
287 writePos = write9;
288 } else {
289 const int write2 = (writePos + 2) & mask;
290 const int write3 = (writePos + 3) & mask;
291 const int write4 = (writePos + 4) & mask;
292 const int write5 = (writePos + 5) & mask;
293 const int write6 = (writePos + 6) & mask;
294 const int write7 = (writePos + 7) & mask;
295 const int write8 = (writePos + 8) & mask;
296 const int write9 = (writePos + 9) & mask;
297 const int write10 = (writePos + 10) & mask;
298 buf[write0] = x | 0x80;
299 buf[write1] = (x >> 7) | 0x80;
300 buf[write2] = (x >> 14) | 0x80;
301 buf[write3] = (x >> 21) | 0x80;
302 buf[write4] = (x >> 28) | 0x80;
303 buf[write5] = (x >> 35) | 0x80;
304 buf[write6] = (x >> 42) | 0x80;
305 buf[write7] = (x >> 49) | 0x80;
306 buf[write8] = (x >> 56) | 0x80;
307 buf[write9] = (x >> 63) & 0x7f;
308 writePos = write10;
309 } 180 }
181
182 writePos = (writePos + packedBytes) & mask;
310} 183}
311 184
312void Buffer::frame () { 185void Buffer::frame () {
diff --git a/daemon/CapturedXML.cpp b/daemon/CapturedXML.cpp
index 8b037cb..af726df 100644
--- a/daemon/CapturedXML.cpp
+++ b/daemon/CapturedXML.cpp
@@ -51,30 +51,12 @@ mxml_node_t* CapturedXML::getTree(bool includeTime) {
51 counters = mxmlNewElement(captured, "counters"); 51 counters = mxmlNewElement(captured, "counters");
52 } 52 }
53 mxml_node_t *const node = mxmlNewElement(counters, "counter"); 53 mxml_node_t *const node = mxmlNewElement(counters, "counter");
54 mxmlElementSetAttr(node, "title", counter.getTitle()); 54 mxmlElementSetAttrf(node, "key", "0x%x", counter.getKey());
55 mxmlElementSetAttr(node, "name", counter.getName());
56 mxmlElementSetAttrf(node, "key", "0x%08x", counter.getKey());
57 mxmlElementSetAttr(node, "type", counter.getType()); 55 mxmlElementSetAttr(node, "type", counter.getType());
58 mxmlElementSetAttrf(node, "event", "0x%08x", counter.getEvent()); 56 mxmlElementSetAttrf(node, "event", "0x%x", counter.getEvent());
59 if (counter.isPerCPU()) {
60 mxmlElementSetAttr(node, "per_cpu", "yes");
61 }
62 if (counter.getCount() > 0) { 57 if (counter.getCount() > 0) {
63 mxmlElementSetAttrf(node, "count", "%d", counter.getCount()); 58 mxmlElementSetAttrf(node, "count", "%d", counter.getCount());
64 } 59 }
65 if (strlen(counter.getDisplay()) > 0) {
66 mxmlElementSetAttr(node, "display", counter.getDisplay());
67 }
68 if (strlen(counter.getUnits()) > 0) {
69 mxmlElementSetAttr(node, "units", counter.getUnits());
70 }
71 if (counter.getModifier() != 1) {
72 mxmlElementSetAttrf(node, "modifier", "%d", counter.getModifier());
73 }
74 if (counter.isAverageSelection()) {
75 mxmlElementSetAttr(node, "average_selection", "yes");
76 }
77 mxmlElementSetAttr(node, "description", counter.getDescription());
78 } 60 }
79 } 61 }
80 62
diff --git a/daemon/Child.cpp b/daemon/Child.cpp
index c784847..286c7e7 100644
--- a/daemon/Child.cpp
+++ b/daemon/Child.cpp
@@ -100,14 +100,15 @@ static void* durationThread(void* pVoid) {
100} 100}
101 101
102static void* stopThread(void* pVoid) { 102static void* stopThread(void* pVoid) {
103 int length;
104 char type;
105 OlySocket* socket = child->socket; 103 OlySocket* socket = child->socket;
106 104
107 prctl(PR_SET_NAME, (unsigned long)&"gatord-stopper", 0, 0, 0); 105 prctl(PR_SET_NAME, (unsigned long)&"gatord-stopper", 0, 0, 0);
108 while (gSessionData->mSessionIsActive) { 106 while (gSessionData->mSessionIsActive) {
109 // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected 107 // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected
110 const int result = socket->receiveNBytes(&type, sizeof(type)); 108 unsigned char header[5];
109 const int result = socket->receiveNBytes((char*)&header, sizeof(header));
110 const char type = header[0];
111 const int length = (header[1] << 0) | (header[2] << 8) | (header[3] << 16) | (header[4] << 24);
111 if (result == -1) { 112 if (result == -1) {
112 child->endSession(); 113 child->endSession();
113 } else if (result > 0) { 114 } else if (result > 0) {
@@ -115,10 +116,6 @@ static void* stopThread(void* pVoid) {
115 logg->logMessage("INVESTIGATE: Received unknown command type %d", type); 116 logg->logMessage("INVESTIGATE: Received unknown command type %d", type);
116 } else { 117 } else {
117 // verify a length of zero 118 // verify a length of zero
118 if (socket->receiveNBytes((char*)&length, sizeof(length)) < 0) {
119 break;
120 }
121
122 if (length == 0) { 119 if (length == 0) {
123 if (type == COMMAND_APC_STOP) { 120 if (type == COMMAND_APC_STOP) {
124 logg->logMessage("Stop command received."); 121 logg->logMessage("Stop command received.");
diff --git a/daemon/ConfigurationXML.cpp b/daemon/ConfigurationXML.cpp
index 9d51f26..fb00202 100644
--- a/daemon/ConfigurationXML.cpp
+++ b/daemon/ConfigurationXML.cpp
@@ -15,19 +15,10 @@
15#include "OlyUtility.h" 15#include "OlyUtility.h"
16#include "SessionData.h" 16#include "SessionData.h"
17 17
18static const char* ATTR_COUNTER = "counter"; 18static const char* ATTR_COUNTER = "counter";
19static const char* ATTR_REVISION = "revision"; 19static const char* ATTR_REVISION = "revision";
20static const char* ATTR_TITLE = "title"; 20static const char* ATTR_EVENT = "event";
21static const char* ATTR_NAME = "name"; 21static const char* ATTR_COUNT = "count";
22static const char* ATTR_EVENT = "event";
23static const char* ATTR_COUNT = "count";
24static const char* ATTR_PER_CPU = "per_cpu";
25static const char* ATTR_DESCRIPTION = "description";
26static const char* ATTR_EBS = "supports_event_based_sampling";
27static const char* ATTR_DISPLAY = "display";
28static const char* ATTR_UNITS = "units";
29static const char* ATTR_MODIFIER = "modifier";
30static const char* ATTR_AVERAGE_SELECTION = "average_selection";
31 22
32ConfigurationXML::ConfigurationXML() { 23ConfigurationXML::ConfigurationXML() {
33 const char * configuration_xml; 24 const char * configuration_xml;
@@ -87,7 +78,7 @@ int ConfigurationXML::parse(const char* configurationXML) {
87 int ret; 78 int ret;
88 79
89 // clear counter overflow 80 // clear counter overflow
90 gSessionData->mCounterOverflow = false; 81 gSessionData->mCounterOverflow = 0;
91 mIndex = 0; 82 mIndex = 0;
92 83
93 // disable all counters prior to parsing the configuration xml 84 // disable all counters prior to parsing the configuration xml
@@ -123,7 +114,7 @@ void ConfigurationXML::validate(void) {
123 const Counter & counter = gSessionData->mCounters[i]; 114 const Counter & counter = gSessionData->mCounters[i];
124 if (counter.isEnabled()) { 115 if (counter.isEnabled()) {
125 if (strcmp(counter.getType(), "") == 0) { 116 if (strcmp(counter.getType(), "") == 0) {
126 logg->logError(__FILE__, __LINE__, "Invalid required attribute in configuration.xml:\n counter=\"%s\"\n title=\"%s\"\n name=\"%s\"\n event=%d\n", counter.getType(), counter.getTitle(), counter.getName(), counter.getEvent()); 117 logg->logError(__FILE__, __LINE__, "Invalid required attribute in configuration.xml:\n counter=\"%s\"\n event=%d\n", counter.getType(), counter.getEvent());
127 handleException(); 118 handleException();
128 } 119 }
129 120
@@ -142,7 +133,7 @@ void ConfigurationXML::validate(void) {
142 } 133 }
143} 134}
144 135
145#define CONFIGURATION_REVISION 2 136#define CONFIGURATION_REVISION 3
146int ConfigurationXML::configurationsTag(mxml_node_t *node) { 137int ConfigurationXML::configurationsTag(mxml_node_t *node) {
147 const char* revision_string; 138 const char* revision_string;
148 139
@@ -156,13 +147,17 @@ int ConfigurationXML::configurationsTag(mxml_node_t *node) {
156 return 1; // revision issue 147 return 1; // revision issue
157 } 148 }
158 149
150 // A revision >= CONFIGURATION_REVISION is okay
151 // Greater than can occur when Streamline is newer than gator
152
159 return 0; 153 return 0;
160} 154}
161 155
162void ConfigurationXML::configurationTag(mxml_node_t *node) { 156void ConfigurationXML::configurationTag(mxml_node_t *node) {
163 // handle all other performance counters 157 // handle all other performance counters
164 if (mIndex >= MAX_PERFORMANCE_COUNTERS) { 158 if (mIndex >= MAX_PERFORMANCE_COUNTERS) {
165 gSessionData->mCounterOverflow = true; 159 mIndex++;
160 gSessionData->mCounterOverflow = mIndex;
166 return; 161 return;
167 } 162 }
168 163
@@ -170,24 +165,15 @@ void ConfigurationXML::configurationTag(mxml_node_t *node) {
170 Counter & counter = gSessionData->mCounters[mIndex]; 165 Counter & counter = gSessionData->mCounters[mIndex];
171 counter.clear(); 166 counter.clear();
172 if (mxmlElementGetAttr(node, ATTR_COUNTER)) counter.setType(mxmlElementGetAttr(node, ATTR_COUNTER)); 167 if (mxmlElementGetAttr(node, ATTR_COUNTER)) counter.setType(mxmlElementGetAttr(node, ATTR_COUNTER));
173 if (mxmlElementGetAttr(node, ATTR_TITLE)) counter.setTitle(mxmlElementGetAttr(node, ATTR_TITLE));
174 if (mxmlElementGetAttr(node, ATTR_NAME)) counter.setName(mxmlElementGetAttr(node, ATTR_NAME));
175 if (mxmlElementGetAttr(node, ATTR_DESCRIPTION)) counter.setDescription(mxmlElementGetAttr(node, ATTR_DESCRIPTION));
176 if (mxmlElementGetAttr(node, ATTR_EVENT)) counter.setEvent(strtol(mxmlElementGetAttr(node, ATTR_EVENT), NULL, 16)); 168 if (mxmlElementGetAttr(node, ATTR_EVENT)) counter.setEvent(strtol(mxmlElementGetAttr(node, ATTR_EVENT), NULL, 16));
177 if (mxmlElementGetAttr(node, ATTR_COUNT)) counter.setCount(strtol(mxmlElementGetAttr(node, ATTR_COUNT), NULL, 10)); 169 if (mxmlElementGetAttr(node, ATTR_COUNT)) counter.setCount(strtol(mxmlElementGetAttr(node, ATTR_COUNT), NULL, 10));
178 if (mxmlElementGetAttr(node, ATTR_PER_CPU)) counter.setPerCPU(util->stringToBool(mxmlElementGetAttr(node, ATTR_PER_CPU), false));
179 if (mxmlElementGetAttr(node, ATTR_EBS)) counter.setEBSCapable(util->stringToBool(mxmlElementGetAttr(node, ATTR_EBS), false));
180 if (mxmlElementGetAttr(node, ATTR_DISPLAY)) counter.setDisplay(mxmlElementGetAttr(node, ATTR_DISPLAY));
181 if (mxmlElementGetAttr(node, ATTR_UNITS)) counter.setUnits(mxmlElementGetAttr(node, ATTR_UNITS));
182 if (mxmlElementGetAttr(node, ATTR_MODIFIER)) counter.setModifier(strtol(mxmlElementGetAttr(node, ATTR_MODIFIER), NULL, 10));
183 if (mxmlElementGetAttr(node, ATTR_AVERAGE_SELECTION)) counter.setAverageSelection(util->stringToBool(mxmlElementGetAttr(node, ATTR_AVERAGE_SELECTION), false));
184 counter.setEnabled(true); 170 counter.setEnabled(true);
185 171
186 // Associate a driver with each counter 172 // Associate a driver with each counter
187 for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) { 173 for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
188 if (driver->claimCounter(counter)) { 174 if (driver->claimCounter(counter)) {
189 if (counter.getDriver() != NULL) { 175 if (counter.getDriver() != NULL) {
190 logg->logError(__FILE__, __LINE__, "More than one driver has claimed %s: %s", counter.getTitle(), counter.getName()); 176 logg->logError(__FILE__, __LINE__, "More than one driver has claimed %s:%i", counter.getType(), counter.getEvent());
191 handleException(); 177 handleException();
192 } 178 }
193 counter.setDriver(driver); 179 counter.setDriver(driver);
@@ -196,12 +182,14 @@ void ConfigurationXML::configurationTag(mxml_node_t *node) {
196 182
197 // If no driver is associated with the counter, disable it 183 // If no driver is associated with the counter, disable it
198 if (counter.getDriver() == NULL) { 184 if (counter.getDriver() == NULL) {
199 logg->logMessage("No driver has claimed %s (%s: %s)", counter.getType(), counter.getTitle(), counter.getName()); 185 logg->logMessage("No driver has claimed %s:%i", counter.getType(), counter.getEvent());
200 counter.setEnabled(false); 186 counter.setEnabled(false);
201 } 187 }
202 188
203 // update counter index 189 if (counter.isEnabled()) {
204 mIndex++; 190 // update counter index
191 mIndex++;
192 }
205} 193}
206 194
207void ConfigurationXML::getDefaultConfigurationXml(const char * & xml, unsigned int & len) { 195void ConfigurationXML::getDefaultConfigurationXml(const char * & xml, unsigned int & len) {
diff --git a/daemon/Counter.h b/daemon/Counter.h
index 041020b..231a85d 100644
--- a/daemon/Counter.h
+++ b/daemon/Counter.h
@@ -24,52 +24,25 @@ public:
24 24
25 void clear () { 25 void clear () {
26 mType[0] = '\0'; 26 mType[0] = '\0';
27 mTitle[0] = '\0';
28 mName[0] = '\0';
29 mDescription[0] = '\0';
30 mDisplay[0] = '\0';
31 mUnits[0] = '\0';
32 mModifier = 1;
33 mEnabled = false; 27 mEnabled = false;
34 mEvent = 0; 28 mEvent = 0;
35 mCount = 0; 29 mCount = 0;
36 mKey = 0; 30 mKey = 0;
37 mPerCPU = false;
38 mEBSCapable = false;
39 mAverageSelection = false;
40 mDriver = NULL; 31 mDriver = NULL;
41 } 32 }
42 33
43 void setType(const char *const type) { strncpy(mType, type, sizeof(mType)); mType[sizeof(mType) - 1] = '\0'; } 34 void setType(const char *const type) { strncpy(mType, type, sizeof(mType)); mType[sizeof(mType) - 1] = '\0'; }
44 void setTitle(const char *const title) { strncpy(mTitle, title, sizeof(mTitle)); mTitle[sizeof(mTitle) - 1] = '\0'; }
45 void setName(const char *const name) { strncpy(mName, name, sizeof(mName)); mName[sizeof(mName) - 1] = '\0'; }
46 void setDescription(const char *const description) { strncpy(mDescription, description, sizeof(mDescription)); mDescription[sizeof(mDescription) - 1] = '\0'; }
47 void setDisplay(const char *const display) { strncpy(mDisplay, display, sizeof(mDisplay)); mDisplay[sizeof(mDisplay) - 1] = '\0'; }
48 void setUnits(const char *const units) { strncpy(mUnits, units, sizeof(mUnits)); mUnits[sizeof(mUnits) - 1] = '\0'; }
49 void setModifier(const int modifier) { mModifier = modifier; }
50 void setEnabled(const bool enabled) { mEnabled = enabled; } 35 void setEnabled(const bool enabled) { mEnabled = enabled; }
51 void setEvent(const int event) { mEvent = event; } 36 void setEvent(const int event) { mEvent = event; }
52 void setCount(const int count) { mCount = count; } 37 void setCount(const int count) { mCount = count; }
53 void setKey(const int key) { mKey = key; } 38 void setKey(const int key) { mKey = key; }
54 void setPerCPU(const bool perCPU) { mPerCPU = perCPU; }
55 void setEBSCapable(const bool ebsCapable) { mEBSCapable = ebsCapable; }
56 void setAverageSelection(const bool averageSelection) { mAverageSelection = averageSelection; }
57 void setDriver(Driver *const driver) { mDriver = driver; } 39 void setDriver(Driver *const driver) { mDriver = driver; }
58 40
59 const char *getType() const { return mType;} 41 const char *getType() const { return mType;}
60 const char *getTitle() const { return mTitle; }
61 const char *getName() const { return mName; }
62 const char *getDescription() const { return mDescription; }
63 const char *getDisplay() const { return mDisplay; }
64 const char *getUnits() const { return mUnits; }
65 int getModifier() const { return mModifier; }
66 bool isEnabled() const { return mEnabled; } 42 bool isEnabled() const { return mEnabled; }
67 int getEvent() const { return mEvent; } 43 int getEvent() const { return mEvent; }
68 int getCount() const { return mCount; } 44 int getCount() const { return mCount; }
69 int getKey() const { return mKey; } 45 int getKey() const { return mKey; }
70 bool isPerCPU() const { return mPerCPU; }
71 bool isEBSCapable() const { return mEBSCapable; }
72 bool isAverageSelection() const { return mAverageSelection; }
73 Driver *getDriver() const { return mDriver; } 46 Driver *getDriver() const { return mDriver; }
74 47
75private: 48private:
@@ -78,19 +51,10 @@ private:
78 Counter & operator=(const Counter &); 51 Counter & operator=(const Counter &);
79 52
80 char mType[MAX_STRING_LEN]; 53 char mType[MAX_STRING_LEN];
81 char mTitle[MAX_STRING_LEN];
82 char mName[MAX_STRING_LEN];
83 char mDescription[MAX_DESCRIPTION_LEN];
84 char mDisplay[MAX_STRING_LEN];
85 char mUnits[MAX_STRING_LEN];
86 int mModifier;
87 bool mEnabled; 54 bool mEnabled;
88 int mEvent; 55 int mEvent;
89 int mCount; 56 int mCount;
90 int mKey; 57 int mKey;
91 bool mPerCPU;
92 bool mEBSCapable;
93 bool mAverageSelection;
94 Driver *mDriver; 58 Driver *mDriver;
95}; 59};
96 60
diff --git a/daemon/EventsXML.cpp b/daemon/EventsXML.cpp
new file mode 100644
index 0000000..2a80482
--- /dev/null
+++ b/daemon/EventsXML.cpp
@@ -0,0 +1,70 @@
1/**
2 * Copyright (C) ARM Limited 2013. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "EventsXML.h"
10
11#include "CapturedXML.h"
12#include "Logging.h"
13#include "OlyUtility.h"
14#include "SessionData.h"
15
16char* EventsXML::getXML() {
17#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len
18 char path[PATH_MAX];
19 mxml_node_t *xml;
20 FILE *fl;
21
22 // Avoid unused variable warning
23 (void)events_xml_len;
24
25 // Load the provided or default events xml
26 if (gSessionData->mEventsXMLPath) {
27 strncpy(path, gSessionData->mEventsXMLPath, PATH_MAX);
28 } else {
29 util->getApplicationFullPath(path, PATH_MAX);
30 strncat(path, "events.xml", PATH_MAX - strlen(path) - 1);
31 }
32 fl = fopen(path, "r");
33 if (fl) {
34 xml = mxmlLoadFile(NULL, fl, MXML_NO_CALLBACK);
35 fclose(fl);
36 } else {
37 logg->logMessage("Unable to locate events.xml, using default");
38 xml = mxmlLoadString(NULL, (char *)events_xml, MXML_NO_CALLBACK);
39 }
40
41 // Add dynamic events from the drivers
42 mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND);
43 if (!events) {
44 logg->logMessage("Unable to find <events> node in the events.xml");
45 handleException();
46 }
47 for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
48 driver->writeEvents(events);
49 }
50
51 char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
52 mxmlDelete(xml);
53
54 return string;
55}
56
57void EventsXML::write(const char* path) {
58 char file[PATH_MAX];
59
60 // Set full path
61 snprintf(file, PATH_MAX, "%s/events.xml", path);
62
63 char* buf = getXML();
64 if (util->writeToDisk(file, buf) < 0) {
65 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
66 handleException();
67 }
68
69 free(buf);
70}
diff --git a/daemon/EventsXML.h b/daemon/EventsXML.h
new file mode 100644
index 0000000..8e693ef
--- /dev/null
+++ b/daemon/EventsXML.h
@@ -0,0 +1,18 @@
1/**
2 * Copyright (C) ARM Limited 2013. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef EVENTS_XML
10#define EVENTS_XML
11
12class EventsXML {
13public:
14 char* getXML();
15 void write(const char* path);
16};
17
18#endif // EVENTS_XML
diff --git a/daemon/Fifo.cpp b/daemon/Fifo.cpp
index f0b0178..250a4d0 100644
--- a/daemon/Fifo.cpp
+++ b/daemon/Fifo.cpp
@@ -6,122 +6,125 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <stdlib.h>
10#include <string.h>
11#include <unistd.h>
12#include "Fifo.h" 9#include "Fifo.h"
10
11#include <stdlib.h>
12#ifdef WIN32
13#define valloc malloc
14#endif
15
13#include "Logging.h" 16#include "Logging.h"
14 17
15// bufferSize is the amount of data to be filled 18// bufferSize is the amount of data to be filled
16// singleBufferSize is the maximum size that may be filled during a single write 19// singleBufferSize is the maximum size that may be filled during a single write
17// (bufferSize + singleBufferSize) will be allocated 20// (bufferSize + singleBufferSize) will be allocated
18Fifo::Fifo(int singleBufferSize, int bufferSize, sem_t* readerSem) { 21Fifo::Fifo(int singleBufferSize, int bufferSize, sem_t* readerSem) {
19 mWrite = mRead = mReadCommit = mRaggedEnd = 0; 22 mWrite = mRead = mReadCommit = mRaggedEnd = 0;
20 mWrapThreshold = bufferSize; 23 mWrapThreshold = bufferSize;
21 mSingleBufferSize = singleBufferSize; 24 mSingleBufferSize = singleBufferSize;
22 mReaderSem = readerSem; 25 mReaderSem = readerSem;
23 mBuffer = (char*)valloc(bufferSize + singleBufferSize); 26 mBuffer = (char*)valloc(bufferSize + singleBufferSize);
24 mEnd = false; 27 mEnd = false;
25 28
26 if (mBuffer == NULL) { 29 if (mBuffer == NULL) {
27 logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize); 30 logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize);
28 handleException(); 31 handleException();
29 } 32 }
30 33
31 if (sem_init(&mWaitForSpaceSem, 0, 0)) { 34 if (sem_init(&mWaitForSpaceSem, 0, 0)) {
32 logg->logError(__FILE__, __LINE__, "sem_init() failed"); 35 logg->logError(__FILE__, __LINE__, "sem_init() failed");
33 handleException(); 36 handleException();
34 } 37 }
35} 38}
36 39
37Fifo::~Fifo() { 40Fifo::~Fifo() {
38 free(mBuffer); 41 free(mBuffer);
39 sem_destroy(&mWaitForSpaceSem); 42 sem_destroy(&mWaitForSpaceSem);
40} 43}
41 44
42int Fifo::numBytesFilled() const { 45int Fifo::numBytesFilled() const {
43 return mWrite - mRead + mRaggedEnd; 46 return mWrite - mRead + mRaggedEnd;
44} 47}
45 48
46char* Fifo::start() const { 49char* Fifo::start() const {
47 return mBuffer; 50 return mBuffer;
48} 51}
49 52
50bool Fifo::isEmpty() const { 53bool Fifo::isEmpty() const {
51 return mRead == mWrite && mRaggedEnd == 0; 54 return mRead == mWrite && mRaggedEnd == 0;
52} 55}
53 56
54bool Fifo::isFull() const { 57bool Fifo::isFull() const {
55 return willFill(0); 58 return willFill(0);
56} 59}
57 60
58// Determines if the buffer will fill assuming 'additional' bytes will be added to the buffer 61// Determines if the buffer will fill assuming 'additional' bytes will be added to the buffer
59// 'full' means there is less than singleBufferSize bytes available contiguously; it does not mean there are zero bytes available 62// 'full' means there is less than singleBufferSize bytes available contiguously; it does not mean there are zero bytes available
60bool Fifo::willFill(int additional) const { 63bool Fifo::willFill(int additional) const {
61 if (mWrite > mRead) { 64 if (mWrite > mRead) {
62 if (numBytesFilled() + additional < mWrapThreshold) { 65 if (numBytesFilled() + additional < mWrapThreshold) {
63 return false; 66 return false;
64 } 67 }
65 } else { 68 } else {
66 if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) { 69 if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) {
67 return false; 70 return false;
68 } 71 }
69 } 72 }
70 return true; 73 return true;
71} 74}
72 75
73// This function will stall until contiguous singleBufferSize bytes are available 76// This function will stall until contiguous singleBufferSize bytes are available
74char* Fifo::write(int length) { 77char* Fifo::write(int length) {
75 if (length <= 0) { 78 if (length <= 0) {
76 length = 0; 79 length = 0;
77 mEnd = true; 80 mEnd = true;
78 } 81 }
79 82
80 // update the write pointer 83 // update the write pointer
81 mWrite += length; 84 mWrite += length;
82 85
83 // handle the wrap-around 86 // handle the wrap-around
84 if (mWrite >= mWrapThreshold) { 87 if (mWrite >= mWrapThreshold) {
85 mRaggedEnd = mWrite; 88 mRaggedEnd = mWrite;
86 mWrite = 0; 89 mWrite = 0;
87 } 90 }
88 91
89 // send a notification that data is ready 92 // send a notification that data is ready
90 sem_post(mReaderSem); 93 sem_post(mReaderSem);
91 94
92 // wait for space 95 // wait for space
93 while (isFull()) { 96 while (isFull()) {
94 sem_wait(&mWaitForSpaceSem); 97 sem_wait(&mWaitForSpaceSem);
95 } 98 }
96 99
97 return &mBuffer[mWrite]; 100 return &mBuffer[mWrite];
98} 101}
99 102
100void Fifo::release() { 103void Fifo::release() {
101 // update the read pointer now that the data has been handled 104 // update the read pointer now that the data has been handled
102 mRead = mReadCommit; 105 mRead = mReadCommit;
103 106
104 // handle the wrap-around 107 // handle the wrap-around
105 if (mRead >= mWrapThreshold) { 108 if (mRead >= mWrapThreshold) {
106 mRaggedEnd = mRead = mReadCommit = 0; 109 mRaggedEnd = mRead = mReadCommit = 0;
107 } 110 }
108 111
109 // send a notification that data is free (space is available) 112 // send a notification that data is free (space is available)
110 sem_post(&mWaitForSpaceSem); 113 sem_post(&mWaitForSpaceSem);
111} 114}
112 115
113// This function will return null if no data is available 116// This function will return null if no data is available
114char* Fifo::read(int *const length) { 117char* Fifo::read(int *const length) {
115 // wait for data 118 // wait for data
116 if (isEmpty() && !mEnd) { 119 if (isEmpty() && !mEnd) {
117 return NULL; 120 return NULL;
118 } 121 }
119 122
120 // obtain the length 123 // obtain the length
121 do { 124 do {
122 mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite; 125 mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite;
123 *length = mReadCommit - mRead; 126 *length = mReadCommit - mRead;
124 } while (*length < 0); // plugs race condition without using semaphores 127 } while (*length < 0); // plugs race condition without using semaphores
125 128
126 return &mBuffer[mRead]; 129 return &mBuffer[mRead];
127} 130}
diff --git a/daemon/Fifo.h b/daemon/Fifo.h
index d46e1af..ada42b9 100644
--- a/daemon/Fifo.h
+++ b/daemon/Fifo.h
@@ -9,27 +9,36 @@
9#ifndef __FIFO_H__ 9#ifndef __FIFO_H__
10#define __FIFO_H__ 10#define __FIFO_H__
11 11
12#ifdef WIN32
13#include <windows.h>
14#define sem_t HANDLE
15#define sem_init(sem, pshared, value) ((*(sem) = CreateSemaphore(NULL, value, INFINITE, NULL)) == NULL)
16#define sem_wait(sem) WaitForSingleObject(*(sem), INFINITE)
17#define sem_post(sem) ReleaseSemaphore(*(sem), 1, NULL)
18#define sem_destroy(sem) CloseHandle(*(sem))
19#else
12#include <semaphore.h> 20#include <semaphore.h>
21#endif
13 22
14class Fifo { 23class Fifo {
15public: 24public:
16 Fifo(int singleBufferSize, int totalBufferSize, sem_t* readerSem); 25 Fifo(int singleBufferSize, int totalBufferSize, sem_t* readerSem);
17 ~Fifo(); 26 ~Fifo();
18 int numBytesFilled() const; 27 int numBytesFilled() const;
19 bool isEmpty() const; 28 bool isEmpty() const;
20 bool isFull() const; 29 bool isFull() const;
21 bool willFill(int additional) const; 30 bool willFill(int additional) const;
22 char* start() const; 31 char* start() const;
23 char* write(int length); 32 char* write(int length);
24 void release(); 33 void release();
25 char* read(int *const length); 34 char* read(int *const length);
26 35
27private: 36private:
28 int mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold; 37 int mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold;
29 sem_t mWaitForSpaceSem; 38 sem_t mWaitForSpaceSem;
30 sem_t* mReaderSem; 39 sem_t* mReaderSem;
31 char* mBuffer; 40 char* mBuffer;
32 bool mEnd; 41 bool mEnd;
33}; 42};
34 43
35#endif //__FIFO_H__ 44#endif //__FIFO_H__
diff --git a/daemon/Hwmon.cpp b/daemon/Hwmon.cpp
index 9603411..9475215 100644
--- a/daemon/Hwmon.cpp
+++ b/daemon/Hwmon.cpp
@@ -26,20 +26,30 @@ public:
26 const char *getName() const { return name; } 26 const char *getName() const { return name; }
27 const char *getLabel() const { return label; } 27 const char *getLabel() const { return label; }
28 const char *getTitle() const { return title; } 28 const char *getTitle() const { return title; }
29 bool isDuplicate() const { return duplicate; }
29 const char *getDisplay() const { return display; } 30 const char *getDisplay() const { return display; }
30 const char *getUnit() const { return unit; } 31 const char *getUnit() const { return unit; }
31 int getModifier() const { return modifier; } 32 int getModifier() const { return modifier; }
32 33
33 void setEnabled(const bool enabled) { this->enabled = enabled; } 34 void setEnabled(const bool enabled) {
35 this->enabled = enabled;
36 // canRead will clear enabled if the counter is not readable
37 canRead();
38 }
34 39
35 double read(); 40 double read();
41 bool canRead();
36 42
37private: 43private:
38 void init(const sensors_chip_name *chip, const sensors_feature *feature); 44 void init(const sensors_chip_name *chip, const sensors_feature *feature);
39 45
40 HwmonCounter *const next; 46 HwmonCounter *const next;
41 const int key; 47 const int key;
42 bool enabled; 48 int polled : 1,
49 readable : 1,
50 enabled : 1,
51 monotonic: 1,
52 duplicate : 1;
43 53
44 const sensors_chip_name *chip; 54 const sensors_chip_name *chip;
45 const sensors_feature *feature; 55 const sensors_feature *feature;
@@ -50,13 +60,12 @@ private:
50 const char *display; 60 const char *display;
51 const char *unit; 61 const char *unit;
52 int modifier; 62 int modifier;
53 bool monotonic;
54 double previous_value; 63 double previous_value;
55 64
56 sensors_subfeature_type input; 65 sensors_subfeature_type input;
57}; 66};
58 67
59HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name *chip, const sensors_feature *feature) : next(next), key(key), enabled(false), chip(chip), feature(feature) { 68HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name *chip, const sensors_feature *feature) : next(next), key(key), polled(false), readable(false), enabled(false), duplicate(false), chip(chip), feature(feature) {
60 69
61 int len = sensors_snprintf_chip_name(NULL, 0, chip) + 1; 70 int len = sensors_snprintf_chip_name(NULL, 0, chip) + 1;
62 char *chip_name = new char[len]; 71 char *chip_name = new char[len];
@@ -131,6 +140,14 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name
131 logg->logError(__FILE__, __LINE__, "Unsupported hwmon feature %i", feature->type); 140 logg->logError(__FILE__, __LINE__, "Unsupported hwmon feature %i", feature->type);
132 handleException(); 141 handleException();
133 } 142 }
143
144 for (HwmonCounter * counter = next; counter != NULL; counter = counter->getNext()) {
145 if (strcmp(label, counter->getLabel()) == 0 && strcmp(title, counter->getTitle()) == 0) {
146 duplicate = true;
147 counter->duplicate = true;
148 break;
149 }
150 }
134} 151}
135 152
136HwmonCounter::~HwmonCounter() { 153HwmonCounter::~HwmonCounter() {
@@ -143,6 +160,7 @@ double HwmonCounter::read() {
143 double result; 160 double result;
144 const sensors_subfeature *subfeature; 161 const sensors_subfeature *subfeature;
145 162
163 // Keep in sync with canRead
146 subfeature = sensors_get_subfeature(chip, feature, input); 164 subfeature = sensors_get_subfeature(chip, feature, input);
147 if (!subfeature) { 165 if (!subfeature) {
148 logg->logError(__FILE__, __LINE__, "No input value for hwmon sensor %s", label); 166 logg->logError(__FILE__, __LINE__, "No input value for hwmon sensor %s", label);
@@ -160,6 +178,27 @@ double HwmonCounter::read() {
160 return result; 178 return result;
161} 179}
162 180
181bool HwmonCounter::canRead() {
182 if (!polled) {
183 double value;
184 const sensors_subfeature *subfeature;
185 bool result = true;
186
187 subfeature = sensors_get_subfeature(chip, feature, input);
188 if (!subfeature) {
189 result = false;
190 } else {
191 result = sensors_get_value(chip, subfeature->number, &value) == 0;
192 }
193
194 polled = true;
195 readable = result;
196 }
197
198 enabled &= readable;
199
200 return readable;
201}
163 202
164Hwmon::Hwmon() : counters(NULL) { 203Hwmon::Hwmon() : counters(NULL) {
165 int err = sensors_init(NULL); 204 int err = sensors_init(NULL);
@@ -191,7 +230,7 @@ Hwmon::~Hwmon() {
191 230
192HwmonCounter *Hwmon::findCounter(const Counter &counter) const { 231HwmonCounter *Hwmon::findCounter(const Counter &counter) const {
193 for (HwmonCounter * hwmonCounter = counters; hwmonCounter != NULL; hwmonCounter = hwmonCounter->getNext()) { 232 for (HwmonCounter * hwmonCounter = counters; hwmonCounter != NULL; hwmonCounter = hwmonCounter->getNext()) {
194 if (strcmp(hwmonCounter->getName(), counter.getType()) == 0) { 233 if (hwmonCounter->canRead() && strcmp(hwmonCounter->getName(), counter.getType()) == 0) {
195 return hwmonCounter; 234 return hwmonCounter;
196 } 235 }
197 } 236 }
@@ -230,6 +269,9 @@ void Hwmon::setupCounter(Counter &counter) {
230 269
231void Hwmon::writeCounters(mxml_node_t *root) const { 270void Hwmon::writeCounters(mxml_node_t *root) const {
232 for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) { 271 for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
272 if (!counter->canRead()) {
273 continue;
274 }
233 mxml_node_t *node = mxmlNewElement(root, "counter"); 275 mxml_node_t *node = mxmlNewElement(root, "counter");
234 mxmlElementSetAttr(node, "name", counter->getName()); 276 mxmlElementSetAttr(node, "name", counter->getName());
235 } 277 }
@@ -241,10 +283,17 @@ void Hwmon::writeEvents(mxml_node_t *root) const {
241 283
242 char buf[1024]; 284 char buf[1024];
243 for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) { 285 for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
286 if (!counter->canRead()) {
287 continue;
288 }
244 mxml_node_t *node = mxmlNewElement(root, "event"); 289 mxml_node_t *node = mxmlNewElement(root, "event");
245 mxmlElementSetAttr(node, "counter", counter->getName()); 290 mxmlElementSetAttr(node, "counter", counter->getName());
246 mxmlElementSetAttr(node, "title", counter->getTitle()); 291 mxmlElementSetAttr(node, "title", counter->getTitle());
247 mxmlElementSetAttr(node, "name", counter->getLabel()); 292 if (counter->isDuplicate()) {
293 mxmlElementSetAttrf(node, "name", "%s (0x%x)", counter->getLabel(), counter->getKey());
294 } else {
295 mxmlElementSetAttr(node, "name", counter->getLabel());
296 }
248 mxmlElementSetAttr(node, "display", counter->getDisplay()); 297 mxmlElementSetAttr(node, "display", counter->getDisplay());
249 mxmlElementSetAttr(node, "units", counter->getUnit()); 298 mxmlElementSetAttr(node, "units", counter->getUnit());
250 if (counter->getModifier() != 1) { 299 if (counter->getModifier() != 1) {
diff --git a/daemon/KMod.cpp b/daemon/KMod.cpp
index 5f12046..04f3330 100644
--- a/daemon/KMod.cpp
+++ b/daemon/KMod.cpp
@@ -58,25 +58,23 @@ void KMod::setupCounter(Counter &counter) {
58 } 58 }
59 59
60 snprintf(text, sizeof(text), "%s/key", base); 60 snprintf(text, sizeof(text), "%s/key", base);
61 int key; 61 int key = 0;
62 Collector::readIntDriver(text, &key); 62 Collector::readIntDriver(text, &key);
63 counter.setKey(key); 63 counter.setKey(key);
64 64
65 snprintf(text, sizeof(text), "%s/event", base); 65 snprintf(text, sizeof(text), "%s/event", base);
66 Collector::writeDriver(text, counter.getEvent()); 66 Collector::writeDriver(text, counter.getEvent());
67 if (counter.isEBSCapable()) { 67 snprintf(text, sizeof(text), "%s/count", base);
68 snprintf(text, sizeof(text), "%s/count", base); 68 if (access(text, F_OK) == 0) {
69 if (access(text, F_OK) == 0) { 69 int count = counter.getCount();
70 int count = counter.getCount(); 70 if (Collector::writeReadDriver(text, &count) && counter.getCount() > 0) {
71 if (Collector::writeReadDriver(text, &count) && counter.getCount() > 0) { 71 logg->logError(__FILE__, __LINE__, "Cannot enable EBS for %s:%i with a count of %d\n", counter.getType(), counter.getEvent(), counter.getCount());
72 logg->logError(__FILE__, __LINE__, "Cannot enable EBS for %s:%s with a count of %d\n", counter.getTitle(), counter.getName(), counter.getCount());
73 handleException();
74 }
75 counter.setCount(count);
76 } else if (counter.getCount() > 0) {
77 logg->logError(__FILE__, __LINE__, "Event Based Sampling is only supported with kernel versions 3.0.0 and higher with CONFIG_PERF_EVENTS=y, and CONFIG_HW_PERF_EVENTS=y\n");
78 handleException(); 72 handleException();
79 } 73 }
74 counter.setCount(count);
75 } else if (counter.getCount() > 0) {
76 logg->logError(__FILE__, __LINE__, "Event Based Sampling is only supported with kernel versions 3.0.0 and higher with CONFIG_PERF_EVENTS=y, and CONFIG_HW_PERF_EVENTS=y\n");
77 handleException();
80 } 78 }
81} 79}
82 80
diff --git a/daemon/LocalCapture.cpp b/daemon/LocalCapture.cpp
index baa3dd9..3235a34 100644
--- a/daemon/LocalCapture.cpp
+++ b/daemon/LocalCapture.cpp
@@ -16,6 +16,7 @@
16#include "SessionData.h" 16#include "SessionData.h"
17#include "Logging.h" 17#include "Logging.h"
18#include "OlyUtility.h" 18#include "OlyUtility.h"
19#include "EventsXML.h"
19 20
20LocalCapture::LocalCapture() {} 21LocalCapture::LocalCapture() {}
21 22
@@ -40,6 +41,10 @@ void LocalCapture::write(char* string) {
40 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file); 41 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
41 handleException(); 42 handleException();
42 } 43 }
44
45 // Write events XML
46 EventsXML eventsXML;
47 eventsXML.write(gSessionData->mAPCDir);
43} 48}
44 49
45char* LocalCapture::createUniqueDirectory(const char* initialPath, const char* ending) { 50char* LocalCapture::createUniqueDirectory(const char* initialPath, const char* ending) {
diff --git a/daemon/OlySocket.cpp b/daemon/OlySocket.cpp
index 499f68c..132510d 100644
--- a/daemon/OlySocket.cpp
+++ b/daemon/OlySocket.cpp
@@ -6,6 +6,8 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include "OlySocket.h"
10
9#include <stdio.h> 11#include <stdio.h>
10#ifdef WIN32 12#ifdef WIN32
11#include <Winsock2.h> 13#include <Winsock2.h>
@@ -15,7 +17,7 @@
15#include <unistd.h> 17#include <unistd.h>
16#include <netdb.h> 18#include <netdb.h>
17#endif 19#endif
18#include "OlySocket.h" 20
19#include "Logging.h" 21#include "Logging.h"
20 22
21#ifdef WIN32 23#ifdef WIN32
diff --git a/daemon/OlyUtility.cpp b/daemon/OlyUtility.cpp
index 2f85131..b29a1e9 100644
--- a/daemon/OlyUtility.cpp
+++ b/daemon/OlyUtility.cpp
@@ -6,6 +6,8 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include "OlyUtility.h"
10
9#include <stdio.h> 11#include <stdio.h>
10#include <stdlib.h> 12#include <stdlib.h>
11#include <string.h> 13#include <string.h>
@@ -19,8 +21,6 @@
19#include <mach-o/dyld.h> 21#include <mach-o/dyld.h>
20#endif 22#endif
21 23
22#include "OlyUtility.h"
23
24OlyUtility* util = NULL; 24OlyUtility* util = NULL;
25 25
26bool OlyUtility::stringToBool(const char* string, bool defValue) { 26bool OlyUtility::stringToBool(const char* string, bool defValue) {
diff --git a/daemon/OlyUtility.h b/daemon/OlyUtility.h
index 5c68a58..abab0a5 100644
--- a/daemon/OlyUtility.h
+++ b/daemon/OlyUtility.h
@@ -9,6 +9,8 @@
9#ifndef OLY_UTILITY_H 9#ifndef OLY_UTILITY_H
10#define OLY_UTILITY_H 10#define OLY_UTILITY_H
11 11
12#include <stddef.h>
13
12#ifdef WIN32 14#ifdef WIN32
13#define PATH_SEPARATOR '\\' 15#define PATH_SEPARATOR '\\'
14#define CAIMAN_PATH_MAX MAX_PATH 16#define CAIMAN_PATH_MAX MAX_PATH
diff --git a/daemon/SessionData.h b/daemon/SessionData.h
index 5b6899b..22a8af0 100644
--- a/daemon/SessionData.h
+++ b/daemon/SessionData.h
@@ -16,7 +16,7 @@
16 16
17#define MAX_PERFORMANCE_COUNTERS 50 17#define MAX_PERFORMANCE_COUNTERS 50
18 18
19#define PROTOCOL_VERSION 13 19#define PROTOCOL_VERSION 14
20#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions 20#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions
21 21
22struct ImageLinkList { 22struct ImageLinkList {
@@ -57,7 +57,7 @@ public:
57 int mCpuId; 57 int mCpuId;
58 58
59 // PMU Counters 59 // PMU Counters
60 bool mCounterOverflow; 60 int mCounterOverflow;
61 Counter mCounters[MAX_PERFORMANCE_COUNTERS]; 61 Counter mCounters[MAX_PERFORMANCE_COUNTERS];
62 62
63private: 63private:
diff --git a/daemon/StreamlineSetup.cpp b/daemon/StreamlineSetup.cpp
index 88c07a6..e196a7d 100644
--- a/daemon/StreamlineSetup.cpp
+++ b/daemon/StreamlineSetup.cpp
@@ -20,6 +20,7 @@
20#include "StreamlineSetup.h" 20#include "StreamlineSetup.h"
21#include "ConfigurationXML.h" 21#include "ConfigurationXML.h"
22#include "Driver.h" 22#include "Driver.h"
23#include "EventsXML.h"
23 24
24static const char* TAG_SESSION = "session"; 25static const char* TAG_SESSION = "session";
25static const char* TAG_REQUEST = "request"; 26static const char* TAG_REQUEST = "request";
@@ -77,8 +78,8 @@ StreamlineSetup::StreamlineSetup(OlySocket* s) {
77 free(data); 78 free(data);
78 } 79 }
79 80
80 if (gSessionData->mCounterOverflow) { 81 if (gSessionData->mCounterOverflow > 0) {
81 logg->logError(__FILE__, __LINE__, "Exceeded maximum number of %d performance counters", MAX_PERFORMANCE_COUNTERS); 82 logg->logError(__FILE__, __LINE__, "Only %i performance counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
82 handleException(); 83 handleException();
83 } 84 }
84} 85}
@@ -87,12 +88,12 @@ StreamlineSetup::~StreamlineSetup() {
87} 88}
88 89
89char* StreamlineSetup::readCommand(int* command) { 90char* StreamlineSetup::readCommand(int* command) {
90 char type; 91 unsigned char header[5];
91 char* data; 92 char* data;
92 int response, length; 93 int response;
93 94
94 // receive type 95 // receive type and length
95 response = mSocket->receiveNBytes(&type, sizeof(type)); 96 response = mSocket->receiveNBytes((char*)&header, sizeof(header));
96 97
97 // After receiving a single byte, we are no longer waiting on a command 98 // After receiving a single byte, we are no longer waiting on a command
98 gSessionData->mWaitingOnCommand = false; 99 gSessionData->mWaitingOnCommand = false;
@@ -102,12 +103,8 @@ char* StreamlineSetup::readCommand(int* command) {
102 handleException(); 103 handleException();
103 } 104 }
104 105
105 // receive length 106 const char type = header[0];
106 response = mSocket->receiveNBytes((char*)&length, sizeof(length)); 107 const int length = (header[1] << 0) | (header[2] << 8) | (header[3] << 16) | (header[4] << 24);
107 if (response < 0) {
108 logg->logError(__FILE__, __LINE__, "Target error: Unexpected socket disconnect");
109 handleException();
110 }
111 108
112 // add artificial limit 109 // add artificial limit
113 if ((length < 0) || length > 1024 * 1024) { 110 if ((length < 0) || length > 1024 * 1024) {
@@ -198,51 +195,22 @@ void StreamlineSetup::handleDeliver(char* xml) {
198 mxmlDelete(tree); 195 mxmlDelete(tree);
199} 196}
200 197
201void StreamlineSetup::sendData(const char* data, int length, int type) { 198void StreamlineSetup::sendData(const char* data, uint32_t length, char type) {
202 mSocket->send((char*)&type, 1); 199 unsigned char header[5];
203 mSocket->send((char*)&length, sizeof(length)); 200 header[0] = type;
201 header[1] = (length >> 0) & 0xff;
202 header[2] = (length >> 8) & 0xff;
203 header[3] = (length >> 16) & 0xff;
204 header[4] = (length >> 24) & 0xff;
205 mSocket->send((char*)&header, sizeof(header));
204 mSocket->send((char*)data, length); 206 mSocket->send((char*)data, length);
205} 207}
206 208
207void StreamlineSetup::sendEvents() { 209void StreamlineSetup::sendEvents() {
208#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len 210 EventsXML eventsXML;
209 char path[PATH_MAX]; 211 char* string = eventsXML.getXML();
210 mxml_node_t *xml;
211 FILE *fl;
212
213 // Avoid unused variable warning
214 (void)events_xml_len;
215
216 // Load the provided or default events xml
217 if (gSessionData->mEventsXMLPath) {
218 strncpy(path, gSessionData->mEventsXMLPath, PATH_MAX);
219 } else {
220 util->getApplicationFullPath(path, PATH_MAX);
221 strncat(path, "events.xml", PATH_MAX - strlen(path) - 1);
222 }
223 fl = fopen(path, "r");
224 if (fl) {
225 xml = mxmlLoadFile(NULL, fl, MXML_NO_CALLBACK);
226 fclose(fl);
227 } else {
228 logg->logMessage("Unable to locate events.xml, using default");
229 xml = mxmlLoadString(NULL, (char *)events_xml, MXML_NO_CALLBACK);
230 }
231
232 // Add dynamic events from the drivers
233 mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND);
234 if (!events) {
235 logg->logMessage("Unable to find <events> node in the events.xml");
236 handleException();
237 }
238 for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
239 driver->writeEvents(events);
240 }
241
242 char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
243 sendString(string, RESPONSE_XML); 212 sendString(string, RESPONSE_XML);
244 free(string); 213 free(string);
245 mxmlDelete(xml);
246} 214}
247 215
248void StreamlineSetup::sendConfiguration() { 216void StreamlineSetup::sendConfiguration() {
@@ -302,8 +270,8 @@ void StreamlineSetup::writeConfiguration(char* xml) {
302 // Re-populate gSessionData with the configuration, as it has now changed 270 // Re-populate gSessionData with the configuration, as it has now changed
303 { ConfigurationXML configuration; } 271 { ConfigurationXML configuration; }
304 272
305 if (gSessionData->mCounterOverflow) { 273 if (gSessionData->mCounterOverflow > 0) {
306 logg->logError(__FILE__, __LINE__, "Exceeded maximum number of %d performance counters", MAX_PERFORMANCE_COUNTERS); 274 logg->logError(__FILE__, __LINE__, "Only %i performance counters counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
307 handleException(); 275 handleException();
308 } 276 }
309} 277}
diff --git a/daemon/StreamlineSetup.h b/daemon/StreamlineSetup.h
index 841735d..a27a7ac 100644
--- a/daemon/StreamlineSetup.h
+++ b/daemon/StreamlineSetup.h
@@ -32,7 +32,7 @@ private:
32 char* readCommand(int*); 32 char* readCommand(int*);
33 void handleRequest(char* xml); 33 void handleRequest(char* xml);
34 void handleDeliver(char* xml); 34 void handleDeliver(char* xml);
35 void sendData(const char* data, int length, int type); 35 void sendData(const char* data, uint32_t length, char type);
36 void sendString(const char* string, int type) {sendData(string, strlen(string), type);} 36 void sendString(const char* string, int type) {sendData(string, strlen(string), type);}
37 void sendEvents(); 37 void sendEvents();
38 void sendConfiguration(); 38 void sendConfiguration();
diff --git a/daemon/common.mk b/daemon/common.mk
index 112b990..ee2415b 100644
--- a/daemon/common.mk
+++ b/daemon/common.mk
@@ -24,7 +24,7 @@ events.xml: events_header.xml $(wildcard events-*.xml) events_footer.xml
24include $(wildcard *.d) 24include $(wildcard *.d)
25include $(wildcard mxml/*.d) 25include $(wildcard mxml/*.d)
26 26
27StreamlineSetup.cpp: events_xml.h 27EventsXML.cpp: events_xml.h
28ConfigurationXML.cpp: configuration_xml.h 28ConfigurationXML.cpp: configuration_xml.h
29 29
30# Don't regenerate conf-lex.c or conf-parse.c 30# Don't regenerate conf-lex.c or conf-parse.c
diff --git a/daemon/configuration.xml b/daemon/configuration.xml
index 62ccd08..b44c00a 100644
--- a/daemon/configuration.xml
+++ b/daemon/configuration.xml
@@ -1,47 +1,57 @@
1<?xml version="1.0" encoding='UTF-8'?> 1<?xml version="1.0" encoding="UTF-8"?>
2<configurations revision="2"> 2<configurations revision="3">
3 <configuration counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <configuration counter="ARM_ARM11_ccnt" event="0xff"/>
4 <configuration counter="ARM_ARM11_cnt0" event="0x7" title="Instruction" name="Executed" per_cpu="yes" description="Instructions executed"/> 4 <configuration counter="ARM_ARM11_cnt0" event="0x7"/>
5 <configuration counter="ARM_ARM11_cnt1" event="0xb" title="Cache" name="Data miss" per_cpu="yes" description="Data cache miss, not including Cache Operations"/> 5 <configuration counter="ARM_ARM11_cnt1" event="0xb"/>
6 <configuration counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 6 <configuration counter="ARM_ARM11MPCore_ccnt" event="0xff"/>
7 <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08" title="Core" name="Instructions" per_cpu="yes" description="Instructions executed"/> 7 <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08"/>
8 <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b" title="Cache" name="Data read miss" per_cpu="yes" description="Data cache miss, not including Cache Operations"/> 8 <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b"/>
9 <configuration counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 9 <configuration counter="ARM_Cortex-A5_ccnt" event="0xff"/>
10 <configuration counter="ARM_Cortex-A5_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 10 <configuration counter="ARM_Cortex-A5_cnt0" event="0x8"/>
11 <configuration counter="ARM_Cortex-A5_cnt1" event="0x1" title="Cache" name="Instruction refill" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 11 <configuration counter="ARM_Cortex-A5_cnt1" event="0x1"/>
12 <configuration counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 12 <configuration counter="ARM_Cortex-A7_ccnt" event="0xff"/>
13 <configuration counter="ARM_Cortex-A7_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 13 <configuration counter="ARM_Cortex-A7_cnt0" event="0x08"/>
14 <configuration counter="ARM_Cortex-A7_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/> 14 <configuration counter="ARM_Cortex-A7_cnt1" event="0x10"/>
15 <configuration counter="ARM_Cortex-A7_cnt2" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" supports_event_based_sampling="yes" description="Level 2 data cache access"/> 15 <configuration counter="ARM_Cortex-A7_cnt2" event="0x16"/>
16 <configuration counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 16 <configuration counter="ARM_Cortex-A8_ccnt" event="0xff"/>
17 <configuration counter="ARM_Cortex-A8_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 17 <configuration counter="ARM_Cortex-A8_cnt0" event="0x8"/>
18 <configuration counter="ARM_Cortex-A8_cnt1" event="0x44" title="Cache" name="L2 miss" per_cpu="yes" supports_event_based_sampling="yes" description="Any cacheable miss in the L2 cache"/> 18 <configuration counter="ARM_Cortex-A8_cnt1" event="0x44"/>
19 <configuration counter="ARM_Cortex-A8_cnt2" event="0x43" title="Cache" name="L1 miss" per_cpu="yes" supports_event_based_sampling="yes" description="Any accesses to the L2 cache"/> 19 <configuration counter="ARM_Cortex-A8_cnt2" event="0x43"/>
20 <configuration counter="ARM_Cortex-A8_cnt3" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/> 20 <configuration counter="ARM_Cortex-A8_cnt3" event="0x10"/>
21 <configuration counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 21 <configuration counter="ARM_Cortex-A9_ccnt" event="0xff"/>
22 <configuration counter="ARM_Cortex-A9_cnt0" event="0x68" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/> 22 <configuration counter="ARM_Cortex-A9_cnt0" event="0x68"/>
23 <configuration counter="ARM_Cortex-A9_cnt1" event="0x06" title="Instruction" name="Memory read" per_cpu="yes" supports_event_based_sampling="yes" description="Memory-reading instruction architecturally executed"/> 23 <configuration counter="ARM_Cortex-A9_cnt1" event="0x06"/>
24 <configuration counter="ARM_Cortex-A9_cnt2" event="0x07" title="Instruction" name="Memory write" per_cpu="yes" supports_event_based_sampling="yes" description="Memory-writing instruction architecturally executed"/> 24 <configuration counter="ARM_Cortex-A9_cnt2" event="0x07"/>
25 <configuration counter="ARM_Cortex-A9_cnt3" event="0x03" title="Cache" name="Data refill" per_cpu="yes" supports_event_based_sampling="yes" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 25 <configuration counter="ARM_Cortex-A9_cnt3" event="0x03"/>
26 <configuration counter="ARM_Cortex-A9_cnt4" event="0x04" title="Cache" name="Data access" per_cpu="yes" supports_event_based_sampling="yes" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 26 <configuration counter="ARM_Cortex-A9_cnt4" event="0x04"/>
27 <configuration counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 27 <configuration counter="ARM_Cortex-A15_ccnt" event="0xff"/>
28 <configuration counter="ARM_Cortex-A15_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 28 <configuration counter="ARM_Cortex-A15_cnt0" event="0x8"/>
29 <configuration counter="ARM_Cortex-A15_cnt1" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" supports_event_based_sampling="yes" description="Level 2 data cache access"/> 29 <configuration counter="ARM_Cortex-A15_cnt1" event="0x16"/>
30 <configuration counter="ARM_Cortex-A15_cnt2" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/> 30 <configuration counter="ARM_Cortex-A15_cnt2" event="0x10"/>
31 <configuration counter="ARM_Cortex-A15_cnt3" event="0x19" title="Bus" name="Access" per_cpu="yes" supports_event_based_sampling="yes" description="Bus - Access"/> 31 <configuration counter="ARM_Cortex-A15_cnt3" event="0x19"/>
32 <configuration counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 32 <configuration counter="ARM_Cortex-A53_ccnt" event="0x11"/>
33 <configuration counter="Scorpion_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 33 <configuration counter="ARM_Cortex-A53_cnt0" event="0x8"/>
34 <configuration counter="Scorpion_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/> 34 <configuration counter="ARM_Cortex-A53_cnt1" event="0x16"/>
35 <configuration counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 35 <configuration counter="ARM_Cortex-A53_cnt2" event="0x10"/>
36 <configuration counter="ScorpionMP_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 36 <configuration counter="ARM_Cortex-A53_cnt3" event="0x19"/>
37 <configuration counter="ScorpionMP_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/> 37 <configuration counter="ARM_Cortex-A57_ccnt" event="0x11"/>
38 <configuration counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 38 <configuration counter="ARM_Cortex-A57_cnt0" event="0x8"/>
39 <configuration counter="Krait_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/> 39 <configuration counter="ARM_Cortex-A57_cnt1" event="0x16"/>
40 <configuration counter="Krait_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/> 40 <configuration counter="ARM_Cortex-A57_cnt2" event="0x10"/>
41 <configuration counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/> 41 <configuration counter="ARM_Cortex-A57_cnt3" event="0x19"/>
42 <configuration counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/> 42 <configuration counter="Scorpion_ccnt" event="0xff"/>
43 <configuration counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/> 43 <configuration counter="Scorpion_cnt0" event="0x08"/>
44 <configuration counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/> 44 <configuration counter="Scorpion_cnt1" event="0x10"/>
45 <configuration counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Frequency setting of the CPU"/> 45 <configuration counter="ScorpionMP_ccnt" event="0xff"/>
46 <configuration counter="L2C-310_cnt0" event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/> 46 <configuration counter="ScorpionMP_cnt0" event="0x08"/>
47 <configuration counter="ScorpionMP_cnt1" event="0x10"/>
48 <configuration counter="Krait_ccnt" event="0xff"/>
49 <configuration counter="Krait_cnt0" event="0x08"/>
50 <configuration counter="Krait_cnt1" event="0x10"/>
51 <configuration counter="Linux_block_rq_wr"/>
52 <configuration counter="Linux_block_rq_rd"/>
53 <configuration counter="Linux_meminfo_memused"/>
54 <configuration counter="Linux_meminfo_memfree"/>
55 <configuration counter="Linux_power_cpu_freq"/>
56 <configuration counter="L2C-310_cnt0" event="0x1"/>
47</configurations> 57</configurations>
diff --git a/daemon/escape.c b/daemon/escape.c
index a154515..3eec1f8 100644
--- a/daemon/escape.c
+++ b/daemon/escape.c
@@ -50,14 +50,20 @@ int main(int argc, char *argv[]) {
50 printf("static const unsigned char "); 50 printf("static const unsigned char ");
51 print_escaped_path(path); 51 print_escaped_path(path);
52 printf("[] = {"); 52 printf("[] = {");
53 for (; (ch = fgetc(in)) != EOF; ++len) { 53 for (;;) {
54 ch = fgetc(in);
54 if (len != 0) { 55 if (len != 0) {
55 printf(","); 56 printf(",");
56 } 57 }
57 if (len % 12 == 0) { 58 if (len % 12 == 0) {
58 printf("\n "); 59 printf("\n ");
59 } 60 }
60 printf(" 0x%.2x", ch); 61 // Write out a null character after the contents of the file but do not increment len
62 printf(" 0x%.2x", (ch == EOF ? 0 : ch));
63 if (ch == EOF) {
64 break;
65 }
66 ++len;
61 } 67 }
62 printf("\n};\nstatic const unsigned int "); 68 printf("\n};\nstatic const unsigned int ");
63 print_escaped_path(path); 69 print_escaped_path(path);
diff --git a/daemon/events-ARM11.xml b/daemon/events-ARM11.xml
index 9f31313..57e3235 100644
--- a/daemon/events-ARM11.xml
+++ b/daemon/events-ARM11.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_ARM11_cnt" count="3"/> 1 <counter_set name="ARM_ARM11_cnt" count="3"/>
2 <category name="ARM11" counter_set="ARM_ARM11_cnt" per_cpu="yes"> 2 <category name="ARM11" counter_set="ARM_ARM11_cnt" per_cpu="yes">
3 <event counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/> 4 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
5 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/> 5 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
6 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/> 6 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
diff --git a/daemon/events-ARM11MPCore.xml b/daemon/events-ARM11MPCore.xml
index 68ca9a5..2d5c5e1 100644
--- a/daemon/events-ARM11MPCore.xml
+++ b/daemon/events-ARM11MPCore.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_ARM11MPCore_cnt" count="3"/> 1 <counter_set name="ARM_ARM11MPCore_cnt" count="3"/>
2 <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cnt" per_cpu="yes"> 2 <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cnt" per_cpu="yes">
3 <event counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/> 4 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
5 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/> 5 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
6 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/> 6 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
diff --git a/daemon/events-CCI-400.xml b/daemon/events-CCI-400.xml
index 2be0df3..86db208 100644
--- a/daemon/events-CCI-400.xml
+++ b/daemon/events-CCI-400.xml
@@ -1,6 +1,6 @@
1 <counter_set name="cci-400_cnt" count="4"/> 1 <counter_set name="cci-400_cnt" count="4"/>
2 <category name="CCI-400" counter_set="cci-400_cnt" per_cpu="no" supports_event_based_sampling="yes"> 2 <category name="CCI-400" counter_set="cci-400_cnt" per_cpu="no" supports_event_based_sampling="yes">
3 <event counter="cci-400_ccnt" event="0xff" title="CCI-400" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="cci-400_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
4 4
5 <option_set name="Slave"> 5 <option_set name="Slave">
6 <option event_delta="0x00" name="S0" description="Slave interface 0"/> 6 <option event_delta="0x00" name="S0" description="Slave interface 0"/>
diff --git a/daemon/events-Cortex-A15.xml b/daemon/events-Cortex-A15.xml
index e3de814..faa8b1c 100644
--- a/daemon/events-Cortex-A15.xml
+++ b/daemon/events-Cortex-A15.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_Cortex-A15_cnt" count="6"/> 1 <counter_set name="ARM_Cortex-A15_cnt" count="6"/>
2 <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> 4 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/daemon/events-Cortex-A5.xml b/daemon/events-Cortex-A5.xml
index 77dd838..a5b1546 100644
--- a/daemon/events-Cortex-A5.xml
+++ b/daemon/events-Cortex-A5.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_Cortex-A5_cnt" count="2"/> 1 <counter_set name="ARM_Cortex-A5_cnt" count="2"/>
2 <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/daemon/events-Cortex-A53.xml b/daemon/events-Cortex-A53.xml
index 0ffa412..577dcd9 100644
--- a/daemon/events-Cortex-A53.xml
+++ b/daemon/events-Cortex-A53.xml
@@ -1,7 +1,7 @@
1 <counter_set name="ARM_Cortex-A53_cnt" count="6"/> 1 <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
2 <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <!-- 0x11 CPU_CYCLES - Cycle --> 3 <!-- 0x11 CPU_CYCLES - Cycle -->
4 <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 4 <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
5 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment --> 5 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill --> 7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
@@ -15,7 +15,7 @@
15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill --> 15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed --> 17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
18 <event event="0x08" title="-" name="INST_RETIRED" description="Instruction architecturally executed"/> 18 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
19 <!-- 0x09 EXC_TAKEN - Exception taken --> 19 <!-- 0x09 EXC_TAKEN - Exception taken -->
20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return --> 21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
@@ -27,145 +27,145 @@
27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed --> 27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
29 <!-- 0x13 MEM_ACCESS - Data memory access --> 29 <!-- 0x13 MEM_ACCESS - Data memory access -->
30 <event event="0x13" title="-" name="MEM_ACCESS" description="Data memory access"/> 30 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access --> 31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
32 <event event="0x14" title="-" name="L1I_CACHE" description="Level 1 instruction cache access"/> 32 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back --> 33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
34 <event event="0x15" title="-" name="L1D_CACHE_WB" description="Level 1 data cache Write-Back"/> 34 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
35 <!-- 0x16 L2D_CACHE - Level 2 data cache access --> 35 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
36 <event event="0x16" title="-" name="L2D_CACHE" description="Level 2 data cache access"/> 36 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill --> 37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
38 <event event="0x17" title="-" name="L2D_CACHE_REFILL" description="Level 2 data cache refill"/> 38 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back --> 39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
40 <event event="0x18" title="-" name="L2D_CACHE_WB" description="Level 2 data cache Write-Back"/> 40 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
41 <!-- 0x19 BUS_ACCESS - Bus access --> 41 <!-- 0x19 BUS_ACCESS - Bus access -->
42 <event event="0x19" title="-" name="BUS_ACCESS" description="Bus access"/> 42 <event event="0x19" title="Bus" name="Access" description="Bus access"/>
43 <!-- 0x1A MEMORY_ERROR - Local memory error --> 43 <!-- 0x1A MEMORY_ERROR - Local memory error -->
44 <event event="0x1A" title="-" name="MEMORY_ERROR" description="Local memory error"/> 44 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
45 <!-- 0x1B INST_SPEC - Operation speculatively executed --> 45 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
46 <event event="0x1B" title="-" name="INST_SPEC" description="Operation speculatively executed"/> 46 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base --> 47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
48 <event event="0x1C" title="-" name="TTBR_WRITE_RETIRED" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/> 48 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
49 <!-- 0x1D BUS_CYCLES - Bus cycle --> 49 <!-- 0x1D BUS_CYCLES - Bus cycle -->
50 <event event="0x1D" title="-" name="BUS_CYCLES" description="Bus cycle"/> 50 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
51 <!-- 0x1E CHAIN - Odd performance counter chain mode --> 51 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
52 <event event="0x1E" title="-" name="CHAIN" description="Odd performance counter chain mode"/> 52 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read --> 53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
54 <event event="0x40" title="-" name="L1D_CACHE_LD" description="Level 1 data cache access - Read"/> 54 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write --> 55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
56 <event event="0x41" title="-" name="L1D_CACHE_ST" description="Level 1 data cache access - Write"/> 56 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read --> 57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
58 <event event="0x42" title="-" name="L1D_CACHE_REFILL_LD" description="Level 1 data cache refill - Read"/> 58 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write --> 59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
60 <event event="0x43" title="-" name="L1D_CACHE_REFILL_ST" description="Level 1 data cache refill - Write"/> 60 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim --> 61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
62 <event event="0x46" title="-" name="L1D_CACHE_WB_VICTIM" description="Level 1 data cache Write-back - Victim"/> 62 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency --> 63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
64 <event event="0x47" title="-" name="L1D_CACHE_WB_CLEAN" description="Level 1 data cache Write-back - Cleaning and coherency"/> 64 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate --> 65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
66 <event event="0x48" title="-" name="L1D_CACHE_INVAL" description="Level 1 data cache invalidate"/> 66 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read --> 67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
68 <event event="0x4C" title="-" name="L1D_TLB_REFILL_LD" description="Level 1 data TLB refill - Read"/> 68 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write --> 69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
70 <event event="0x4D" title="-" name="L1D_TLB_REFILL_ST" description="Level 1 data TLB refill - Write"/> 70 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read --> 71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
72 <event event="0x50" title="-" name="L2D_CACHE_LD" description="Level 2 data cache access - Read"/> 72 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write --> 73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
74 <event event="0x51" title="-" name="L2D_CACHE_ST" description="Level 2 data cache access - Write"/> 74 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read --> 75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
76 <event event="0x52" title="-" name="L2D_CACHE_REFILL_LD" description="Level 2 data cache refill - Read"/> 76 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write --> 77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
78 <event event="0x53" title="-" name="L2D_CACHE_REFILL_ST" description="Level 2 data cache refill - Write"/> 78 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim --> 79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
80 <event event="0x56" title="-" name="L2D_CACHE_WB_VICTIM" description="Level 2 data cache Write-back - Victim"/> 80 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency --> 81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
82 <event event="0x57" title="-" name="L2D_CACHE_WB_CLEAN" description="Level 2 data cache Write-back - Cleaning and coherency"/> 82 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate --> 83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
84 <event event="0x58" title="-" name="L2D_CACHE_INVAL" description="Level 2 data cache invalidate"/> 84 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read --> 85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
86 <event event="0x60" title="-" name="BUS_ACCESS_LD" description="Bus access - Read"/> 86 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write --> 87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
88 <event event="0x61" title="-" name="BUS_ACCESS_ST" description="Bus access - Write"/> 88 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal --> 89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
90 <event event="0x62" title="-" name="BUS_ACCESS_SHARED" description="Bus access - Normal"/> 90 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal --> 91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
92 <event event="0x63" title="-" name="BUS_ACCESS_NOT_SHARED" description="Bus access - Not normal"/> 92 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal --> 93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
94 <event event="0x64" title="-" name="BUS_ACCESS_NORMAL" description="Bus access - Normal"/> 94 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral --> 95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
96 <event event="0x65" title="-" name="BUS_ACCESS_PERIPH" description="Bus access - Peripheral"/> 96 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read --> 97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
98 <event event="0x66" title="-" name="MEM_ACCESS_LD" description="Data memory access - Read"/> 98 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write --> 99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
100 <event event="0x67" title="-" name="MEM_ACCESS_ST" description="Data memory access - Write"/> 100 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read --> 101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
102 <event event="0x68" title="-" name="UNALIGNED_LD_SPEC" description="Unaligned access - Read"/> 102 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write --> 103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
104 <event event="0x69" title="-" name="UNALIGNED_ST_SPEC" description="Unaligned access - Write"/> 104 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access --> 105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
106 <event event="0x6A" title="-" name="UNALIGNED_LDST_SPEC" description="Unaligned access"/> 106 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX --> 107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
108 <event event="0x6C" title="-" name="LDREX_SPEC" description="Exclusive operation speculatively executed - LDREX"/> 108 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass --> 109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
110 <event event="0x6D" title="-" name="STREX_PASS_SPEC" description="Exclusive instruction speculatively executed - STREX pass"/> 110 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail --> 111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
112 <event event="0x6E" title="-" name="STREX_FAIL_SPEC" description="Exclusive operation speculatively executed - STREX fail"/> 112 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load --> 113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
114 <event event="0x70" title="-" name="LD_SPEC" description="Operation speculatively executed - Load"/> 114 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store --> 115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
116 <event event="0x71" title="-" name="ST_SPEC" description="Operation speculatively executed - Store"/> 116 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store --> 117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
118 <event event="0x72" title="-" name="LDST_SPEC" description="Operation speculatively executed - Load or store"/> 118 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing --> 119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
120 <event event="0x73" title="-" name="DP_SPEC" description="Operation speculatively executed - Integer data processing"/> 120 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD --> 121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
122 <event event="0x74" title="-" name="ASE_SPEC" description="Operation speculatively executed - Advanced SIMD"/> 122 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP --> 123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
124 <event event="0x75" title="-" name="VFP_SPEC" description="Operation speculatively executed - VFP"/> 124 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC --> 125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
126 <event event="0x76" title="-" name="PC_WRITE_SPEC" description="Operation speculatively executed - Software change of the PC"/> 126 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing --> 127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
128 <event event="0x77" title="-" name="CRYPTO_SPEC" description="Operation speculatively executed, crypto data processing"/> 128 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch --> 129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
130 <event event="0x78" title="-" name="BR_IMMED_SPEC" description="Branch speculatively executed - Immediate branch"/> 130 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return --> 131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
132 <event event="0x79" title="-" name="BR_RETURN_SPEC" description="Branch speculatively executed - Procedure return"/> 132 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch --> 133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
134 <event event="0x7A" title="-" name="BR_INDIRECT_SPEC" description="Branch speculatively executed - Indirect branch"/> 134 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB --> 135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
136 <event event="0x7C" title="-" name="ISB_SPEC" description="Barrier speculatively executed - ISB"/> 136 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB --> 137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
138 <event event="0x7D" title="-" name="DSB_SPEC" description="Barrier speculatively executed - DSB"/> 138 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB --> 139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
140 <event event="0x7E" title="-" name="DMB_SPEC" description="Barrier speculatively executed - DMB"/> 140 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous --> 141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
142 <event event="0x81" title="-" name="EXC_UNDEF" description="Exception taken, other synchronous"/> 142 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call --> 143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
144 <event event="0x82" title="-" name="EXC_SVC" description="Exception taken, Supervisor Call"/> 144 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort --> 145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
146 <event event="0x83" title="-" name="EXC_PABORT" description="Exception taken, Instruction Abort"/> 146 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError --> 147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
148 <event event="0x84" title="-" name="EXC_DABORT" description="Exception taken, Data Abort or SError"/> 148 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ --> 149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
150 <event event="0x86" title="-" name="EXC_IRQ" description="Exception taken, IRQ"/> 150 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ --> 151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
152 <event event="0x87" title="-" name="EXC_FIQ" description="Exception taken, FIQ"/> 152 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call --> 153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
154 <event event="0x88" title="-" name="EXC_SMC" description="Exception taken, Secure Monitor Call"/> 154 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call --> 155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
156 <event event="0x8A" title="-" name="EXC_HVC" description="Exception taken, Hypervisor Call"/> 156 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally --> 157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
158 <event event="0x8B" title="-" name="EXC_TRAP_PABORT" description="Exception taken, Instruction Abort not taken locally"/> 158 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally --> 159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
160 <event event="0x8C" title="-" name="EXC_TRAP_DABORT" description="Exception taken, Data Abort or SError not taken locally"/> 160 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken Other traps not taken locally --> 161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
162 <event event="0x8D" title="-" name="EXC_TRAP_OTHER" description="Exception taken – Other traps not taken locally"/> 162 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally --> 163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
164 <event event="0x8E" title="-" name="EXC_TRAP_IRQ" description="Exception taken, IRQ not taken locally"/> 164 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally --> 165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
166 <event event="0x8F" title="-" name="EXC_TRAP_FIQ" description="Exception taken, FIQ not taken locally"/> 166 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed Load Acquire --> 167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
168 <event event="0x90" title="-" name="RC_LD_SPEC" description="Release consistency instruction speculatively executed – Load Acquire"/> 168 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed Store Release --> 169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
170 <event event="0x91" title="-" name="RC_ST_SPEC" description="Release consistency instruction speculatively executed – Store Release"/> 170 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
171 </category> 171 </category>
diff --git a/daemon/events-Cortex-A57.xml b/daemon/events-Cortex-A57.xml
index e8c0a61..b7178c0 100644
--- a/daemon/events-Cortex-A57.xml
+++ b/daemon/events-Cortex-A57.xml
@@ -1,8 +1,8 @@
1 <counter_set name="ARM_Cortex-A57_cnt" count="6"/> 1 <counter_set name="ARM_Cortex-A57_cnt" count="6"/>
2 <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <!-- 0x11 CPU_CYCLES - Cycle --> 3 <!-- 0x11 CPU_CYCLES - Cycle -->
4 <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 4 <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
5 <!-- 0x00 SW_INCR - Instruction architecturally executed number (condition check pass) - Software increment --> 5 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill --> 7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
@@ -15,7 +15,7 @@
15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill --> 15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed --> 17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
18 <event event="0x08" title="-" name="INST_RETIRED" description="Instruction architecturally executed"/> 18 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
19 <!-- 0x09 EXC_TAKEN - Exception taken --> 19 <!-- 0x09 EXC_TAKEN - Exception taken -->
20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return --> 21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
@@ -27,145 +27,145 @@
27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed --> 27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
29 <!-- 0x13 MEM_ACCESS - Data memory access --> 29 <!-- 0x13 MEM_ACCESS - Data memory access -->
30 <event event="0x13" title="-" name="MEM_ACCESS" description="Data memory access"/> 30 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access --> 31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
32 <event event="0x14" title="-" name="L1I_CACHE" description="Level 1 instruction cache access"/> 32 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back --> 33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
34 <event event="0x15" title="-" name="L1D_CACHE_WB" description="Level 1 data cache Write-Back"/> 34 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
35 <!-- 0x16 L2D_CACHE - Level 2 data cache access --> 35 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
36 <event event="0x16" title="-" name="L2D_CACHE" description="Level 2 data cache access"/> 36 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill --> 37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
38 <event event="0x17" title="-" name="L2D_CACHE_REFILL" description="Level 2 data cache refill"/> 38 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back --> 39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
40 <event event="0x18" title="-" name="L2D_CACHE_WB" description="Level 2 data cache Write-Back"/> 40 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
41 <!-- 0x19 BUS_ACCESS - Bus access --> 41 <!-- 0x19 BUS_ACCESS - Bus access -->
42 <event event="0x19" title="-" name="BUS_ACCESS" description="Bus access"/> 42 <event event="0x19" title="Bus" name="Access" description="Bus access"/>
43 <!-- 0x1A MEMORY_ERROR - Local memory error --> 43 <!-- 0x1A MEMORY_ERROR - Local memory error -->
44 <event event="0x1A" title="-" name="MEMORY_ERROR" description="Local memory error"/> 44 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
45 <!-- 0x1B INST_SPEC - Operation speculatively executed --> 45 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
46 <event event="0x1B" title="-" name="INST_SPEC" description="Operation speculatively executed"/> 46 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base --> 47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
48 <event event="0x1C" title="-" name="TTBR_WRITE_RETIRED" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/> 48 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
49 <!-- 0x1D BUS_CYCLES - Bus cycle --> 49 <!-- 0x1D BUS_CYCLES - Bus cycle -->
50 <event event="0x1D" title="-" name="BUS_CYCLES" description="Bus cycle"/> 50 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
51 <!-- 0x1E CHAIN - Odd performance counter chain mode --> 51 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
52 <event event="0x1E" title="-" name="CHAIN" description="Odd performance counter chain mode"/> 52 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read --> 53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
54 <event event="0x40" title="-" name="L1D_CACHE_LD" description="Level 1 data cache access - Read"/> 54 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write --> 55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
56 <event event="0x41" title="-" name="L1D_CACHE_ST" description="Level 1 data cache access - Write"/> 56 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read --> 57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
58 <event event="0x42" title="-" name="L1D_CACHE_REFILL_LD" description="Level 1 data cache refill - Read"/> 58 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write --> 59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
60 <event event="0x43" title="-" name="L1D_CACHE_REFILL_ST" description="Level 1 data cache refill - Write"/> 60 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim --> 61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
62 <event event="0x46" title="-" name="L1D_CACHE_WB_VICTIM" description="Level 1 data cache Write-back - Victim"/> 62 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency --> 63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
64 <event event="0x47" title="-" name="L1D_CACHE_WB_CLEAN" description="Level 1 data cache Write-back - Cleaning and coherency"/> 64 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate --> 65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
66 <event event="0x48" title="-" name="L1D_CACHE_INVAL" description="Level 1 data cache invalidate"/> 66 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read --> 67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
68 <event event="0x4C" title="-" name="L1D_TLB_REFILL_LD" description="Level 1 data TLB refill - Read"/> 68 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write --> 69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
70 <event event="0x4D" title="-" name="L1D_TLB_REFILL_ST" description="Level 1 data TLB refill - Write"/> 70 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read --> 71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
72 <event event="0x50" title="-" name="L2D_CACHE_LD" description="Level 2 data cache access - Read"/> 72 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write --> 73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
74 <event event="0x51" title="-" name="L2D_CACHE_ST" description="Level 2 data cache access - Write"/> 74 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read --> 75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
76 <event event="0x52" title="-" name="L2D_CACHE_REFILL_LD" description="Level 2 data cache refill - Read"/> 76 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write --> 77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
78 <event event="0x53" title="-" name="L2D_CACHE_REFILL_ST" description="Level 2 data cache refill - Write"/> 78 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim --> 79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
80 <event event="0x56" title="-" name="L2D_CACHE_WB_VICTIM" description="Level 2 data cache Write-back - Victim"/> 80 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency --> 81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
82 <event event="0x57" title="-" name="L2D_CACHE_WB_CLEAN" description="Level 2 data cache Write-back - Cleaning and coherency"/> 82 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate --> 83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
84 <event event="0x58" title="-" name="L2D_CACHE_INVAL" description="Level 2 data cache invalidate"/> 84 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read --> 85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
86 <event event="0x60" title="-" name="BUS_ACCESS_LD" description="Bus access - Read"/> 86 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write --> 87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
88 <event event="0x61" title="-" name="BUS_ACCESS_ST" description="Bus access - Write"/> 88 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal --> 89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
90 <event event="0x62" title="-" name="BUS_ACCESS_SHARED" description="Bus access - Normal"/> 90 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal --> 91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
92 <event event="0x63" title="-" name="BUS_ACCESS_NOT_SHARED" description="Bus access - Not normal"/> 92 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal --> 93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
94 <event event="0x64" title="-" name="BUS_ACCESS_NORMAL" description="Bus access - Normal"/> 94 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral --> 95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
96 <event event="0x65" title="-" name="BUS_ACCESS_PERIPH" description="Bus access - Peripheral"/> 96 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read --> 97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
98 <event event="0x66" title="-" name="MEM_ACCESS_LD" description="Data memory access - Read"/> 98 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write --> 99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
100 <event event="0x67" title="-" name="MEM_ACCESS_ST" description="Data memory access - Write"/> 100 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read --> 101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
102 <event event="0x68" title="-" name="UNALIGNED_LD_SPEC" description="Unaligned access - Read"/> 102 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write --> 103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
104 <event event="0x69" title="-" name="UNALIGNED_ST_SPEC" description="Unaligned access - Write"/> 104 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access --> 105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
106 <event event="0x6A" title="-" name="UNALIGNED_LDST_SPEC" description="Unaligned access"/> 106 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX --> 107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
108 <event event="0x6C" title="-" name="LDREX_SPEC" description="Exclusive operation speculatively executed - LDREX"/> 108 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass --> 109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
110 <event event="0x6D" title="-" name="STREX_PASS_SPEC" description="Exclusive instruction speculatively executed - STREX pass"/> 110 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail --> 111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
112 <event event="0x6E" title="-" name="STREX_FAIL_SPEC" description="Exclusive operation speculatively executed - STREX fail"/> 112 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load --> 113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
114 <event event="0x70" title="-" name="LD_SPEC" description="Operation speculatively executed - Load"/> 114 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store --> 115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
116 <event event="0x71" title="-" name="ST_SPEC" description="Operation speculatively executed - Store"/> 116 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store --> 117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
118 <event event="0x72" title="-" name="LDST_SPEC" description="Operation speculatively executed - Load or store"/> 118 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing --> 119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
120 <event event="0x73" title="-" name="DP_SPEC" description="Operation speculatively executed - Integer data processing"/> 120 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD --> 121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
122 <event event="0x74" title="-" name="ASE_SPEC" description="Operation speculatively executed - Advanced SIMD"/> 122 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP --> 123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
124 <event event="0x75" title="-" name="VFP_SPEC" description="Operation speculatively executed - VFP"/> 124 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC --> 125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
126 <event event="0x76" title="-" name="PC_WRITE_SPEC" description="Operation speculatively executed - Software change of the PC"/> 126 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing --> 127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
128 <event event="0x77" title="-" name="CRYPTO_SPEC" description="Operation speculatively executed, crypto data processing"/> 128 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch --> 129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
130 <event event="0x78" title="-" name="BR_IMMED_SPEC" description="Branch speculatively executed - Immediate branch"/> 130 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return --> 131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
132 <event event="0x79" title="-" name="BR_RETURN_SPEC" description="Branch speculatively executed - Procedure return"/> 132 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch --> 133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
134 <event event="0x7A" title="-" name="BR_INDIRECT_SPEC" description="Branch speculatively executed - Indirect branch"/> 134 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB --> 135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
136 <event event="0x7C" title="-" name="ISB_SPEC" description="Barrier speculatively executed - ISB"/> 136 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB --> 137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
138 <event event="0x7D" title="-" name="DSB_SPEC" description="Barrier speculatively executed - DSB"/> 138 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB --> 139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
140 <event event="0x7E" title="-" name="DMB_SPEC" description="Barrier speculatively executed - DMB"/> 140 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous --> 141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
142 <event event="0x81" title="-" name="EXC_UNDEF" description="Exception taken, other synchronous"/> 142 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call --> 143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
144 <event event="0x82" title="-" name="EXC_SVC" description="Exception taken, Supervisor Call"/> 144 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort --> 145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
146 <event event="0x83" title="-" name="EXC_PABORT" description="Exception taken, Instruction Abort"/> 146 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError --> 147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
148 <event event="0x84" title="-" name="EXC_DABORT" description="Exception taken, Data Abort or SError"/> 148 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ --> 149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
150 <event event="0x86" title="-" name="EXC_IRQ" description="Exception taken, IRQ"/> 150 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ --> 151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
152 <event event="0x87" title="-" name="EXC_FIQ" description="Exception taken, FIQ"/> 152 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call --> 153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
154 <event event="0x88" title="-" name="EXC_SMC" description="Exception taken, Secure Monitor Call"/> 154 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call --> 155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
156 <event event="0x8A" title="-" name="EXC_HVC" description="Exception taken, Hypervisor Call"/> 156 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally --> 157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
158 <event event="0x8B" title="-" name="EXC_TRAP_PABORT" description="Exception taken, Instruction Abort not taken locally"/> 158 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally --> 159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
160 <event event="0x8C" title="-" name="EXC_TRAP_DABORT" description="Exception taken, Data Abort or SError not taken locally"/> 160 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken Other traps not taken locally --> 161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
162 <event event="0x8D" title="-" name="EXC_TRAP_OTHER" description="Exception taken – Other traps not taken locally"/> 162 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally --> 163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
164 <event event="0x8E" title="-" name="EXC_TRAP_IRQ" description="Exception taken, IRQ not taken locally"/> 164 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally --> 165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
166 <event event="0x8F" title="-" name="EXC_TRAP_FIQ" description="Exception taken, FIQ not taken locally"/> 166 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed Load Acquire --> 167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
168 <event event="0x90" title="-" name="RC_LD_SPEC" description="Release consistency instruction speculatively executed – Load Acquire"/> 168 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed Store Release --> 169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
170 <event event="0x91" title="-" name="RC_ST_SPEC" description="Release consistency instruction speculatively executed – Store Release"/> 170 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
171 </category> 171 </category>
diff --git a/daemon/events-Cortex-A7.xml b/daemon/events-Cortex-A7.xml
index bbd7a26..54d7264 100644
--- a/daemon/events-Cortex-A7.xml
+++ b/daemon/events-Cortex-A7.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_Cortex-A7_cnt" count="4"/> 1 <counter_set name="ARM_Cortex-A7_cnt" count="4"/>
2 <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> 4 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/daemon/events-Cortex-A8.xml b/daemon/events-Cortex-A8.xml
index a301f1f..f251823 100644
--- a/daemon/events-Cortex-A8.xml
+++ b/daemon/events-Cortex-A8.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_Cortex-A8_cnt" count="4"/> 1 <counter_set name="ARM_Cortex-A8_cnt" count="4"/>
2 <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
@@ -22,7 +22,7 @@
22 <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/> 22 <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>
23 <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/> 23 <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>
24 <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/> 24 <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>
25 <event event="0x43" title="Cache" name="L1 miss" description="Any accesses to the L2 cache"/> 25 <event event="0x43" title="Cache" name="L2 access" description="Any accesses to the L2 cache"/>
26 <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/> 26 <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>
27 <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/> 27 <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>
28 <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/> 28 <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>
diff --git a/daemon/events-Cortex-A9.xml b/daemon/events-Cortex-A9.xml
index 9ebb308..75f09c8 100644
--- a/daemon/events-Cortex-A9.xml
+++ b/daemon/events-Cortex-A9.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ARM_Cortex-A9_cnt" count="6"/> 1 <counter_set name="ARM_Cortex-A9_cnt" count="6"/>
2 <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/daemon/events-Krait-architected.xml b/daemon/events-Krait-architected.xml
index 4254666..b8d3bcb 100644
--- a/daemon/events-Krait-architected.xml
+++ b/daemon/events-Krait-architected.xml
@@ -1,6 +1,6 @@
1 <counter_set name="Krait_cnt" count="4"/> 1 <counter_set name="Krait_cnt" count="4"/>
2 <category name="Krait" counter_set="Krait_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Krait" counter_set="Krait_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/daemon/events-Linux.xml b/daemon/events-Linux.xml
index 42baf14..05dc613 100644
--- a/daemon/events-Linux.xml
+++ b/daemon/events-Linux.xml
@@ -9,7 +9,9 @@
9 <event counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/> 9 <event counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/>
10 <event counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/> 10 <event counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/>
11 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" display="maximum" units="B" average_selection="yes" description="Memory used by OS disk buffers"/> 11 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" display="maximum" units="B" average_selection="yes" description="Memory used by OS disk buffers"/>
12 <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Frequency setting of the CPU"/> 12 <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" series_composition="overlay" average_selection="yes" average_cores="yes" description="Frequency setting of the CPU"/>
13 <event counter="Linux_power_cpu_idle" title="Power" name="Idle" per_cpu="yes" display="maximum" average_selection="yes" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/> 13 <event counter="Linux_power_cpu_idle" title="Idle" name="State" per_cpu="yes" display="maximum" average_selection="yes" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
14 <event counter="Linux_cpu_wait_contention" title="CPU Contention" name="Wait" per_cpu="no" display="maximum" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on contended resource"/>
15 <event counter="Linux_cpu_wait_io" title="CPU I/O" name="Wait" per_cpu="no" display="maximum" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on I/O resource"/>
14 </category> 16 </category>
15 17
diff --git a/daemon/events-Mali-T6xx.xml b/daemon/events-Mali-T6xx.xml
index 3d795de..647e3d5 100644
--- a/daemon/events-Mali-T6xx.xml
+++ b/daemon/events-Mali-T6xx.xml
@@ -4,30 +4,30 @@
4 </category> 4 </category>
5 5
6 <category name="Mali-T6xx-PMShader" per_cpu="no"> 6 <category name="Mali-T6xx-PMShader" per_cpu="no">
7 <event counter="ARM_Mali-T6xx_PM_SHADER_0" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/> 7 <event counter="ARM_Mali-T6xx_PM_SHADER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
8 <event counter="ARM_Mali-T6xx_PM_SHADER_1" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/> 8 <event counter="ARM_Mali-T6xx_PM_SHADER_1" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
9 <event counter="ARM_Mali-T6xx_PM_SHADER_2" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/> 9 <event counter="ARM_Mali-T6xx_PM_SHADER_2" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
10 <event counter="ARM_Mali-T6xx_PM_SHADER_3" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/> 10 <event counter="ARM_Mali-T6xx_PM_SHADER_3" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/>
11 <event counter="ARM_Mali-T6xx_PM_SHADER_4" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/> 11 <event counter="ARM_Mali-T6xx_PM_SHADER_4" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/>
12 <event counter="ARM_Mali-T6xx_PM_SHADER_5" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/> 12 <event counter="ARM_Mali-T6xx_PM_SHADER_5" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/>
13 <event counter="ARM_Mali-T6xx_PM_SHADER_6" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/> 13 <event counter="ARM_Mali-T6xx_PM_SHADER_6" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
14 <event counter="ARM_Mali-T6xx_PM_SHADER_7" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/> 14 <event counter="ARM_Mali-T6xx_PM_SHADER_7" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
15 </category> 15 </category>
16 16
17 <category name="Mali-T6xx-PMTiler" per_cpu="no"> 17 <category name="Mali-T6xx-PMTiler" per_cpu="no">
18 <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" units="%" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/> 18 <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
19 </category> 19 </category>
20 20
21 <category name="Mali-T6xx-PML2" per_cpu="no"> 21 <category name="Mali-T6xx-PML2" per_cpu="no">
22 <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" units="%" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/> 22 <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
23 <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" units="%" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/> 23 <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
24 </category> 24 </category>
25 25
26 <category name="Mali-T6xx-MMU_AS" per_cpu="no"> 26 <category name="Mali-T6xx-MMU_AS" per_cpu="no">
27 <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/> 27 <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
28 <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/> 28 <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
29 <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/> 29 <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
30 <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/> 30 <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
31 </category> 31 </category>
32 32
33 <category name="Mali-T6xx-MMU_page_fault" per_cpu="no"> 33 <category name="Mali-T6xx-MMU_page_fault" per_cpu="no">
diff --git a/daemon/events-Mali-T6xx_hw.xml b/daemon/events-Mali-T6xx_hw.xml
index 7c7b1ea..1fd9c4e 100644
--- a/daemon/events-Mali-T6xx_hw.xml
+++ b/daemon/events-Mali-T6xx_hw.xml
@@ -1,278 +1,113 @@
1 1
2 <category name="Mali-T6xx-JobManager" per_cpu="no"> 2 <category name="Mali-T6xx-JobManager" per_cpu="no">
3 <event counter="ARM_Mali-T6xx_MESSAGES_SENT" title="Mali GPU Job Manager" name="Job Manager messages sent" description="Number of JCB messages sent by the Job Manager."/>
4 <event counter="ARM_Mali-T6xx_MESSAGES_RECEIVED" title="Mali GPU Job Manager" name="Job Manager messages received " description="Number of JCB messages received by the Job Manager."/>
5 <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali GPU Job Manager" name="GPU active cycles" description="Number of cycles the GPU was active."/>
6 <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali GPU Job Manager" name="IRQ active cycles" description="Number of cycles with active interrupts."/>
7 3
8 <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali GPU Job Manager" name="Job Slot 0 jobs complete" description="Number of jobs completed in Job Slot 0."/> 4 <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali Job Manager Cycles" name="GPU cycles" description="Number of cycles the GPU was active"/>
9 <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali GPU Job Manager" name="Job Slot 0 tasks complete" description="Number of tasks completed in Job Slot 0."/> 5 <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali Job Manager Cycles" name="IRQ cycles" description="Number of cycles the GPU had a pending interrupt"/>
10 <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 0 active" description="Number of cycles Job Slot 0 was active."/> 6 <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali Job Manager Cycles" name="JS0 cycles" description="Number of cycles JS0 (fragment) was active"/>
11 <event counter="ARM_Mali-T6xx_JS0_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 0 wait read" description="Number of cycles Job Slot 0 stalled waiting for descriptors to be read."/> 7 <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali Job Manager Cycles" name="JS1 cycles" description="Number of cycles JS1 (vertex/tiler/compute) was active"/>
12 <event counter="ARM_Mali-T6xx_JS0_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 0 wait issue" description="Number of cycles Job Slot 0 stalled unable to issue tasks because all available cores were full."/> 8 <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali Job Manager Cycles" name="JS2 cycles" description="Number of cycles JS2 (compute) was active"/>
13 <event counter="ARM_Mali-T6xx_JS0_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 0 wait depend" description="Number of cycles Job Slot 0 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
14 <event counter="ARM_Mali-T6xx_JS0_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 0 wait finish" description="Number of cycles Job Slot 0 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
15 9
16 <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali GPU Job Manager" name="Job Slot 1 jobs complete" description="Number of jobs completed in Job Slot 1."/> 10 <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali Job Manager Work" name="JS0 jobs" description="Number of Jobs (fragment) completed in JS0"/>
17 <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali GPU Job Manager" name="Job Slot 1 tasks complete" description="Number of tasks completed in Job Slot 1."/> 11 <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali Job Manager Work" name="JS0 tasks" description="Number of Tasks completed in JS0"/>
18 <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 1 active" description="Number of cycles Job Slot 1 was active."/> 12 <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali Job Manager Work" name="JS1 jobs" description="Number of Jobs (vertex/tiler/compute) completed in JS1"/>
19 <event counter="ARM_Mali-T6xx_JS1_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 1 wait read" description="Number of cycles Job Slot 1 stalled waiting for descriptors to be read."/> 13 <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali Job Manager Work" name="JS1 tasks" description="Number of Tasks completed in JS1"/>
20 <event counter="ARM_Mali-T6xx_JS1_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 1 wait issue" description="Number of cycles Job Slot 1 stalled unable to issue tasks because all available cores were full."/> 14 <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali Job Manager Work" name="JS2 tasks" description="Number of Tasks completed in JS2"/>
21 <event counter="ARM_Mali-T6xx_JS1_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 1 wait depend" description="Number of cycles Job Slot 1 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/> 15 <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali Job Manager Work" name="JS2 jobs" description="Number of Jobs (compute) completed in JS2"/>
22 <event counter="ARM_Mali-T6xx_JS1_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 1 wait finish" description="Number of cycles Job Slot 1 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
23 16
24 <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali GPU Job Manager" name="Job Slot 2 jobs complete" description="Number of jobs completed in Job Slot 2."/>
25 <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali GPU Job Manager" name="Job Slot 2 tasks complete" description="Number of tasks completed in Job Slot 2."/>
26 <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 2 active" description="Number of cycles Job Slot 2 was active."/>
27 <event counter="ARM_Mali-T6xx_JS2_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 2 wait read" description="Number of cycles Job Slot 2 stalled waiting for descriptors to be read."/>
28 <event counter="ARM_Mali-T6xx_JS2_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 2 wait issue" description="Number of cycles Job Slot 2 stalled unable to issue tasks because all available cores were full."/>
29 <event counter="ARM_Mali-T6xx_JS2_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 2 wait depend" description="Number of cycles Job Slot 2 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
30 <event counter="ARM_Mali-T6xx_JS2_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 2 wait finish" description="Number of cycles Job Slot 2 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
31<!--
32 <event counter="ARM_Mali-T6xx_JS3_JOBS" title="Mali GPU Job Manager" name="Job Slot 3 jobs complete" description="Number of jobs completed in Job Slot 3."/>
33 <event counter="ARM_Mali-T6xx_JS3_TASKS" title="Mali GPU Job Manager" name="Job Slot 3 tasks complete" description="Number of tasks completed in Job Slot 3."/>
34 <event counter="ARM_Mali-T6xx_JS3_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 3 active" description="Number of cycles Job Slot 3 was active."/>
35 <event counter="ARM_Mali-T6xx_JS3_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 3 wait read" description="Number of cycles Job Slot 3 stalled waiting for descriptors to be read."/>
36 <event counter="ARM_Mali-T6xx_JS3_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 3 wait issue" description="Number of cycles Job Slot 3 stalled unable to issue tasks because all available cores were full."/>
37 <event counter="ARM_Mali-T6xx_JS3_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 3 wait depend" description="Number of cycles Job Slot 3 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
38 <event counter="ARM_Mali-T6xx_JS3_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 3 wait finish" description="Number of cycles Job Slot 3 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
39
40 <event counter="ARM_Mali-T6xx_JS4_JOBS" title="Mali GPU Job Manager" name="Job Slot 4 jobs complete" description="Number of jobs completed in Job Slot 4."/>
41 <event counter="ARM_Mali-T6xx_JS4_TASKS" title="Mali GPU Job Manager" name="Job Slot 4 tasks complete" description="Number of tasks completed in Job Slot 4."/>
42 <event counter="ARM_Mali-T6xx_JS4_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 4 active" description="Number of cycles Job Slot 4 was active."/>
43 <event counter="ARM_Mali-T6xx_JS4_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 4 wait read" description="Number of cycles Job Slot 4 stalled waiting for descriptors to be read."/>
44 <event counter="ARM_Mali-T6xx_JS4_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 4 wait issue" description="Number of cycles Job Slot 4 stalled unable to issue tasks because all available cores were full."/>
45 <event counter="ARM_Mali-T6xx_JS4_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 4 wait depend" description="Number of cycles Job Slot 4 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
46 <event counter="ARM_Mali-T6xx_JS4_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 4 wait finish" description="Number of cycles Job Slot 4 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
47
48 <event counter="ARM_Mali-T6xx_JS5_JOBS" title="Mali GPU Job Manager" name="Job Slot 5 jobs complete" description="Number of jobs completed in Job Slot 5."/>
49 <event counter="ARM_Mali-T6xx_JS5_TASKS" title="Mali GPU Job Manager" name="Job Slot 5 tasks complete" description="Number of tasks completed in Job Slot 5."/>
50 <event counter="ARM_Mali-T6xx_JS5_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 5 active" description="Number of cycles Job Slot 5 was active."/>
51 <event counter="ARM_Mali-T6xx_JS5_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 5 wait read" description="Number of cycles Job Slot 5 stalled waiting for descriptors to be read."/>
52 <event counter="ARM_Mali-T6xx_JS5_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 5 wait issue" description="Number of cycles Job Slot 5 stalled unable to issue tasks because all available cores were full."/>
53 <event counter="ARM_Mali-T6xx_JS5_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 5 wait depend" description="Number of cycles Job Slot 5 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
54 <event counter="ARM_Mali-T6xx_JS5_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 5 wait finish" description="Number of cycles Job Slot 5 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
55
56 <event counter="ARM_Mali-T6xx_JS6_JOBS" title="Mali GPU Job Manager" name="Job Slot 6 jobs complete" description="Number of jobs completed in Job Slot 6."/>
57 <event counter="ARM_Mali-T6xx_JS6_TASKS" title="Mali GPU Job Manager" name="Job Slot 6 tasks complete" description="Number of tasks completed in Job Slot 6."/>
58 <event counter="ARM_Mali-T6xx_JS6_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 6 active" description="Number of cycles Job Slot 6 was active."/>
59 <event counter="ARM_Mali-T6xx_JS6_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 6 wait read" description="Number of cycles Job Slot 6 stalled waiting for descriptors to be read."/>
60 <event counter="ARM_Mali-T6xx_JS6_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 6 wait issue" description="Number of cycles Job Slot 6 stalled unable to issue tasks because all available cores were full."/>
61 <event counter="ARM_Mali-T6xx_JS6_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 6 wait depend" description="Number of cycles Job Slot 6 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
62 <event counter="ARM_Mali-T6xx_JS6_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 6 wait finish" description="Number of cycles Job Slot 6 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
63-->
64 </category> 17 </category>
65 18
66 <category name="Mali-T6xx-Tiler" per_cpu="no"> 19 <category name="Mali-T6xx-Tiler" per_cpu="no">
67<!--
68 <event counter="ARM_Mali-T6xx_JOBS_PROCESSED" title="Mali GPU Tiler" name="Jobs processed" description="Number of jobs processed."/>
69-->
70 <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali GPU Tiler" name="Triangles processed" description="Number of triangles processed."/>
71 <event counter="ARM_Mali-T6xx_QUADS" title="Mali GPU Tiler" name="Quads processed" description="Number of quads processed."/>
72 <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali GPU Tiler" name="Polygons processed" description="Number of polygons processed."/>
73 <event counter="ARM_Mali-T6xx_POINTS" title="Mali GPU Tiler" name="Points processed" description="Number of points processed."/>
74
75 <event counter="ARM_Mali-T6xx_LINES" title="Mali GPU Tiler" name="Lines processed" description="Number of lines processed."/>
76 <event counter="ARM_Mali-T6xx_VCACHE_HIT" title="Mali GPU Tiler" name="Vertex cache hits" description="Number of vertex cache hits."/>
77 <event counter="ARM_Mali-T6xx_VCACHE_MISS" title="Mali GPU Tiler" name="Vertex cache misses" description="Number of vertex cache misses."/>
78 <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali GPU Tiler" name="Front facing primitives" description="Number of front facing primitives."/>
79
80 <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali GPU Tiler" name="Back facing primitives" description="Number of back facing primitives."/>
81 <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali GPU Tiler" name="Visible primitives" description="Number of visible primitives."/>
82 <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali GPU Tiler" name="Culled primitives" description="Number of culled primitives."/>
83 <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali GPU Tiler" name="Clipped primitives" description="Number of clipped primitives."/>
84
85 <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali GPU Tiler" name="Level 0 primitives" description="Number of primitives tiled to hierarchy level 0."/>
86 <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali GPU Tiler" name="Level 1 primitives" description="Number of primitives tiled to hierarchy level 1."/>
87 <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali GPU Tiler" name="Level 2 primitives" description="Number of primitives tiled to hierarchy level 2."/>
88 <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali GPU Tiler" name="Level 3 primitives" description="Number of primitives tiled to hierarchy level 3."/>
89
90 <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali GPU Tiler" name="Level 4 primitives" description="Number of primitives tiled to hierarchy level 4."/>
91 <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali GPU Tiler" name="Level 5 primitives" description="Number of primitives tiled to hierarchy level 5."/>
92 <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali GPU Tiler" name="Level 6 primitives" description="Number of primitives tiled to hierarchy level 6."/>
93 <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali GPU Tiler" name="Level 7 primitives" description="Number of primitives tiled to hierarchy level 7."/>
94
95 <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali GPU Tiler" name="Primitives tiled to 1 command" description="Number of primitives producing 1 command in tile list."/>
96 <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali GPU Tiler" name="Primitives tiled to 2 commands" description="Number of primitives producing 2 commands in tile list."/>
97 <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali GPU Tiler" name="Primitives tiled to 3 commands" description="Number of primitives producing 3 commands in tile list."/>
98 <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali GPU Tiler" name="Primitives tiled to 4 commands" description="Number of primitives producing 4 commands in tile list."/>
99
100 <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali GPU Tiler" name="Primitives tiled to 4-7 commands" description="Number of primitives producing 4-7 commands in tile list."/>
101 <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali GPU Tiler" name="Primitives tiled to 8-15 commands" description="Number of primitives producing 8-15 commands in tile list."/>
102 <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali GPU Tiler" name="Primitives tiled to 16-63 commands" description="Number of primitives producing 16-63 commands in tile list."/>
103 <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali GPU Tiler" name="Primitives tiled to >= 64 commands" description="Number of primitives producing >= 64 commands in tile list."/>
104
105 <event counter="ARM_Mali-T6xx_COMPRESS_IN" title="Mali GPU Tiler" name="Commands entering compressor" description="Number of commands entering compressor."/>
106 <event counter="ARM_Mali-T6xx_COMPRESS_OUT" title="Mali GPU Tiler" name="Compressed commands from compressor" description="Number of compressed commands produced by compressor."/>
107 <event counter="ARM_Mali-T6xx_COMPRESS_FLUSH" title="Mali GPU Tiler" name="Compressor state flushes" description="Number of compressor state flushes."/>
108 <event counter="ARM_Mali-T6xx_TIMESTAMPS" title="Mali GPU Tiler" name="Timestamps emitted" description="Number of timestamps emitted."/>
109 20
110 <event counter="ARM_Mali-T6xx_PCACHE_HIT" title="Mali GPU Tiler" name="Pointer-cache hits" description="Number of pointer-cache hits."/> 21 <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali Tiler Primitives" name="Polygons" description="Number of polygons processed"/>
111 <event counter="ARM_Mali-T6xx_PCACHE_MISS" title="Mali GPU Tiler" name="Pointer-cache misses" description="Number of pointer-cache misses."/> 22 <event counter="ARM_Mali-T6xx_QUADS" title="Mali Tiler Primitives" name="Quads" description="Number of quads processed"/>
112 <event counter="ARM_Mali-T6xx_PCACHE_LINE" title="Mali GPU Tiler" name="Pointer-cache line-fills" description="Number of pointer-cache line-fills."/> 23 <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali Tiler Primitives" name="Triangles" description="Number of triangles processed"/>
113 <event counter="ARM_Mali-T6xx_PCACHE_STALL" title="Mali GPU Tiler" name="Pointer-cache stalls" description="Number of pointer-cache stalls."/> 24 <event counter="ARM_Mali-T6xx_LINES" title="Mali Tiler Primitives" name="Lines" description="Number of lines processed"/>
25 <event counter="ARM_Mali-T6xx_POINTS" title="Mali Tiler Primitives" name="Points" description="Number of points processed"/>
26
27 <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali Tiler Culling" name="Front facing prims" description="Number of front facing primitives"/>
28 <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali Tiler Culling" name="Back facing prims" description="Number of back facing primitives"/>
29 <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali Tiler Culling" name="Visible prims" description="Number of visible primitives"/>
30 <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali Tiler Culling" name="Culled prims" description="Number of culled primitives"/>
31 <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali Tiler Culling" name="Clipped prims" description="Number of clipped primitives"/>
32
33 <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali Tiler Hierarchy" name="L0 prims" description="Number of primitives in hierarchy level 0"/>
34 <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali Tiler Hierarchy" name="L1 prims" description="Number of primitives in hierarchy level 1"/>
35 <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali Tiler Hierarchy" name="L2 prims" description="Number of primitives in hierarchy level 2"/>
36 <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali Tiler Hierarchy" name="L3 prims" description="Number of primitives in hierarchy level 3"/>
37 <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali Tiler Hierarchy" name="L4 prims" description="Number of primitives in hierarchy level 4"/>
38 <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali Tiler Hierarchy" name="L5 prims" description="Number of primitives in hierarchy level 5"/>
39 <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali Tiler Hierarchy" name="L6 prims" description="Number of primitives in hierarchy level 6"/>
40 <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali Tiler Hierarchy" name="L7 prims" description="Number of primitives in hierarchy level 7"/>
41
42 <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali Tiler Commands" name="Prims in 1 command" description="Number of primitives producing 1 command"/>
43 <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali Tiler Commands" name="Prims in 2 command" description="Number of primitives producing 2 commands"/>
44 <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali Tiler Commands" name="Prims in 3 command" description="Number of primitives producing 3 commands"/>
45 <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali Tiler Commands" name="Prims in 4 command" description="Number of primitives producing 4 commands"/>
46 <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali Tiler Commands" name="Prims in 4-7 commands" description="Number of primitives producing 4-7 commands"/>
47 <event counter="ARM_Mali-T6xx_COMMAND_5_7" title="Mali Tiler Commands" name="Prims in 5-7 commands" description="Number of primitives producing 5-7 commands"/>
48 <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali Tiler Commands" name="Prims in 8-15 commands" description="Number of primitives producing 8-15 commands"/>
49 <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali Tiler Commands" name="Prims in 16-63 commands" description="Number of primitives producing 16-63 commands"/>
50 <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali Tiler Commands" name="Prims in &gt;= 64 commands" description="Number of primitives producing &gt;= 64 commands"/>
114 51
115 <event counter="ARM_Mali-T6xx_WRBUF_HIT" title="Mali GPU Tiler" name="Write-buffer hits" description="Number of write-buffer hits."/>
116 <event counter="ARM_Mali-T6xx_WRBUF_MISS" title="Mali GPU Tiler" name="Write-buffer misses" description="Number of write-buffer misses."/>
117 <event counter="ARM_Mali-T6xx_WRBUF_LINE" title="Mali GPU Tiler" name="Write-buffer full-lines written out" description="Number of complete cache lines written out from the write buffer."/>
118 <event counter="ARM_Mali-T6xx_WRBUF_PARTIAL" title="Mali GPU Tiler" name="Write-buffer partial-lines written out" description="Number of incomplete cache lines written out from the write buffer."/>
119
120 <event counter="ARM_Mali-T6xx_WRBUF_STALL" title="Mali GPU Tiler" name="Write-buffer stalls" description="Number of write-buffer stalls."/>
121 <event counter="ARM_Mali-T6xx_ACTIVE" title="Mali GPU Tiler" name="Tiler active cycles" description="Number of cycles the tiler is active."/>
122 <event counter="ARM_Mali-T6xx_LOADING_DESC" title="Mali GPU Tiler" name="Cycles loading descriptors" description="Number of cycle spent loading descriptors while the tiler frontend is otherwise idle."/>
123 <event counter="ARM_Mali-T6xx_INDEX_WAIT" title="Mali GPU Tiler" name="Cycles index fetch miss" description="Number of cycles the vertex cache could accept an index, but due to a miss, the index fetcher could not provide one."/>
124
125 <event counter="ARM_Mali-T6xx_INDEX_RANGE_WAIT" title="Mali GPU Tiler" name="Cycles index out of range" description="Number of cycles the index fetcher provides an index, but the index is outside the range of currently shaded vertices. Only relevant for fused jobs."/>
126 <event counter="ARM_Mali-T6xx_VERTEX_WAIT" title="Mali GPU Tiler" name="Cycles vertex cache miss" description="Number of cycles the primitive assembly could accept a vertex, but due to a vertex cache miss, the vertex fetcher is unable to provide a vertex."/>
127 <event counter="ARM_Mali-T6xx_PCACHE_WAIT" title="Mali GPU Tiler" name="Cycles pointer cache miss" description="Number of cycles the command compressor could accept a command, but due to a cache miss, the pointer cache is unable to provide the polygon list pointer."/>
128 <event counter="ARM_Mali-T6xx_WRBUF_WAIT" title="Mali GPU Tiler" name="Cycles no write buffer entry" description="Number of cycles a command could be written to the write buffer, but no write buffer entry is available."/>
129
130 <event counter="ARM_Mali-T6xx_BUS_READ" title="Mali GPU Tiler" name="Data beats from L2 cache read." description="Number of data beats (64-bit) on read from the L2 cache."/>
131 <event counter="ARM_Mali-T6xx_BUS_WRITE" title="Mali GPU Tiler" name="Data beats from L2 cache write" description="Number of data beats (64-bit) on written to the L2 cache."/>
132
133 <event counter="ARM_Mali-T6xx_UTLB_STALL" title="Mali GPU Tiler" name="uTLB cycles stall" description="uTLB: Cycles with stall on input AXI address channel."/>
134
135 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_MISS" title="Mali GPU Tiler" name="uTLB replay buffer cache misses" description="uTLB: Number of cache misses on accesses from replay buffer."/>
136 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_FULL" title="Mali GPU Tiler" name="uTLB cycle reply buffer full" description="uTLB: Number of cycles replay buffer is full."/>
137 <event counter="ARM_Mali-T6xx_UTLB_NEW_MISS" title="Mali GPU Tiler" name="uTLB cache misses on new request" description="uTLB: Number of cache misses on new requests."/>
138 <event counter="ARM_Mali-T6xx_UTLB_HIT" title="Mali GPU Tiler" name="uTLB cache hits" description="uTLB: Number of cache hits."/>
139 </category> 52 </category>
140 53
141 <category name="Mali-T6xx-ShaderCore" per_cpu="no"> 54 <category name="Mali-T6xx-ShaderCore" per_cpu="no">
142<!--
143 <event counter="ARM_Mali-T6xx_SHADER_CORE_ACTIVE" title="Mali GPU Shader Core" name="Shader core active cycles" description="Number of cycles the shader core active."/>
144-->
145 <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Fragment" name="Fragment active cycles" description="Number of cycles fragment processing was active."/>
146 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Fragment" name="Primitives" description="Number of primitives."/>
147 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Fragment" name="Primitives dropped" description="Primitives dropped due to Polygon List Reader coverage."/>
148 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_DESC" title="Fragment" name="Stall: Waiting for descriptors" description="Number of cycles spent waiting for descriptors / 2."/>
149
150 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_PLR" title="Fragment" name="Stall: Waiting for PLR" description="Cycles spent waiting for Polygon List Reader."/>
151 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_VERT" title="Fragment" name="Stall: Waiting for vertices" description="Cycles spent waiting for vertices."/>
152 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_TRISETUP" title="Fragment" name="Stall: Waiting for trisetup" description="Cycles spent waiting for trisetup."/>
153 <event counter="ARM_Mali-T6xx_FRAG_CYCLES_RAST" title="Fragment" name="Stall: Waiting for rasterizer" description="Cycles spent waiting for rasterizer."/>
154
155 <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Fragment" name="Fragment threads started" description="Number of fragment threads started."/>
156 <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Fragment" name="Dummy threads started" description="Number of dummy threads started."/>
157 <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Fragment" name="Quads rasterized" description="Number of quads rasterized."/>
158 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Fragment" name="Quads doing early ZS test" description="Number of quads doing early ZS test."/>
159
160 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Fragment" name="Quads killed early ZS test" description="Number of quads killed in early ZS test."/>
161 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Fragment" name="Threads doing late ZS test" description="Number of threads doing in late ZS test."/>
162 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Fragment" name="Threads killed late ZS test" description="Number of threads killed in late ZS test."/>
163 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Fragment" name="cycles waiting for physical tile buffers" description="Number of cycles spent waiting while no physical tile buffers were available for rendering."/>
164
165 <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Fragment" name="Tiles rendered" description="Number of tiles rendered."/>
166 <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Fragment" name="Transaction elimination signature matches" description="Transaction elimination signature matches."/>
167 <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Compute" name="Compute active cycles" description="Number of cycles compute processing was active."/>
168 <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Compute" name="Tasks" description="Number of tasks."/>
169 55
170 <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Compute" name="Compute threads started" description="Number of compute threads started."/> 56 <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Mali Core Cycles" name="Tripipe cycles" description="Number of cycles the Tripipe was active"/>
171 <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Compute" name="Stall: Waiting for descriptors" description="Number of cycles spent waiting for descriptors."/> 57 <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Mali Core Cycles" name="Fragment cycles" description="Number of cycles fragment processing was active"/>
172 <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Tripipe" name="Tripipe active cycles" description="Number of cycles the Tripipe was active."/> 58 <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Mali Core Cycles" name="Compute cycles" description="Number of cycles vertex\compute processing was active"/>
173 <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Arithmetic Pipeline" name="Instructions per pipe" description="Number of instruction words in the arithmetic pipelines, divided by the number of arithmetic pipelines."/> 59 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Mali Core Cycles" name="Fragment cycles waiting for tile" description="Number of cycles spent waiting for a physical tile buffer"/>
60
61 <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Mali Core Threads" name="Fragment threads" description="Number of fragment threads started"/>
62 <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Mali Core Threads" name="Dummy fragment threads" description="Number of dummy fragment threads started"/>
63 <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Mali Core Threads" name="Compute threads" description="Number of vertex\compute threads started"/>
64 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
65 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
66 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
67 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
68
69 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
70 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
71 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
72 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
73
74 <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Mali Fragment Quads" name="Quads rasterized" description="Number of quads rasterized"/>
75 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Mali Fragment Quads" name="Quads doing early ZS" description="Number of quads doing early ZS test"/>
76 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Mali Fragment Quads" name="Quads killed early Z" description="Number of quads killed by early ZS test"/>
77
78 <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Mali Fragment Tasks" name="Tiles rendered" description="Number of tiles rendered"/>
79 <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Mali Fragment Tasks" name="Tile writes killed by TE" description="Number of tile writes skipped by transaction elimination"/>
80
81 <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Mali Arithmetic Pipe" name="A instructions" description="Number of instructions completed by the the A-pipe (normalized per pipeline)"/>
82
83 <event counter="ARM_Mali-T6xx_LS_WORDS" title="Mali Load/Store Pipe" name="LS instructions" description="Number of instructions completed by the LS-pipe"/>
84 <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Mali Load/Store Pipe" name="LS instruction issues" description="Number of instructions issued to the LS-pipe, including restarts"/>
85
86 <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Mali Texture Pipe" name="T instructions" description="Number of instructions completed by the T-pipe"/>
87 <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Mali Texture Pipe" name="T instruction issues" description="Number of instructions issused to the T-pipe, including restarts"/>
88 <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Mali Texture Pipe" name="Cache misses" description="Number of instructions in the T-pipe, recirculated due to cache miss"/>
89
90 <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Mali Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store cache"/>
91 <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Mali Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store cache"/>
92 <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Mali Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store cache"/>
93 <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Mali Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store cache"/>
94 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Mali Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store cache"/>
95 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Mali Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store cache"/>
96 <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Mali Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store cache"/>
97 <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Mali Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store cache"/>
98 <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Mali Load/Store Cache" name="Snoops in to LSC" description="Number of coherent memory snoops in to the Load/Store cache"/>
174 99
175 <event counter="ARM_Mali-T6xx_ARITH_CYCLES_REG" title="Arithmetic Pipeline" name="Stall: Register scheduling" description="Number of cycles lost in the arithmetic pipelines due to register scheduling, divided by the number of arithmetic pipelines."/>
176 <event counter="ARM_Mali-T6xx_ARITH_CYCLES_L0" title="Arithmetic Pipeline" name="Stall: Icache miss per pipe" description="Number of cycles lost in the arithmetic pipelines due to L0 instruction cache misses, divided by the number of arithmetic pipelines."/>
177 <event counter="ARM_Mali-T6xx_ARITH_FRAG_DEPEND" title="Arithmetic Pipeline" name="Stall: Fragment dependency fails per pipe" description="Number of fragment dependency check failures in the arithmetic pipelines, divided by the number of arithmetic pipelines."/>
178 <event counter="ARM_Mali-T6xx_LS_WORDS" title="Load/Store Pipeline" name="Load/Store instruction words completed" description="Number of instruction words completed in the Load/Store pipeline."/>
179
180 <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Load/Store Pipeline" name="Full pipeline issues" description="Number of full pipeline issues in the Load/Store pipeline."/>
181 <event counter="ARM_Mali-T6xx_LS_RESTARTS" title="Load/Store Pipeline" name="Stall: Unpairable instruction" description="Number of restarts due to unpairable instructions in the Load/Store pipeline."/>
182 <event counter="ARM_Mali-T6xx_LS_REISSUES_MISS" title="Load/Store Pipeline" name="Stall: Cache misses" description="Number of full pipe re-issues due to cache misses or TLB misses in the Load/Store pipeline."/>
183 <event counter="ARM_Mali-T6xx_LS_REISSUES_VD" title="Load/Store Pipeline" name="Stall: Varying misses" description="Number of full pipe re-issues due to varying data being unavailable in the Load/Store pipeline."/>
184
185 <event counter="ARM_Mali-T6xx_LS_REISSUE_ATTRIB_MISS" title="Load/Store Pipeline" name="Stall: Attribute cache misses" description="Number of full pipe re-issues due to attribute cache misses in the Load/Store pipeline."/>
186 <event counter="ARM_Mali-T6xx_LS_NO_WB" title="Load/Store Pipeline" name="Writeback not used, pause buffer used" description="Writeback not used, and something into pause buffer in the Load/Store pipeline."/>
187 <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Texturing Pipeline" name="Texturing pipeline instruction words completed" description="Number of instruction words completed in the texturing pipeline."/>
188 <event counter="ARM_Mali-T6xx_TEX_BUBBLES" title="Texturing Pipeline" name="Stall: Waiting for barrier" description="Number of bubbles with threads waiting for barrier in the texturing pipeline."/>
189
190 <event counter="ARM_Mali-T6xx_TEX_WORDS_L0" title="Texturing Pipeline" name="Stall: Icache misses" description="Number of instruction words in the texturing pipeline restart loop 1 due to L0 instruction cache miss."/>
191 <event counter="ARM_Mali-T6xx_TEX_WORDS_DESC" title="Texturing Pipeline" name="Stall: Descriptor misses" description="Number of instruction words in the texturing pipeline restart loop 1 due to descriptor misses."/>
192 <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Texturing Pipeline" name="Threads in loop 2" description="Number of threads in the texturing pipeline through loop 2 address calculation."/>
193 <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Texturing Pipeline" name="Stall: Texture cache misses" description="Number of instructions in the texturing pipeline recirculated due to complete texture cache miss."/>
194
195 <event counter="ARM_Mali-T6xx_TEX_RECIRC_DESC" title="Texturing Pipeline" name="Stall: Surface Descriptor misses" description="Number of instructions in the texturing pipeline recirculated due to surface descriptor miss."/>
196 <event counter="ARM_Mali-T6xx_TEX_RECIRC_MULTI" title="Texturing Pipeline" name="Reissue: multipass" description="Number of instructions in the texturing pipeline recirculated due to multipass."/>
197 <event counter="ARM_Mali-T6xx_TEX_RECIRC_PMISS" title="Texturing Pipeline" name="Stall: Partial misses" description="Number of instructions in the texturing pipeline recirculated due to partial cache miss."/>
198 <event counter="ARM_Mali-T6xx_TEX_RECIRC_CONF" title="Texturing Pipeline" name="Stall: Bank conflict" description="Number of instructions in the texturing pipeline recirculated due to texture cache bank conflict."/>
199
200 <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store Cache."/>
201 <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store Cache."/>
202 <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store Cache."/>
203 <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store Cache."/>
204
205 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store Cache."/>
206 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store Cache."/>
207 <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store Cache."/>
208 <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store Cache."/>
209
210 <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Load/Store Cache" name="Snoops in LSC" description="Snoops in the Load/Store Cache."/>
211 <event counter="ARM_Mali-T6xx_AXI_TLB_STALL" title="AXI uTLB" name="Stall: TLB AXI address channel" description="AXI address channel stall generated."/>
212 <event counter="ARM_Mali-T6xx_AXI_TLB_MIESS" title="AXI uTLB" name="Stall: TLB Cache misses" description="New request cache miss."/>
213 <event counter="ARM_Mali-T6xx_AXI_TLB_TRANSACTION" title="AXI uTLB" name="AXI transactions" description="Number of AXI transactions."/>
214
215 <event counter="ARM_Mali-T6xx_LS_TLB_MISS" title="LS uTLB" name="Cache misses per interface" description="Number of cache misses / number of interfaces."/>
216 <event counter="ARM_Mali-T6xx_LS_TLB_HIT" title="LS uTLB" name="Cache hits per interface" description="Number of cache hits / number of interfaces."/>
217 <event counter="ARM_Mali-T6xx_AXI_BEATS_READ" title="AXI" name="Beats read" description="Number of beats read."/>
218 <event counter="ARM_Mali-T6xx_AXI_BEATS_WRITTEN" title="AXI" name="Beats written" description="Number of beats written."/>
219 </category> 100 </category>
220 101
221 <category name="Mali-T6xx-L2AndMMU" per_cpu="no"> 102 <category name="Mali-T6xx-L2AndMMU" per_cpu="no">
222 <event counter="ARM_Mali-T6xx_MMU_TABLE_WALK" title="MMU" name="Page table walks" description="Number of page table walks started."/>
223 <event counter="ARM_Mali-T6xx_MMU_REPLAY_MISS" title="MMU" name="Cache misses from replay buffer" description="Number of cache misses on accesses from replay buffer."/>
224 <event counter="ARM_Mali-T6xx_MMU_REPLAY_FULL" title="MMU" name="MMU full replay buffer (cycles)" description="Number of cycles replay buffer is full."/>
225 <event counter="ARM_Mali-T6xx_MMU_NEW_MISS" title="MMU" name="Cache misses on new requests" description="Number of cache misses on new requests."/>
226
227 <event counter="ARM_Mali-T6xx_MMU_HIT" title="MMU" name="MMU cache hits" description="Number of cache hits."/>
228
229 <event counter="ARM_Mali-T6xx_UTLB_STALL" title="uTLB" name="Stall on input AXI (cycles)" description="Cycles with stall on input AXI address channel."/>
230 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_MISS" title="uTLB" name="Cache misses from replay buffer" description="Number of cache misses on accesses from replay buffer."/>
231 <event counter="ARM_Mali-T6xx_UTLB_REPLAY_FULL" title="uTLB" name="uTLB full replay buffer (cycles)" description="Number of cycles replay buffer is full."/>
232 <event counter="ARM_Mali-T6xx_UTLB_NEW_MISS" title="uTLB" name="Cache misses on new requests" description="Number of cache misses on new requests."/>
233
234 <event counter="ARM_Mali-T6xx_UTLB_HIT" title="uTLB" name="uTLB cache hits" description="Number of cache hits."/>
235
236 <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="L2 Cache" name="External bus write beats" description="External bus write beats."/>
237 <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="L2 Cache" name="External bus read beats" description="External bus read beats."/>
238
239 <event counter="ARM_Mali-T6xx_L2_ANY_LOOKUP" title="L2 Cache" name="Transaction/snoop tag lookups" description="A transaction or a snoop response completes the tag lookup."/>
240 <event counter="ARM_Mali-T6xx_L2_READ_LOOKUP" title="L2 Cache" name="Read transaction tag lookups" description="Any read transaction completes the tag lookup."/>
241 <event counter="ARM_Mali-T6xx_L2_SREAD_LOOKUP" title="L2 Cache" name="Shareable read transaction tag lookups" description="Shareable read transaction tag lookup."/>
242 <event counter="ARM_Mali-T6xx_L2_READ_REPLAY" title="L2 Cache" name="Replayed read transactions" description="Any read transaction is replayed (not serialized)."/>
243
244 <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="L2 Cache" name="Read transaction snoops" description="Read transaction issues a snoop."/>
245 <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="L2 Cache" name="L2 Cache read hits" description="A read hits in the L2 Cache."/>
246 <event counter="ARM_Mali-T6xx_L2_CLEAN_MISS" title="L2 Cache" name="CleanUnique misses" description="A CleanUnique misses in the L2 Cache, line allocated without a linefill."/>
247 <event counter="ARM_Mali-T6xx_L2_WRITE_LOOKUP" title="L2 Cache" name="Write transaction tag lookups" description="Any write transaction completes the tag lookup."/>
248
249 <event counter="ARM_Mali-T6xx_L2_SWRITE_LOOKUP" title="L2 write" name="Shareable write transaction tag lookup" description="Shareable write transaction tag lookup."/>
250 <event counter="ARM_Mali-T6xx_L2_WRITE_REPLAY" title="L2 write" name="Replayed write transaction" description="Any write transaction is replayed (not serialized)."/>
251 <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="L2 write" name="Write transaction snoops" description="Write transaction issues a snoop."/>
252 <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="L2 write" name="L2 write hits" description="A write hits in the L2 Cache."/>
253
254 <event counter="ARM_Mali-T6xx_L2_EXT_READ_FULL" title="L2 Cache" name="External read attempted with full BIU" description="External read attempted, but the BIU read buffer is full."/>
255 <event counter="ARM_Mali-T6xx_L2_EXT_READ_HALF" title="L2 Cache" name="External read requested with more then half full BIU" description="External read requested when the BIU read buffer is more than half full."/>
256 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_FULL" title="L2 Cache" name="External write attempted with full BIU" description="External write attempted, but the BIU write buffer is full."/>
257 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_HALF" title="L2 Cache" name="External write requested with more then half full BIU" description="External write requested when the BIU write buffer is more than half full."/>
258
259 <event counter="ARM_Mali-T6xx_L2_EXT_READ" title="L2 Cache" name="External read" description="External read."/>
260 <event counter="ARM_Mali-T6xx_L2_EXT_READ_LINE" title="L2 Cache" name="External read - linefill" description="External read - linefill."/>
261 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE" title="L2 Cache" name="External write." description="External write."/>
262 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_LINE" title="L2 Cache" name="External write - writeback." description="External write - writeback."/>
263
264 <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_SMALL" title="L2 Cache" name="External write - burst size less than 64B" description="External write - burst size less than 64B."/>
265 <event counter="ARM_Mali-T6xx_L2_EXT_BARRIER" title="L2 Cache" name="External barrier" description="External barrier (even if disabled)."/>
266 <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="L2 Cache" name="External interconnect stalls (AR)" description="A valid read address (AR) is stalled by the external interconnect."/>
267 <event counter="ARM_Mali-T6xx_L2_EXT_R_BUF_FULL" title="L2 Cache" name="External read stalls (full buffer)" description="External read stalled due to the response buffer being full."/>
268 103
269 <event counter="ARM_Mali-T6xx_L2_EXT_RD_BUF_FULL" title="L2 Cache" name="External read not allocated" description="External read could not allocate an entry in the read data buffer."/> 104 <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="Mali L2 Cache" name="External write beats" description="Number of external bus write beats"/>
270 <event counter="ARM_Mali-T6xx_L2_EXT_R_RAW" title="L2 Cache" name="External read stalled (RAW)" description="External read stalled due to the RAW hazard."/> 105 <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="Mali L2 Cache" name="External read beats" description="Number of external bus read beats"/>
271 <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="L2 Cache" name="External interconnect stalls (W channel)" description="Valid write data (W channel) is stalled by the external interconnect."/> 106 <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="Mali L2 Cache" name="Read snoops" description="Number of read transaction snoops"/>
272 <event counter="ARM_Mali-T6xx_L2_EXT_W_BUF_FULL" title="L2 Cache" name="External write stalls (full buffer)" description="External write stalled due to the response buffer being full."/> 107 <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="Mali L2 Cache" name="L2 read hits" description="Number of reads hitting in the L2 cache"/>
108 <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="Mali L2 Cache" name="Write snoops" description="Number of write transaction snoops"/>
109 <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="Mali L2 Cache" name="L2 write hits" description="Number of writes hitting in the L2 cache"/>
110 <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="Mali L2 Cache" name="External bus stalls (AR)" description="Number of cycles a valid read address (AR) is stalled by the external interconnect"/>
111 <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="Mali L2 Cache" name="External bus stalls (W)" description="Number of cycles a valid write data (W channel) is stalled by the external interconnect"/>
273 112
274 <event counter="ARM_Mali-T6xx_L2_EXT_R_W_HAZARD" title="L2 Cache" name="External read stalled (WAW or WAR)" description="External read stalled due to the WAW or WAR hazard."/>
275 <event counter="ARM_Mali-T6xx_L2_TAG_HAZARD" title="L2 Cache" name="Replayed transactions due to tag hazard" description="A transaction will be replayed due to a tag hazard."/>
276 <event counter="ARM_Mali-T6xx_L2_SNOOP_FULL" title="L2 Cache" name="Cycles with full snoop buffer" description="Counts every cycle when the snoop buffer is full."/>
277 <event counter="ARM_Mali-T6xx_L2_REPLAY_FULL" title="L2 Cache" name="Cycles with full replay buffer" description="Counts every cycle when the replay buffer is full."/>
278 </category> 113 </category>
diff --git a/daemon/events-Scorpion.xml b/daemon/events-Scorpion.xml
index d08a5a2..fa716fd 100644
--- a/daemon/events-Scorpion.xml
+++ b/daemon/events-Scorpion.xml
@@ -1,6 +1,6 @@
1 <counter_set name="Scorpion_cnt" count="4"/> 1 <counter_set name="Scorpion_cnt" count="4"/>
2 <category name="Scorpion" counter_set="Scorpion_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Scorpion" counter_set="Scorpion_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/daemon/events-ScorpionMP.xml b/daemon/events-ScorpionMP.xml
index dad4c70..c648cce 100644
--- a/daemon/events-ScorpionMP.xml
+++ b/daemon/events-ScorpionMP.xml
@@ -1,6 +1,6 @@
1 <counter_set name="ScorpionMP_cnt" count="4"/> 1 <counter_set name="ScorpionMP_cnt" count="4"/>
2 <category name="ScorpionMP" counter_set="ScorpionMP_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="ScorpionMP" counter_set="ScorpionMP_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
diff --git a/driver/gator_backtrace.c b/driver/gator_backtrace.c
index 94f01e6..0670d6c 100644
--- a/driver/gator_backtrace.c
+++ b/driver/gator_backtrace.c
@@ -10,16 +10,22 @@
10/* 10/*
11 * EABI backtrace stores {fp,lr} on the stack. 11 * EABI backtrace stores {fp,lr} on the stack.
12 */ 12 */
13struct frame_tail_eabi { 13struct stack_frame_eabi {
14 union { 14 union {
15 struct { 15 struct {
16 unsigned long fp; // points to prev_lr 16 unsigned long fp;
17 // May be the fp in the case of a leaf function or clang
17 unsigned long lr; 18 unsigned long lr;
19 // If lr is really the fp, lr2 is the corresponding lr
20 unsigned long lr2;
18 }; 21 };
19 // Used to read 32 bit fp/lr from a 64 bit kernel 22 // Used to read 32 bit fp/lr from a 64 bit kernel
20 struct { 23 struct {
21 u32 fp_32; 24 u32 fp_32;
25 // same as lr above
22 u32 lr_32; 26 u32 lr_32;
27 // same as lr2 above
28 u32 lr2_32;
23 }; 29 };
24 }; 30 };
25}; 31};
@@ -27,61 +33,76 @@ struct frame_tail_eabi {
27static void arm_backtrace_eabi(int cpu, struct pt_regs *const regs, unsigned int depth) 33static void arm_backtrace_eabi(int cpu, struct pt_regs *const regs, unsigned int depth)
28{ 34{
29#if defined(__arm__) || defined(__aarch64__) 35#if defined(__arm__) || defined(__aarch64__)
30 struct frame_tail_eabi *tail; 36 struct stack_frame_eabi *curr;
31 struct frame_tail_eabi *next; 37 struct stack_frame_eabi bufcurr;
32 struct frame_tail_eabi buftail;
33#if defined(__arm__) 38#if defined(__arm__)
34 const bool is_compat = false; 39 const bool is_compat = false;
35 unsigned long fp = regs->ARM_fp; 40 unsigned long fp = regs->ARM_fp;
36 unsigned long sp = regs->ARM_sp; 41 unsigned long sp = regs->ARM_sp;
37 unsigned long lr = regs->ARM_lr; 42 unsigned long lr = regs->ARM_lr;
38 const int frame_offset = 4; 43 const int gcc_frame_offset = sizeof(unsigned long);
39#else 44#else
40 // Is userspace aarch32 (32 bit) 45 // Is userspace aarch32 (32 bit)
41 const bool is_compat = compat_user_mode(regs); 46 const bool is_compat = compat_user_mode(regs);
42 unsigned long fp = (is_compat ? regs->regs[11] : regs->regs[29]); 47 unsigned long fp = (is_compat ? regs->regs[11] : regs->regs[29]);
43 unsigned long sp = (is_compat ? regs->compat_sp : regs->sp); 48 unsigned long sp = (is_compat ? regs->compat_sp : regs->sp);
44 unsigned long lr = (is_compat ? regs->compat_lr : regs->regs[30]); 49 unsigned long lr = (is_compat ? regs->compat_lr : regs->regs[30]);
45 const int frame_offset = (is_compat ? 4 : 0); 50 const int gcc_frame_offset = (is_compat ? sizeof(u32) : 0);
46#endif 51#endif
52 // clang frame offset is always zero
47 int is_user_mode = user_mode(regs); 53 int is_user_mode = user_mode(regs);
48 54
55 // pc (current function) has already been added
56
49 if (!is_user_mode) { 57 if (!is_user_mode) {
50 return; 58 return;
51 } 59 }
52 60
53 /* entry preamble may not have executed */ 61 // Add the lr (parent function)
62 // entry preamble may not have executed
54 gator_add_trace(cpu, lr); 63 gator_add_trace(cpu, lr);
55 64
56 /* check tail is valid */ 65 // check fp is valid
57 if (fp == 0 || fp < sp) { 66 if (fp == 0 || fp < sp) {
58 return; 67 return;
59 } 68 }
60 69
61 tail = (struct frame_tail_eabi *)(fp - frame_offset); 70 // Get the current stack frame
71 curr = (struct stack_frame_eabi *)(fp - gcc_frame_offset);
72 if ((unsigned long)curr & 3) {
73 return;
74 }
62 75
63 while (depth-- && tail && !((unsigned long)tail & 3)) { 76 while (depth-- && curr) {
64 /* Also check accessibility of one struct frame_tail beyond */ 77 if (!access_ok(VERIFY_READ, curr, sizeof(struct stack_frame_eabi)) ||
65 if (!access_ok(VERIFY_READ, tail, sizeof(struct frame_tail_eabi))) 78 __copy_from_user_inatomic(&bufcurr, curr, sizeof(struct stack_frame_eabi))) {
66 return;
67 if (__copy_from_user_inatomic(&buftail, tail, sizeof(struct frame_tail_eabi)))
68 return; 79 return;
80 }
81
82 fp = (is_compat ? bufcurr.fp_32 : bufcurr.fp);
83 lr = (is_compat ? bufcurr.lr_32 : bufcurr.lr);
84
85#define calc_next(reg) ((reg) - gcc_frame_offset)
86 // Returns true if reg is a valid fp
87#define validate_next(reg, curr) \
88 ((reg) != 0 && (calc_next(reg) & 3) == 0 && (unsigned long)(curr) < calc_next(reg))
89
90 // Try lr from the stack as the fp because gcc leaf functions do not push lr
91 // If gcc_frame_offset is non-zero, the lr will also be the clang fp
92 // This assumes code is at a lower address than the stack
93 if (validate_next(lr, curr)) {
94 fp = lr;
95 lr = (is_compat ? bufcurr.lr2_32 : bufcurr.lr2);
96 }
69 97
70 lr = (is_compat ? buftail.lr_32 : buftail.lr);
71 gator_add_trace(cpu, lr); 98 gator_add_trace(cpu, lr);
72 99
73 /* frame pointers should progress back up the stack, towards higher addresses */ 100 if (!validate_next(fp, curr)) {
74 next = (struct frame_tail_eabi *)(lr - frame_offset); 101 return;
75 if (tail >= next || lr == 0) {
76 fp = (is_compat ? buftail.fp_32 : buftail.fp);
77 next = (struct frame_tail_eabi *)(fp - frame_offset);
78 /* check tail is valid */
79 if (tail >= next || fp == 0) {
80 return;
81 }
82 } 102 }
83 103
84 tail = next; 104 // Move to the next stack frame
105 curr = (struct stack_frame_eabi *)calc_next(fp);
85 } 106 }
86#endif 107#endif
87} 108}
@@ -89,11 +110,12 @@ static void arm_backtrace_eabi(int cpu, struct pt_regs *const regs, unsigned int
89#if defined(__arm__) || defined(__aarch64__) 110#if defined(__arm__) || defined(__aarch64__)
90static int report_trace(struct stackframe *frame, void *d) 111static int report_trace(struct stackframe *frame, void *d)
91{ 112{
92 unsigned int *depth = d, cookie = NO_COOKIE, cpu = get_physical_cpu(); 113 unsigned int *depth = d, cookie = NO_COOKIE;
93 unsigned long addr = frame->pc; 114 unsigned long addr = frame->pc;
94 115
95 if (*depth) { 116 if (*depth) {
96#if defined(MODULE) 117#if defined(MODULE)
118 unsigned int cpu = get_physical_cpu();
97 struct module *mod = __module_address(addr); 119 struct module *mod = __module_address(addr);
98 if (mod) { 120 if (mod) {
99 cookie = get_cookie(cpu, current, mod->name, false); 121 cookie = get_cookie(cpu, current, mod->name, false);
diff --git a/driver/gator_events_l2c-310.c b/driver/gator_events_l2c-310.c
index e646215..21aa4a2 100644
--- a/driver/gator_events_l2c-310.c
+++ b/driver/gator_events_l2c-310.c
@@ -11,8 +11,10 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#if defined(CONFIG_OF)
14#include <linux/of.h> 15#include <linux/of.h>
15#include <linux/of_address.h> 16#include <linux/of_address.h>
17#endif
16#include <asm/hardware/cache-l2x0.h> 18#include <asm/hardware/cache-l2x0.h>
17 19
18#include "gator.h" 20#include "gator.h"
@@ -152,16 +154,23 @@ static void __iomem *gator_events_l2c310_probe(void)
152#endif 154#endif
153 }; 155 };
154 int i; 156 int i;
155 157 void __iomem *base;
156#if defined(CONFIG_OF) 158#if defined(CONFIG_OF)
157 if (of_have_populated_dt()) 159 struct device_node *node = of_find_all_nodes(NULL);
158 return of_iomap(of_find_compatible_node(NULL, 160
159 NULL, "arm,pl310-cache"), 0); 161 if (node) {
162 of_node_put(node);
163
164 node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
165 base = of_iomap(node, 0);
166 of_node_put(node);
167
168 return base;
169 }
160#endif 170#endif
161 171
162 for (i = 0; i < ARRAY_SIZE(variants); i++) { 172 for (i = 0; i < ARRAY_SIZE(variants); i++) {
163 void __iomem *base = ioremap(variants[i], SZ_4K); 173 base = ioremap(variants[i], SZ_4K);
164
165 if (base) { 174 if (base) {
166 u32 cache_id = readl(base + L2X0_CACHE_ID); 175 u32 cache_id = readl(base + L2X0_CACHE_ID);
167 176
diff --git a/driver/gator_events_mali_t6xx_hw.c b/driver/gator_events_mali_t6xx_hw.c
index fb2e15c..4f49c1d 100644
--- a/driver/gator_events_mali_t6xx_hw.c
+++ b/driver/gator_events_mali_t6xx_hw.c
@@ -22,14 +22,30 @@
22 22
23#include "gator_events_mali_common.h" 23#include "gator_events_mali_common.h"
24 24
25/* If API version is not specified then assume API version 1. */
26#ifndef MALI_DDK_GATOR_API_VERSION
27#define MALI_DDK_GATOR_API_VERSION 1
28#endif
29
30#if (MALI_DDK_GATOR_API_VERSION != 1) && (MALI_DDK_GATOR_API_VERSION != 2)
31#error MALI_DDK_GATOR_API_VERSION is invalid (must be 1 for r1/r2 DDK, or 2 for r3 DDK).
32#endif
33
25/* 34/*
26 * Mali-T6xx 35 * Mali-T6xx
27 */ 36 */
28typedef struct kbase_device *kbase_find_device_type(int); 37typedef struct kbase_device *kbase_find_device_type(int);
29typedef kbase_context *kbase_create_context_type(kbase_device *); 38typedef kbase_context *kbase_create_context_type(kbase_device *);
30typedef void kbase_destroy_context_type(kbase_context *); 39typedef void kbase_destroy_context_type(kbase_context *);
40
41#if MALI_DDK_GATOR_API_VERSION == 1
31typedef void *kbase_va_alloc_type(kbase_context *, u32); 42typedef void *kbase_va_alloc_type(kbase_context *, u32);
32typedef void kbase_va_free_type(kbase_context *, void *); 43typedef void kbase_va_free_type(kbase_context *, void *);
44#elif MALI_DDK_GATOR_API_VERSION == 2
45typedef void *kbase_va_alloc_type(kbase_context *, u32, kbase_hwc_dma_mapping * handle);
46typedef void kbase_va_free_type(kbase_context *, kbase_hwc_dma_mapping * handle);
47#endif
48
33typedef mali_error kbase_instr_hwcnt_enable_type(kbase_context *, kbase_uk_hwcnt_setup *); 49typedef mali_error kbase_instr_hwcnt_enable_type(kbase_context *, kbase_uk_hwcnt_setup *);
34typedef mali_error kbase_instr_hwcnt_disable_type(kbase_context *); 50typedef mali_error kbase_instr_hwcnt_disable_type(kbase_context *);
35typedef mali_error kbase_instr_hwcnt_clear_type(kbase_context *); 51typedef mali_error kbase_instr_hwcnt_clear_type(kbase_context *);
@@ -358,6 +374,11 @@ static const char *const hardware_counter_names[] = {
358/* Memory to dump hardware counters into */ 374/* Memory to dump hardware counters into */
359static void *kernel_dump_buffer; 375static void *kernel_dump_buffer;
360 376
377#if MALI_DDK_GATOR_API_VERSION == 2
378/* DMA state used to manage lifetime of the buffer */
379kbase_hwc_dma_mapping kernel_dump_buffer_handle;
380#endif
381
361/* kbase context and device */ 382/* kbase context and device */
362static kbase_context *kbcontext = NULL; 383static kbase_context *kbcontext = NULL;
363static struct kbase_device *kbdevice = NULL; 384static struct kbase_device *kbdevice = NULL;
@@ -524,9 +545,14 @@ static int start(void)
524 * * number of blocks (always 8 for midgard) 545 * * number of blocks (always 8 for midgard)
525 * * number of counters per block (always 64 for midgard) 546 * * number of counters per block (always 64 for midgard)
526 * * number of bytes per counter (always 4 in midgard) 547 * * number of bytes per counter (always 4 in midgard)
527 * For a Mali-T6xx with a single core group = 1 * 8 * 64 * 4 548 * For a Mali-T6xx with a single core group = 1 * 8 * 64 * 4 = 2048
549 * For a Mali-T6xx with a dual core group = 2 * 8 * 64 * 4 = 4096
528 */ 550 */
529 kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 2048); 551#if MALI_DDK_GATOR_API_VERSION == 1
552 kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 4096);
553#elif MALI_DDK_GATOR_API_VERSION == 2
554 kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 4096, &kernel_dump_buffer_handle);
555#endif
530 if (!kernel_dump_buffer) { 556 if (!kernel_dump_buffer) {
531 pr_debug("gator: Mali-T6xx: error trying to allocate va\n"); 557 pr_debug("gator: Mali-T6xx: error trying to allocate va\n");
532 goto destroy_context; 558 goto destroy_context;
@@ -556,7 +582,11 @@ static int start(void)
556 return 0; 582 return 0;
557 583
558free_buffer: 584free_buffer:
585#if MALI_DDK_GATOR_API_VERSION == 1
559 kbase_va_free_symbol(kbcontext, kernel_dump_buffer); 586 kbase_va_free_symbol(kbcontext, kernel_dump_buffer);
587#elif MALI_DDK_GATOR_API_VERSION == 2
588 kbase_va_free_symbol(kbcontext, &kernel_dump_buffer_handle);
589#endif
560 590
561destroy_context: 591destroy_context:
562 kbase_destroy_context_symbol(kbcontext); 592 kbase_destroy_context_symbol(kbcontext);
@@ -588,7 +618,13 @@ static void stop(void)
588 kbcontext = NULL; 618 kbcontext = NULL;
589 619
590 kbase_instr_hwcnt_disable_symbol(temp_kbcontext); 620 kbase_instr_hwcnt_disable_symbol(temp_kbcontext);
621
622#if MALI_DDK_GATOR_API_VERSION == 1
591 kbase_va_free_symbol(temp_kbcontext, kernel_dump_buffer); 623 kbase_va_free_symbol(temp_kbcontext, kernel_dump_buffer);
624#elif MALI_DDK_GATOR_API_VERSION == 2
625 kbase_va_free_symbol(temp_kbcontext, &kernel_dump_buffer_handle);
626#endif
627
592 kbase_destroy_context_symbol(temp_kbcontext); 628 kbase_destroy_context_symbol(temp_kbcontext);
593 629
594 pr_debug("gator: Mali-T6xx: hardware counters stopped\n"); 630 pr_debug("gator: Mali-T6xx: hardware counters stopped\n");
diff --git a/driver/gator_events_perf_pmu.c b/driver/gator_events_perf_pmu.c
index 34a6bc7..53b2d0a 100644
--- a/driver/gator_events_perf_pmu.c
+++ b/driver/gator_events_perf_pmu.c
@@ -15,23 +15,36 @@
15 15
16extern bool event_based_sampling; 16extern bool event_based_sampling;
17 17
18// Maximum number of per-core counters - currently reserves enough space for two full hardware PMUs for big.LITTLE
18#define CNTMAX 16 19#define CNTMAX 16
19#define CCI_400 4 20#define CCI_400 4
21// Maximum number of uncore counters
20// + 1 for the cci-400 cycles counter 22// + 1 for the cci-400 cycles counter
21#define UCCNT (CCI_400 + 1) 23#define UCCNT (CCI_400 + 1)
22 24
25// A gator_attr is needed for every counter
23struct gator_attr { 26struct gator_attr {
27 // Set once in gator_events_perf_pmu_*_init - the name of the event in the gatorfs
24 char name[40]; 28 char name[40];
29 // Exposed in gatorfs - set by gatord to enable this counter
25 unsigned long enabled; 30 unsigned long enabled;
31 // Set once in gator_events_perf_pmu_*_init - the perf type to use, see perf_type_id in the perf_event.h header file.
26 unsigned long type; 32 unsigned long type;
33 // Exposed in gatorfs - set by gatord to select the event to collect
27 unsigned long event; 34 unsigned long event;
35 // Exposed in gatorfs - set by gatord with the sample period to use and enable EBS for this counter
28 unsigned long count; 36 unsigned long count;
37 // Exposed as read only in gatorfs - set once in __attr_init as the key to use in the APC data
29 unsigned long key; 38 unsigned long key;
30}; 39};
31 40
41// Per-core counter attributes
32static struct gator_attr attrs[CNTMAX]; 42static struct gator_attr attrs[CNTMAX];
43// Number of initialized per-core counters
33static int attr_count; 44static int attr_count;
45// Uncore counter attributes
34static struct gator_attr uc_attrs[UCCNT]; 46static struct gator_attr uc_attrs[UCCNT];
47// Number of initialized uncore counters
35static int uc_attr_count; 48static int uc_attr_count;
36 49
37struct gator_event { 50struct gator_event {
@@ -458,7 +471,7 @@ int gator_events_perf_pmu_init(void)
458 break; 471 break;
459 } 472 }
460 } 473 }
461 // Assume that valid PMUs are contigious 474 // Assume that valid PMUs are contiguous
462 if (IS_ERR(pe)) { 475 if (IS_ERR(pe)) {
463 break; 476 break;
464 } 477 }
@@ -470,6 +483,7 @@ int gator_events_perf_pmu_init(void)
470 found_cpu = true; 483 found_cpu = true;
471 gator_events_perf_pmu_cpu_init(gator_cpu, type); 484 gator_events_perf_pmu_cpu_init(gator_cpu, type);
472 } 485 }
486 // Initialize gator_attrs for dynamic PMUs here
473 } 487 }
474 488
475 perf_event_release_kernel(pe); 489 perf_event_release_kernel(pe);
@@ -483,6 +497,8 @@ int gator_events_perf_pmu_init(void)
483 gator_events_perf_pmu_cpu_init(gator_cpu, PERF_TYPE_RAW); 497 gator_events_perf_pmu_cpu_init(gator_cpu, PERF_TYPE_RAW);
484 } 498 }
485 499
500 // Initialize gator_attrs for non-dynamic PMUs here
501
486 if (attr_count > CNTMAX) { 502 if (attr_count > CNTMAX) {
487 printk(KERN_ERR "gator: Too many perf counters\n"); 503 printk(KERN_ERR "gator: Too many perf counters\n");
488 return -1; 504 return -1;
diff --git a/driver/gator_iks.c b/driver/gator_iks.c
index 6f45c54..ed2c6dd 100644
--- a/driver/gator_iks.c
+++ b/driver/gator_iks.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * Copyright (C) ARM Limited 2010-2013. All rights reserved. 2 * Copyright (C) ARM Limited 2013. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -14,6 +14,7 @@
14#include <asm/smp_plat.h> 14#include <asm/smp_plat.h>
15#include <trace/events/power_cpu_migrate.h> 15#include <trace/events/power_cpu_migrate.h>
16 16
17static bool map_cpuids;
17static int mpidr_cpuids[NR_CPUS]; 18static int mpidr_cpuids[NR_CPUS];
18static int __lcpu_to_pcpu[NR_CPUS]; 19static int __lcpu_to_pcpu[NR_CPUS];
19 20
@@ -40,7 +41,7 @@ static void calc_first_cluster_size(void)
40 ++mpidr_cpuids_count; 41 ++mpidr_cpuids_count;
41 } 42 }
42 43
43 BUG_ON(mpidr_cpuids_count != nr_cpu_ids); 44 map_cpuids = (mpidr_cpuids_count == nr_cpu_ids);
44} 45}
45 46
46static int linearize_mpidr(int mpidr) 47static int linearize_mpidr(int mpidr)
@@ -58,6 +59,10 @@ static int linearize_mpidr(int mpidr)
58int lcpu_to_pcpu(const int lcpu) 59int lcpu_to_pcpu(const int lcpu)
59{ 60{
60 int pcpu; 61 int pcpu;
62
63 if (!map_cpuids)
64 return lcpu;
65
61 BUG_ON(lcpu >= nr_cpu_ids || lcpu < 0); 66 BUG_ON(lcpu >= nr_cpu_ids || lcpu < 0);
62 pcpu = __lcpu_to_pcpu[lcpu]; 67 pcpu = __lcpu_to_pcpu[lcpu];
63 BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0); 68 BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0);
@@ -67,6 +72,10 @@ int lcpu_to_pcpu(const int lcpu)
67int pcpu_to_lcpu(const int pcpu) 72int pcpu_to_lcpu(const int pcpu)
68{ 73{
69 int lcpu; 74 int lcpu;
75
76 if (!map_cpuids)
77 return pcpu;
78
70 BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0); 79 BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0);
71 for (lcpu = 0; lcpu < nr_cpu_ids; ++lcpu) { 80 for (lcpu = 0; lcpu < nr_cpu_ids; ++lcpu) {
72 if (__lcpu_to_pcpu[lcpu] == pcpu) { 81 if (__lcpu_to_pcpu[lcpu] == pcpu) {
@@ -114,6 +123,10 @@ GATOR_DEFINE_PROBE(cpu_migrate_current, TP_PROTO(u64 timestamp, u32 cpu_hwid))
114static int gator_migrate_start(void) 123static int gator_migrate_start(void)
115{ 124{
116 int retval = 0; 125 int retval = 0;
126
127 if (!map_cpuids)
128 return retval;
129
117 if (retval == 0) 130 if (retval == 0)
118 retval = GATOR_REGISTER_TRACE(cpu_migrate_begin); 131 retval = GATOR_REGISTER_TRACE(cpu_migrate_begin);
119 if (retval == 0) 132 if (retval == 0)
@@ -130,6 +143,9 @@ static int gator_migrate_start(void)
130 143
131static void gator_migrate_stop(void) 144static void gator_migrate_stop(void)
132{ 145{
146 if (!map_cpuids)
147 return;
148
133 GATOR_UNREGISTER_TRACE(cpu_migrate_current); 149 GATOR_UNREGISTER_TRACE(cpu_migrate_current);
134 GATOR_UNREGISTER_TRACE(cpu_migrate_finish); 150 GATOR_UNREGISTER_TRACE(cpu_migrate_finish);
135 GATOR_UNREGISTER_TRACE(cpu_migrate_begin); 151 GATOR_UNREGISTER_TRACE(cpu_migrate_begin);
diff --git a/driver/gator_main.c b/driver/gator_main.c
index 88650f6..5eab034 100644
--- a/driver/gator_main.c
+++ b/driver/gator_main.c
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10// This version must match the gator daemon version 10// This version must match the gator daemon version
11static unsigned long gator_protocol_version = 13; 11static unsigned long gator_protocol_version = 14;
12 12
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/cpu.h> 14#include <linux/cpu.h>
@@ -162,8 +162,8 @@ static void gator_commit_buffer(int cpu, int buftype, u64 time);
162static int buffer_bytes_available(int cpu, int buftype); 162static int buffer_bytes_available(int cpu, int buftype);
163static bool buffer_check_space(int cpu, int buftype, int bytes); 163static bool buffer_check_space(int cpu, int buftype, int bytes);
164static int contiguous_space_available(int cpu, int bufytpe); 164static int contiguous_space_available(int cpu, int bufytpe);
165static void gator_buffer_write_packed_int(int cpu, int buftype, unsigned int x); 165static void gator_buffer_write_packed_int(int cpu, int buftype, int x);
166static void gator_buffer_write_packed_int64(int cpu, int buftype, unsigned long long x); 166static void gator_buffer_write_packed_int64(int cpu, int buftype, long long x);
167static void gator_buffer_write_bytes(int cpu, int buftype, const char *x, int len); 167static void gator_buffer_write_bytes(int cpu, int buftype, const char *x, int len);
168static void gator_buffer_write_string(int cpu, int buftype, const char *x); 168static void gator_buffer_write_string(int cpu, int buftype, const char *x);
169static void gator_add_trace(int cpu, unsigned long address); 169static void gator_add_trace(int cpu, unsigned long address);
@@ -389,6 +389,8 @@ static bool buffer_commit_ready(int *cpu, int *buftype)
389 return true; 389 return true;
390 } 390 }
391 } 391 }
392 *cpu = -1;
393 *buftype = -1;
392 return false; 394 return false;
393} 395}
394 396
@@ -476,14 +478,14 @@ static void gator_commit_buffer(int cpu, int buftype, u64 time)
476 if (length < 0) { 478 if (length < 0) {
477 length += gator_buffer_size[buftype]; 479 length += gator_buffer_size[buftype];
478 } 480 }
479 length = length - type_length - sizeof(int); 481 length = length - type_length - sizeof(s32);
480 482
481 if (length <= FRAME_HEADER_SIZE) { 483 if (length <= FRAME_HEADER_SIZE) {
482 // Nothing to write, only the frame header is present 484 // Nothing to write, only the frame header is present
483 return; 485 return;
484 } 486 }
485 487
486 for (byte = 0; byte < sizeof(int); byte++) { 488 for (byte = 0; byte < sizeof(s32); byte++) {
487 per_cpu(gator_buffer, cpu)[buftype][(commit + type_length + byte) & gator_buffer_mask[buftype]] = (length >> byte * 8) & 0xFF; 489 per_cpu(gator_buffer, cpu)[buftype][(commit + type_length + byte) & gator_buffer_mask[buftype]] = (length >> byte * 8) & 0xFF;
488 } 490 }
489 491
@@ -595,7 +597,7 @@ static void gator_timer_offline(void *migrate)
595 597
596 // Offline any events and output counters 598 // Offline any events and output counters
597 time = gator_get_time(); 599 time = gator_get_time();
598 if (marshal_event_header()) { 600 if (marshal_event_header(time)) {
599 list_for_each_entry(gi, &gator_events, list) { 601 list_for_each_entry(gi, &gator_events, list) {
600 if (gi->offline) { 602 if (gi->offline) {
601 len = gi->offline(&buffer, migrate); 603 len = gi->offline(&buffer, migrate);
@@ -644,11 +646,13 @@ static void gator_timer_online(void *migrate)
644 struct gator_interface *gi; 646 struct gator_interface *gi;
645 int len, cpu = get_physical_cpu(); 647 int len, cpu = get_physical_cpu();
646 int *buffer; 648 int *buffer;
649 u64 time;
647 650
648 gator_trace_power_online(); 651 gator_trace_power_online();
649 652
650 // online any events and output counters 653 // online any events and output counters
651 if (marshal_event_header()) { 654 time = gator_get_time();
655 if (marshal_event_header(time)) {
652 list_for_each_entry(gi, &gator_events, list) { 656 list_for_each_entry(gi, &gator_events, list) {
653 if (gi->online) { 657 if (gi->online) {
654 len = gi->online(&buffer, migrate); 658 len = gi->online(&buffer, migrate);
@@ -656,7 +660,7 @@ static void gator_timer_online(void *migrate)
656 } 660 }
657 } 661 }
658 // Only check after writing all counters so that time and corresponding counters appear in the same frame 662 // Only check after writing all counters so that time and corresponding counters appear in the same frame
659 buffer_check(cpu, BLOCK_COUNTER_BUF, gator_get_time()); 663 buffer_check(cpu, BLOCK_COUNTER_BUF, time);
660 } 664 }
661 665
662 if (!migrate) { 666 if (!migrate) {
@@ -745,8 +749,6 @@ static u64 gator_get_time(void)
745 if (!printed_monotonic_warning && delta > 500000) { 749 if (!printed_monotonic_warning && delta > 500000) {
746 printk(KERN_ERR "%s: getrawmonotonic is not monotonic cpu: %i delta: %lli\nSkew in Streamline data may be present at the fine zoom levels\n", __FUNCTION__, cpu, delta); 750 printk(KERN_ERR "%s: getrawmonotonic is not monotonic cpu: %i delta: %lli\nSkew in Streamline data may be present at the fine zoom levels\n", __FUNCTION__, cpu, delta);
747 printed_monotonic_warning = true; 751 printed_monotonic_warning = true;
748 } else {
749 pr_debug("%s: getrawmonotonic is not monotonic cpu: %i delta: %lli\n", __FUNCTION__, cpu, delta);
750 } 752 }
751 timestamp = prev_timestamp; 753 timestamp = prev_timestamp;
752 } 754 }
@@ -894,6 +896,7 @@ static int gator_init(void)
894 if (gator_events_list[i]) 896 if (gator_events_list[i])
895 gator_events_list[i](); 897 gator_events_list[i]();
896 898
899 gator_trace_sched_init();
897 gator_trace_power_init(); 900 gator_trace_power_init();
898 901
899 return 0; 902 return 0;
@@ -1227,83 +1230,81 @@ static int userspace_buffer_release(struct inode *inode, struct file *file)
1227 return 0; 1230 return 0;
1228} 1231}
1229 1232
1230static ssize_t userspace_buffer_read(struct file *file, char __user *buf, 1233static ssize_t userspace_buffer_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
1231 size_t count, loff_t *offset)
1232{ 1234{
1233 int retval = -EINVAL; 1235 int commit, length1, length2, read;
1234 int commit = 0, length1, length2, read;
1235 char *buffer1; 1236 char *buffer1;
1236 char *buffer2 = NULL; 1237 char *buffer2;
1237 int cpu, buftype; 1238 int cpu, buftype;
1239 int written = 0;
1238 1240
1239 /* do not handle partial reads */ 1241 // ensure there is enough space for a whole frame
1240 if (count != userspace_buffer_size || *offset) 1242 if (count < userspace_buffer_size || *offset) {
1241 return -EINVAL; 1243 return -EINVAL;
1244 }
1242 1245
1243 // sleep until the condition is true or a signal is received 1246 // sleep until the condition is true or a signal is received
1244 // the condition is checked each time gator_buffer_wait is woken up 1247 // the condition is checked each time gator_buffer_wait is woken up
1245 buftype = cpu = -1;
1246 wait_event_interruptible(gator_buffer_wait, buffer_commit_ready(&cpu, &buftype) || !gator_started); 1248 wait_event_interruptible(gator_buffer_wait, buffer_commit_ready(&cpu, &buftype) || !gator_started);
1247 1249
1248 if (signal_pending(current)) 1250 if (signal_pending(current)) {
1249 return -EINTR; 1251 return -EINTR;
1250 1252 }
1251 length2 = 0;
1252 retval = -EFAULT;
1253
1254 mutex_lock(&gator_buffer_mutex);
1255 1253
1256 if (buftype == -1 || cpu == -1) { 1254 if (buftype == -1 || cpu == -1) {
1257 retval = 0; 1255 return 0;
1258 goto out;
1259 } 1256 }
1260 1257
1261 read = per_cpu(gator_buffer_read, cpu)[buftype]; 1258 mutex_lock(&gator_buffer_mutex);
1262 commit = per_cpu(gator_buffer_commit, cpu)[buftype];
1263 1259
1264 /* May happen if the buffer is freed during pending reads. */ 1260 do {
1265 if (!per_cpu(gator_buffer, cpu)[buftype]) { 1261 read = per_cpu(gator_buffer_read, cpu)[buftype];
1266 retval = -EFAULT; 1262 commit