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authorJon Medhurst2012-05-10 08:15:56 -0500
committerJon Medhurst2012-05-16 08:22:59 -0500
commitd18974d3f05535eda819f2d0b92a9d49719b0f26 (patch)
treeee0d02ac702b3802b0f002a0f8edf2171d7e58c3 /daemon/events-ARM11.xml
parent970700feed8c3523b06476ae340bf46f6d262550 (diff)
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gator: Version 5.10
New gator release (build 1385) for ARM DS-5 v5.10 Signed-off-by: Jon Medhurst <tixy@linaro.org>
Diffstat (limited to 'daemon/events-ARM11.xml')
-rw-r--r--daemon/events-ARM11.xml8
1 files changed, 4 insertions, 4 deletions
diff --git a/daemon/events-ARM11.xml b/daemon/events-ARM11.xml
index 5742271..c9d188f 100644
--- a/daemon/events-ARM11.xml
+++ b/daemon/events-ARM11.xml
@@ -4,18 +4,18 @@
4 <counter name="ARM_ARM11_cnt2"/> 4 <counter name="ARM_ARM11_cnt2"/>
5 </counter_set> 5 </counter_set>
6 <category name="ARM11" counter_set="ARM_ARM11_cntX" per_cpu="yes"> 6 <category name="ARM11" counter_set="ARM_ARM11_cntX" per_cpu="yes">
7 <event counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/> 7 <event counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" alias="ClockCycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
8 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/> 8 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
9 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/> 9 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
10 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/> 10 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
11 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/> 11 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
12 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/> 12 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
13 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/> 13 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/>
14 <event event="0x06" title="Branch" name="Mispredicted" description="Branch mis-predicted"/> 14 <event event="0x06" title="Branch" name="Mispredicted" alias="BranchMispredicted" description="Branch mis-predicted"/>
15 <event event="0x07" title="Instruction" name="Executed" description="Instructions executed"/> 15 <event event="0x07" title="Instruction" name="Executed" alias="InstructionsExecuted" description="Instructions executed"/>
16 <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/> 16 <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/>
17 <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/> 17 <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/>
18 <event event="0x0b" title="Cache" name="Data miss" description="Data cache miss, not including Cache Operations"/> 18 <event event="0x0b" title="Cache" name="Data miss" alias="L1Miss" description="Data cache miss, not including Cache Operations"/>
19 <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/> 19 <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/>
20 <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/> 20 <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/>
21 <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/> 21 <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/>