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-rw-r--r--daemon/Android.mk6
-rw-r--r--daemon/Buffer.cpp36
-rw-r--r--daemon/Buffer.h11
-rw-r--r--daemon/CapturedXML.cpp11
-rw-r--r--daemon/CapturedXML.h2
-rw-r--r--daemon/Child.cpp45
-rw-r--r--daemon/Child.h2
-rw-r--r--daemon/ConfigurationXML.cpp10
-rw-r--r--daemon/Counter.h4
-rw-r--r--daemon/DriverSource.cpp53
-rw-r--r--daemon/DriverSource.h5
-rw-r--r--daemon/EventsXML.cpp16
-rw-r--r--daemon/EventsXML.h5
-rw-r--r--daemon/ExternalSource.cpp177
-rw-r--r--daemon/ExternalSource.h11
-rw-r--r--daemon/Fifo.h2
-rw-r--r--daemon/Hwmon.cpp16
-rw-r--r--daemon/KMod.cpp11
-rw-r--r--daemon/LocalCapture.h2
-rw-r--r--daemon/Logging.h2
-rw-r--r--daemon/Makefile8
-rw-r--r--daemon/Makefile_aarch649
-rw-r--r--daemon/Monitor.cpp11
-rw-r--r--daemon/Monitor.h1
-rw-r--r--daemon/OlySocket.cpp77
-rw-r--r--daemon/OlySocket.h14
-rw-r--r--daemon/PerfDriver.cpp92
-rw-r--r--daemon/PerfDriver.h6
-rw-r--r--daemon/PerfGroup.cpp28
-rw-r--r--daemon/PerfGroup.h2
-rw-r--r--daemon/PerfSource.cpp14
-rw-r--r--daemon/Proc.cpp106
-rw-r--r--daemon/Proc.h2
-rw-r--r--daemon/Sender.h2
-rw-r--r--daemon/SessionData.cpp55
-rw-r--r--daemon/SessionData.h17
-rw-r--r--daemon/SessionXML.cpp8
-rw-r--r--daemon/StreamlineSetup.cpp2
-rw-r--r--daemon/StreamlineSetup.h4
-rw-r--r--daemon/UEvent.cpp6
-rw-r--r--daemon/UserSpaceSource.cpp14
-rw-r--r--daemon/UserSpaceSource.h2
-rw-r--r--daemon/common.mk16
-rw-r--r--daemon/defaults.xml5
-rw-r--r--daemon/defaults_xml.h306
-rw-r--r--daemon/escapebin0 -> 8900 bytes
-rw-r--r--daemon/escape.c2
-rw-r--r--daemon/events-CCI-400.xml21
-rw-r--r--daemon/events-CCN-504.xml9
-rw-r--r--daemon/events-Cortex-A53.xml84
-rw-r--r--daemon/events-Cortex-A57.xml84
-rw-r--r--daemon/events-L2C-310.xml30
-rw-r--r--daemon/events-Linux.xml5
-rw-r--r--daemon/events-Mali-4xx.xml126
-rw-r--r--daemon/events-Mali-T6xx.xml26
-rw-r--r--daemon/events-Mali-T6xx_hw.xml33
-rw-r--r--daemon/events.xml1670
-rw-r--r--daemon/events_xml.h16317
-rw-r--r--[l---------]daemon/k/perf_event.h793
-rw-r--r--daemon/main.cpp260
-rw-r--r--driver/Makefile15
-rw-r--r--driver/gator.h6
-rw-r--r--driver/gator_backtrace.c2
-rw-r--r--driver/gator_buffer.c6
-rw-r--r--driver/gator_events_armv7.c4
-rw-r--r--driver/gator_events_block.c12
-rw-r--r--driver/gator_events_mali_4xx.c144
-rw-r--r--driver/gator_events_mali_common.c36
-rw-r--r--driver/gator_events_mali_common.h20
-rw-r--r--driver/gator_events_mali_t6xx.c5
-rw-r--r--driver/gator_events_mali_t6xx_hw.c183
-rw-r--r--driver/gator_events_mmapped.c26
-rw-r--r--driver/gator_events_perf_pmu.c6
-rw-r--r--driver/gator_events_scorpion.c4
-rw-r--r--driver/gator_iks.c2
-rw-r--r--driver/gator_main.c77
-rw-r--r--driver/gator_marshaling.c101
-rw-r--r--driver/gator_trace_gpu.c142
-rw-r--r--driver/gator_trace_power.c4
-rw-r--r--driver/gator_trace_sched.c85
-rw-r--r--driver/mali_t6xx.mk4
81 files changed, 20133 insertions, 1445 deletions
diff --git a/daemon/Android.mk b/daemon/Android.mk
index 44c069c..045d028 100644
--- a/daemon/Android.mk
+++ b/daemon/Android.mk
@@ -3,7 +3,7 @@ include $(CLEAR_VARS)
3 3
4XML_H := $(shell cd $(LOCAL_PATH) && make events_xml.h defaults_xml.h) 4XML_H := $(shell cd $(LOCAL_PATH) && make events_xml.h defaults_xml.h)
5 5
6LOCAL_CFLAGS += -Wall -O3 -mthumb-interwork -fno-exceptions -pthread -DETCDIR=\"/etc\" -Ilibsensors 6LOCAL_CFLAGS += -Wall -O3 -mthumb-interwork -fno-exceptions -DETCDIR=\"/etc\" -Ilibsensors
7 7
8LOCAL_SRC_FILES := \ 8LOCAL_SRC_FILES := \
9 Buffer.cpp \ 9 Buffer.cpp \
@@ -15,14 +15,12 @@ LOCAL_SRC_FILES := \
15 DynBuf.cpp \ 15 DynBuf.cpp \
16 EventsXML.cpp \ 16 EventsXML.cpp \
17 ExternalSource.cpp \ 17 ExternalSource.cpp \
18 FSDriver.cpp \
19 Fifo.cpp \ 18 Fifo.cpp \
20 Hwmon.cpp \ 19 Hwmon.cpp \
21 KMod.cpp \ 20 KMod.cpp \
22 LocalCapture.cpp \ 21 LocalCapture.cpp \
23 Logging.cpp \ 22 Logging.cpp \
24 main.cpp \ 23 main.cpp \
25 MaliVideoDriver.cpp \
26 Monitor.cpp \ 24 Monitor.cpp \
27 OlySocket.cpp \ 25 OlySocket.cpp \
28 OlyUtility.cpp \ 26 OlyUtility.cpp \
@@ -57,7 +55,7 @@ LOCAL_SRC_FILES := \
57 mxml/mxml-set.c \ 55 mxml/mxml-set.c \
58 mxml/mxml-string.c 56 mxml/mxml-string.c
59 57
60LOCAL_C_INCLUDES := $(LOCAL_PATH) 58LOCAL_C_INCLUDES := $(LOCAL_PATH)
61 59
62LOCAL_MODULE := gatord 60LOCAL_MODULE := gatord
63LOCAL_MODULE_TAGS := optional 61LOCAL_MODULE_TAGS := optional
diff --git a/daemon/Buffer.cpp b/daemon/Buffer.cpp
index dd19f7f..93557da 100644
--- a/daemon/Buffer.cpp
+++ b/daemon/Buffer.cpp
@@ -15,12 +15,11 @@
15#define mask (mSize - 1) 15#define mask (mSize - 1)
16 16
17enum { 17enum {
18 CODE_PEA = 1, 18 CODE_PEA = 1,
19 CODE_KEYS = 2, 19 CODE_KEYS = 2,
20 CODE_FORMAT = 3, 20 CODE_FORMAT = 3,
21 CODE_MAPS = 4, 21 CODE_MAPS = 4,
22 CODE_COMM = 5, 22 CODE_COMM = 5,
23 CODE_KEYS_OLD = 6,
24}; 23};
25 24
26// Summary Frame Messages 25// Summary Frame Messages
@@ -168,7 +167,7 @@ void Buffer::check(const uint64_t time) {
168 } 167 }
169} 168}
170 169
171void Buffer::packInt(char *const buf, const int size, int &writePos, int32_t x) { 170void Buffer::packInt(int32_t x) {
172 int packedBytes = 0; 171 int packedBytes = 0;
173 int more = true; 172 int more = true;
174 while (more) { 173 while (more) {
@@ -182,15 +181,11 @@ void Buffer::packInt(char *const buf, const int size, int &writePos, int32_t x)
182 b |= 0x80; 181 b |= 0x80;
183 } 182 }
184 183
185 buf[(writePos + packedBytes) & /*mask*/(size - 1)] = b; 184 mBuf[(mWritePos + packedBytes) & mask] = b;
186 packedBytes++; 185 packedBytes++;
187 } 186 }
188 187
189 writePos = (writePos + packedBytes) & /*mask*/(size - 1); 188 mWritePos = (mWritePos + packedBytes) & mask;
190}
191
192void Buffer::packInt(int32_t x) {
193 packInt(mBuf, mSize, mWritePos, x);
194} 189}
195 190
196void Buffer::packInt64(int64_t x) { 191void Buffer::packInt64(int64_t x) {
@@ -325,21 +320,6 @@ void Buffer::keys(const int count, const __u64 *const ids, const int *const keys
325 check(1); 320 check(1);
326} 321}
327 322
328void Buffer::keysOld(const int keyCount, const int *const keys, const int bytes, const char *const buf) {
329 if (checkSpace((2 + keyCount) * MAXSIZE_PACK32 + bytes)) {
330 packInt(CODE_KEYS_OLD);
331 packInt(keyCount);
332 for (int i = 0; i < keyCount; ++i) {
333 packInt(keys[i]);
334 }
335 writeBytes(buf, bytes);
336 } else {
337 logg->logError(__FILE__, __LINE__, "Ran out of buffer space for perf attrs");
338 handleException();
339 }
340 check(1);
341}
342
343void Buffer::format(const int length, const char *const format) { 323void Buffer::format(const int length, const char *const format) {
344 if (checkSpace(MAXSIZE_PACK32 + length + 1)) { 324 if (checkSpace(MAXSIZE_PACK32 + length + 1)) {
345 packInt(CODE_FORMAT); 325 packInt(CODE_FORMAT);
diff --git a/daemon/Buffer.h b/daemon/Buffer.h
index 2de1b97..5023777 100644
--- a/daemon/Buffer.h
+++ b/daemon/Buffer.h
@@ -54,7 +54,6 @@ public:
54 // Perf Attrs messages 54 // Perf Attrs messages
55 void pea(const struct perf_event_attr *const pea, int key); 55 void pea(const struct perf_event_attr *const pea, int key);
56 void keys(const int count, const __u64 *const ids, const int *const keys); 56 void keys(const int count, const __u64 *const ids, const int *const keys);
57 void keysOld(const int keyCount, const int *const keys, const int bytes, const char *const buf);
58 void format(const int length, const char *const format); 57 void format(const int length, const char *const format);
59 void maps(const int pid, const int tid, const char *const maps); 58 void maps(const int pid, const int tid, const char *const maps);
60 void comm(const int pid, const int tid, const char *const image, const char *const comm); 59 void comm(const int pid, const int tid, const char *const image, const char *const comm);
@@ -65,11 +64,6 @@ public:
65 // Prefer a new member to using these functions if possible 64 // Prefer a new member to using these functions if possible
66 char *getWritePos() { return mBuf + mWritePos; } 65 char *getWritePos() { return mBuf + mWritePos; }
67 void advanceWrite(int bytes) { mWritePos = (mWritePos + bytes) & /*mask*/(mSize - 1); } 66 void advanceWrite(int bytes) { mWritePos = (mWritePos + bytes) & /*mask*/(mSize - 1); }
68 static void packInt(char *const buf, const int size, int &writePos, int32_t x);
69 void packInt(int32_t x);
70 void packInt64(int64_t x);
71 void writeBytes(const void *const data, size_t count);
72 void writeString(const char *const str);
73 67
74 static void writeLEInt(unsigned char *buf, int v) { 68 static void writeLEInt(unsigned char *buf, int v) {
75 buf[0] = (v >> 0) & 0xFF; 69 buf[0] = (v >> 0) & 0xFF;
@@ -82,6 +76,11 @@ private:
82 bool commitReady() const; 76 bool commitReady() const;
83 bool checkSpace(int bytes); 77 bool checkSpace(int bytes);
84 78
79 void packInt(int32_t x);
80 void packInt64(int64_t x);
81 void writeBytes(const void *const data, size_t count);
82 void writeString(const char *const str);
83
85 const int32_t mCore; 84 const int32_t mCore;
86 const int32_t mBufType; 85 const int32_t mBufType;
87 const int mSize; 86 const int mSize;
diff --git a/daemon/CapturedXML.cpp b/daemon/CapturedXML.cpp
index 4a11415..cf79b72 100644
--- a/daemon/CapturedXML.cpp
+++ b/daemon/CapturedXML.cpp
@@ -33,7 +33,7 @@ mxml_node_t* CapturedXML::getTree(bool includeTime) {
33 captured = mxmlNewElement(xml, "captured"); 33 captured = mxmlNewElement(xml, "captured");
34 mxmlElementSetAttr(captured, "version", "1"); 34 mxmlElementSetAttr(captured, "version", "1");
35 if (gSessionData->perf.isSetup()) { 35 if (gSessionData->perf.isSetup()) {
36 mxmlElementSetAttr(captured, "type", "Perf"); 36 mxmlElementSetAttr(captured, "type", "Perf");
37 } 37 }
38 mxmlElementSetAttrf(captured, "protocol", "%d", PROTOCOL_VERSION); 38 mxmlElementSetAttrf(captured, "protocol", "%d", PROTOCOL_VERSION);
39 if (includeTime) { // Send the following only after the capture is complete 39 if (includeTime) { // Send the following only after the capture is complete
@@ -66,15 +66,10 @@ mxml_node_t* CapturedXML::getTree(bool includeTime) {
66 mxml_node_t *const node = mxmlNewElement(counters, "counter"); 66 mxml_node_t *const node = mxmlNewElement(counters, "counter");
67 mxmlElementSetAttrf(node, "key", "0x%x", counter.getKey()); 67 mxmlElementSetAttrf(node, "key", "0x%x", counter.getKey());
68 mxmlElementSetAttr(node, "type", counter.getType()); 68 mxmlElementSetAttr(node, "type", counter.getType());
69 if (counter.getEvent() != -1) { 69 mxmlElementSetAttrf(node, "event", "0x%x", counter.getEvent());
70 mxmlElementSetAttrf(node, "event", "0x%x", counter.getEvent());
71 }
72 if (counter.getCount() > 0) { 70 if (counter.getCount() > 0) {
73 mxmlElementSetAttrf(node, "count", "%d", counter.getCount()); 71 mxmlElementSetAttrf(node, "count", "%d", counter.getCount());
74 } 72 }
75 if (counter.getCores() > 0) {
76 mxmlElementSetAttrf(node, "cores", "%d", counter.getCores());
77 }
78 } 73 }
79 } 74 }
80 75
@@ -94,7 +89,7 @@ void CapturedXML::write(char* path) {
94 89
95 // Set full path 90 // Set full path
96 snprintf(file, PATH_MAX, "%s/captured.xml", path); 91 snprintf(file, PATH_MAX, "%s/captured.xml", path);
97 92
98 char* xml = getXML(true); 93 char* xml = getXML(true);
99 if (util->writeToDisk(file, xml) < 0) { 94 if (util->writeToDisk(file, xml) < 0) {
100 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file); 95 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
diff --git a/daemon/CapturedXML.h b/daemon/CapturedXML.h
index ed08c44..efc1e52 100644
--- a/daemon/CapturedXML.h
+++ b/daemon/CapturedXML.h
@@ -23,4 +23,4 @@ private:
23 23
24const char * mxmlWhitespaceCB(mxml_node_t *node, int where); 24const char * mxmlWhitespaceCB(mxml_node_t *node, int where);
25 25
26#endif //__CAPTURED_XML_H__ 26#endif //__CAPTURED_XML_H__
diff --git a/daemon/Child.cpp b/daemon/Child.cpp
index 1901ecc..ca33561 100644
--- a/daemon/Child.cpp
+++ b/daemon/Child.cpp
@@ -26,13 +26,13 @@
26#include "Driver.h" 26#include "Driver.h"
27#include "PerfSource.h" 27#include "PerfSource.h"
28#include "DriverSource.h" 28#include "DriverSource.h"
29#include "ExternalSource.h"
30#include "UserSpaceSource.h" 29#include "UserSpaceSource.h"
30#include "ExternalSource.h"
31 31
32static sem_t haltPipeline, senderThreadStarted, startProfile, senderSem; // Shared by Child and spawned threads 32static sem_t haltPipeline, senderThreadStarted, startProfile, senderSem; // Shared by Child and spawned threads
33static Source *primarySource = NULL; 33static Source *primarySource = NULL;
34static Source *externalSource = NULL;
35static Source *userSpaceSource = NULL; 34static Source *userSpaceSource = NULL;
35static Source *externalSource = NULL;
36static Sender* sender = NULL; // Shared by Child.cpp and spawned threads 36static Sender* sender = NULL; // Shared by Child.cpp and spawned threads
37Child* child = NULL; // shared by Child.cpp and main.cpp 37Child* child = NULL; // shared by Child.cpp and main.cpp
38 38
@@ -147,16 +147,16 @@ static void *senderThread(void *) {
147 prctl(PR_SET_NAME, (unsigned long)&"gatord-sender", 0, 0, 0); 147 prctl(PR_SET_NAME, (unsigned long)&"gatord-sender", 0, 0, 0);
148 sem_wait(&haltPipeline); 148 sem_wait(&haltPipeline);
149 149
150 while (!primarySource->isDone() || 150 while (!primarySource->isDone() || (userSpaceSource != NULL && !userSpaceSource->isDone()) || (externalSource != NULL && !externalSource->isDone())) {
151 !externalSource->isDone() ||
152 (userSpaceSource != NULL && !userSpaceSource->isDone())) {
153 sem_wait(&senderSem); 151 sem_wait(&senderSem);
154 152
155 primarySource->write(sender); 153 primarySource->write(sender);
156 externalSource->write(sender);
157 if (userSpaceSource != NULL) { 154 if (userSpaceSource != NULL) {
158 userSpaceSource->write(sender); 155 userSpaceSource->write(sender);
159 } 156 }
157 if (externalSource != NULL) {
158 externalSource->write(sender);
159 }
160 } 160 }
161 161
162 // write end-of-capture sequence 162 // write end-of-capture sequence
@@ -202,10 +202,6 @@ void Child::initialization() {
202void Child::endSession() { 202void Child::endSession() {
203 gSessionData->mSessionIsActive = false; 203 gSessionData->mSessionIsActive = false;
204 primarySource->interrupt(); 204 primarySource->interrupt();
205 externalSource->interrupt();
206 if (userSpaceSource != NULL) {
207 userSpaceSource->interrupt();
208 }
209 sem_post(&haltPipeline); 205 sem_post(&haltPipeline);
210} 206}
211 207
@@ -231,9 +227,9 @@ void Child::run() {
231 227
232 // Set up the driver; must be done after gSessionData->mPerfCounterType[] is populated 228 // Set up the driver; must be done after gSessionData->mPerfCounterType[] is populated
233 if (!gSessionData->perf.isSetup()) { 229 if (!gSessionData->perf.isSetup()) {
234 primarySource = new DriverSource(&senderSem, &startProfile); 230 primarySource = new DriverSource(&senderSem, &startProfile);
235 } else { 231 } else {
236 primarySource = new PerfSource(&senderSem, &startProfile); 232 primarySource = new PerfSource(&senderSem, &startProfile);
237 } 233 }
238 234
239 // Initialize all drivers 235 // Initialize all drivers
@@ -284,18 +280,11 @@ void Child::run() {
284 thread_creation_success = false; 280 thread_creation_success = false;
285 } else if (socket && pthread_create(&stopThreadID, NULL, stopThread, NULL)) { 281 } else if (socket && pthread_create(&stopThreadID, NULL, stopThread, NULL)) {
286 thread_creation_success = false; 282 thread_creation_success = false;
287 } else if (pthread_create(&senderThreadID, NULL, senderThread, NULL)) { 283 } else if (pthread_create(&senderThreadID, NULL, senderThread, NULL)){
288 thread_creation_success = false; 284 thread_creation_success = false;
289 } 285 }
290 286
291 externalSource = new ExternalSource(&senderSem); 287 if (gSessionData->hwmon.countersEnabled()) {
292 if (!externalSource->prepare()) {
293 logg->logError(__FILE__, __LINE__, "Unable to prepare for capture");
294 handleException();
295 }
296 externalSource->start();
297
298 if (gSessionData->hwmon.countersEnabled() || gSessionData->fsDriver.countersEnabled()) {
299 userSpaceSource = new UserSpaceSource(&senderSem); 288 userSpaceSource = new UserSpaceSource(&senderSem);
300 if (!userSpaceSource->prepare()) { 289 if (!userSpaceSource->prepare()) {
301 logg->logError(__FILE__, __LINE__, "Unable to prepare for capture"); 290 logg->logError(__FILE__, __LINE__, "Unable to prepare for capture");
@@ -303,6 +292,14 @@ void Child::run() {
303 } 292 }
304 userSpaceSource->start(); 293 userSpaceSource->start();
305 } 294 }
295 if (access("/tmp/gator", F_OK) == 0) {
296 externalSource = new ExternalSource(&senderSem);
297 if (!externalSource->prepare()) {
298 logg->logError(__FILE__, __LINE__, "Unable to prepare for capture");
299 handleException();
300 }
301 externalSource->start();
302 }
306 303
307 if (!thread_creation_success) { 304 if (!thread_creation_success) {
308 logg->logError(__FILE__, __LINE__, "Failed to create gator threads"); 305 logg->logError(__FILE__, __LINE__, "Failed to create gator threads");
@@ -315,10 +312,12 @@ void Child::run() {
315 // Start profiling 312 // Start profiling
316 primarySource->run(); 313 primarySource->run();
317 314
315 if (externalSource != NULL) {
316 externalSource->join();
317 }
318 if (userSpaceSource != NULL) { 318 if (userSpaceSource != NULL) {
319 userSpaceSource->join(); 319 userSpaceSource->join();
320 } 320 }
321 externalSource->join();
322 321
323 // Wait for the other threads to exit 322 // Wait for the other threads to exit
324 pthread_join(senderThreadID, NULL); 323 pthread_join(senderThreadID, NULL);
@@ -338,8 +337,8 @@ void Child::run() {
338 337
339 logg->logMessage("Profiling ended."); 338 logg->logMessage("Profiling ended.");
340 339
341 delete userSpaceSource;
342 delete externalSource; 340 delete externalSource;
341 delete userSpaceSource;
343 delete primarySource; 342 delete primarySource;
344 delete sender; 343 delete sender;
345 delete localCapture; 344 delete localCapture;
diff --git a/daemon/Child.h b/daemon/Child.h
index a306a77..9e206d7 100644
--- a/daemon/Child.h
+++ b/daemon/Child.h
@@ -30,4 +30,4 @@ private:
30 Child &operator=(const Child &); 30 Child &operator=(const Child &);
31}; 31};
32 32
33#endif //__CHILD_H__ 33#endif //__CHILD_H__
diff --git a/daemon/ConfigurationXML.cpp b/daemon/ConfigurationXML.cpp
index 6590dd3..fd479f2 100644
--- a/daemon/ConfigurationXML.cpp
+++ b/daemon/ConfigurationXML.cpp
@@ -21,13 +21,12 @@ static const char* ATTR_COUNTER = "counter";
21static const char* ATTR_REVISION = "revision"; 21static const char* ATTR_REVISION = "revision";
22static const char* ATTR_EVENT = "event"; 22static const char* ATTR_EVENT = "event";
23static const char* ATTR_COUNT = "count"; 23static const char* ATTR_COUNT = "count";
24static const char* ATTR_CORES = "cores";
25 24
26ConfigurationXML::ConfigurationXML() { 25ConfigurationXML::ConfigurationXML() {
27 const char * configuration_xml; 26 const char * configuration_xml;
28 unsigned int configuration_xml_len; 27 unsigned int configuration_xml_len;
29 getDefaultConfigurationXml(configuration_xml, configuration_xml_len); 28 getDefaultConfigurationXml(configuration_xml, configuration_xml_len);
30 29
31 char path[PATH_MAX]; 30 char path[PATH_MAX];
32 31
33 getPath(path); 32 getPath(path);
@@ -54,7 +53,7 @@ ConfigurationXML::ConfigurationXML() {
54 53
55 break; 54 break;
56 } 55 }
57 56
58 validate(); 57 validate();
59} 58}
60 59
@@ -83,7 +82,7 @@ int ConfigurationXML::parse(const char* configurationXML) {
83 node = mxmlGetFirstChild(tree); 82 node = mxmlGetFirstChild(tree);
84 while (node && mxmlGetType(node) != MXML_ELEMENT) 83 while (node && mxmlGetType(node) != MXML_ELEMENT)
85 node = mxmlWalkNext(node, tree, MXML_NO_DESCEND); 84 node = mxmlWalkNext(node, tree, MXML_NO_DESCEND);
86 85
87 ret = configurationsTag(node); 86 ret = configurationsTag(node);
88 87
89 node = mxmlGetFirstChild(node); 88 node = mxmlGetFirstChild(node);
@@ -128,7 +127,7 @@ void ConfigurationXML::validate(void) {
128#define CONFIGURATION_REVISION 3 127#define CONFIGURATION_REVISION 3
129int ConfigurationXML::configurationsTag(mxml_node_t *node) { 128int ConfigurationXML::configurationsTag(mxml_node_t *node) {
130 const char* revision_string; 129 const char* revision_string;
131 130
132 revision_string = mxmlElementGetAttr(node, ATTR_REVISION); 131 revision_string = mxmlElementGetAttr(node, ATTR_REVISION);
133 if (!revision_string) { 132 if (!revision_string) {
134 return 1; //revision issue; 133 return 1; //revision issue;
@@ -159,7 +158,6 @@ void ConfigurationXML::configurationTag(mxml_node_t *node) {
159 if (mxmlElementGetAttr(node, ATTR_COUNTER)) counter.setType(mxmlElementGetAttr(node, ATTR_COUNTER)); 158 if (mxmlElementGetAttr(node, ATTR_COUNTER)) counter.setType(mxmlElementGetAttr(node, ATTR_COUNTER));
160 if (mxmlElementGetAttr(node, ATTR_EVENT)) counter.setEvent(strtol(mxmlElementGetAttr(node, ATTR_EVENT), NULL, 16)); 159 if (mxmlElementGetAttr(node, ATTR_EVENT)) counter.setEvent(strtol(mxmlElementGetAttr(node, ATTR_EVENT), NULL, 16));
161 if (mxmlElementGetAttr(node, ATTR_COUNT)) counter.setCount(strtol(mxmlElementGetAttr(node, ATTR_COUNT), NULL, 10)); 160 if (mxmlElementGetAttr(node, ATTR_COUNT)) counter.setCount(strtol(mxmlElementGetAttr(node, ATTR_COUNT), NULL, 10));
162 if (mxmlElementGetAttr(node, ATTR_CORES)) counter.setCores(strtol(mxmlElementGetAttr(node, ATTR_CORES), NULL, 10));
163 if (counter.getCount() > 0) { 161 if (counter.getCount() > 0) {
164 gSessionData->mIsEBS = true; 162 gSessionData->mIsEBS = true;
165 } 163 }
diff --git a/daemon/Counter.h b/daemon/Counter.h
index 5202aa0..6891745 100644
--- a/daemon/Counter.h
+++ b/daemon/Counter.h
@@ -27,7 +27,6 @@ public:
27 mEnabled = false; 27 mEnabled = false;
28 mEvent = -1; 28 mEvent = -1;
29 mCount = 0; 29 mCount = 0;
30 mCores = -1;
31 mKey = 0; 30 mKey = 0;
32 mDriver = NULL; 31 mDriver = NULL;
33 } 32 }
@@ -36,7 +35,6 @@ public:
36 void setEnabled(const bool enabled) { mEnabled = enabled; } 35 void setEnabled(const bool enabled) { mEnabled = enabled; }
37 void setEvent(const int event) { mEvent = event; } 36 void setEvent(const int event) { mEvent = event; }
38 void setCount(const int count) { mCount = count; } 37 void setCount(const int count) { mCount = count; }
39 void setCores(const int cores) { mCores = cores; }
40 void setKey(const int key) { mKey = key; } 38 void setKey(const int key) { mKey = key; }
41 void setDriver(Driver *const driver) { mDriver = driver; } 39 void setDriver(Driver *const driver) { mDriver = driver; }
42 40
@@ -44,7 +42,6 @@ public:
44 bool isEnabled() const { return mEnabled; } 42 bool isEnabled() const { return mEnabled; }
45 int getEvent() const { return mEvent; } 43 int getEvent() const { return mEvent; }
46 int getCount() const { return mCount; } 44 int getCount() const { return mCount; }
47 int getCores() const { return mCores; }
48 int getKey() const { return mKey; } 45 int getKey() const { return mKey; }
49 Driver *getDriver() const { return mDriver; } 46 Driver *getDriver() const { return mDriver; }
50 47
@@ -57,7 +54,6 @@ private:
57 bool mEnabled; 54 bool mEnabled;
58 int mEvent; 55 int mEvent;
59 int mCount; 56 int mCount;
60 int mCores;
61 int mKey; 57 int mKey;
62 Driver *mDriver; 58 Driver *mDriver;
63}; 59};
diff --git a/daemon/DriverSource.cpp b/daemon/DriverSource.cpp
index 11d3095..f78ec6b 100644
--- a/daemon/DriverSource.cpp
+++ b/daemon/DriverSource.cpp
@@ -12,24 +12,19 @@
12 12
13#include <fcntl.h> 13#include <fcntl.h>
14#include <inttypes.h> 14#include <inttypes.h>
15#include <sys/prctl.h>
16#include <unistd.h> 15#include <unistd.h>
17 16
18#include "Buffer.h"
19#include "Child.h" 17#include "Child.h"
20#include "DynBuf.h"
21#include "Fifo.h" 18#include "Fifo.h"
22#include "Logging.h" 19#include "Logging.h"
23#include "Proc.h"
24#include "Sender.h" 20#include "Sender.h"
25#include "SessionData.h" 21#include "SessionData.h"
26 22
27extern Child *child; 23extern Child *child;
28 24
29DriverSource::DriverSource(sem_t *senderSem, sem_t *startProfile) : mBuffer(NULL), mFifo(NULL), mSenderSem(senderSem), mStartProfile(startProfile), mBufferSize(0), mBufferFD(0), mLength(1) { 25DriverSource::DriverSource(sem_t *senderSem, sem_t *startProfile) : mFifo(NULL), mSenderSem(senderSem), mStartProfile(startProfile), mBufferSize(0), mBufferFD(0), mLength(1) {
30 int driver_version = 0; 26 int driver_version = 0;
31 27
32 mBuffer = new Buffer(0, FRAME_PERF_ATTRS, 4*1024*1024, senderSem);
33 if (readIntDriver("/dev/gator/version", &driver_version) == -1) { 28 if (readIntDriver("/dev/gator/version", &driver_version) == -1) {
34 logg->logError(__FILE__, __LINE__, "Error reading gator driver version"); 29 logg->logError(__FILE__, __LINE__, "Error reading gator driver version");
35 handleException(); 30 handleException();
@@ -48,7 +43,7 @@ DriverSource::DriverSource(sem_t *senderSem, sem_t *startProfile) : mBuffer(NULL
48 handleException(); 43 handleException();
49 } else { 44 } else {
50 // Release version mismatch 45 // Release version mismatch
51 logg->logError(__FILE__, __LINE__, 46 logg->logError(__FILE__, __LINE__,
52 "gator driver version \"%d\" is different than gator daemon version \"%d\".\n" 47 "gator driver version \"%d\" is different than gator daemon version \"%d\".\n"
53 ">> Please upgrade the driver and daemon to the latest versions.", driver_version, PROTOCOL_VERSION); 48 ">> Please upgrade the driver and daemon to the latest versions.", driver_version, PROTOCOL_VERSION);
54 handleException(); 49 handleException();
@@ -92,28 +87,6 @@ bool DriverSource::prepare() {
92 return true; 87 return true;
93} 88}
94 89
95void DriverSource::bootstrapThread() {
96 prctl(PR_SET_NAME, (unsigned long)&"gatord-bootstrap", 0, 0, 0);
97
98 DynBuf printb;
99 DynBuf b1;
100 DynBuf b2;
101 DynBuf b3;
102
103 if (!readProc(mBuffer, false, &printb, &b1, &b2, &b3)) {
104 logg->logMessage("%s(%s:%i): readProc failed", __FUNCTION__, __FILE__, __LINE__);
105 handleException();
106 }
107
108 mBuffer->commit(1);
109 mBuffer->setDone();
110}
111
112void *DriverSource::bootstrapThreadStatic(void *arg) {
113 static_cast<DriverSource *>(arg)->bootstrapThread();
114 return NULL;
115}
116
117void DriverSource::run() { 90void DriverSource::run() {
118 // Get the initial pointer to the collect buffer 91 // Get the initial pointer to the collect buffer
119 char *collectBuffer = mFifo->start(); 92 char *collectBuffer = mFifo->start();
@@ -165,12 +138,6 @@ void DriverSource::run() {
165 138
166 sem_post(mStartProfile); 139 sem_post(mStartProfile);
167 140
168 pthread_t bootstrapThreadID;
169 if (pthread_create(&bootstrapThreadID, NULL, bootstrapThreadStatic, this) != 0) {
170 logg->logError(__FILE__, __LINE__, "Unable to start the gator_bootstrap thread");
171 handleException();
172 }
173
174 // Collect Data 141 // Collect Data
175 do { 142 do {
176 // This command will stall until data is received from the driver 143 // This command will stall until data is received from the driver
@@ -197,8 +164,6 @@ void DriverSource::run() {
197 } while (bytesCollected > 0); 164 } while (bytesCollected > 0);
198 165
199 logg->logMessage("Exit collect data loop"); 166 logg->logMessage("Exit collect data loop");
200
201 pthread_join(bootstrapThreadID, NULL);
202} 167}
203 168
204void DriverSource::interrupt() { 169void DriverSource::interrupt() {
@@ -209,7 +174,7 @@ void DriverSource::interrupt() {
209} 174}
210 175
211bool DriverSource::isDone() { 176bool DriverSource::isDone() {
212 return mLength <= 0 && (mBuffer == NULL || mBuffer->isDone()); 177 return mLength <= 0;
213} 178}
214 179
215void DriverSource::write(Sender *sender) { 180void DriverSource::write(Sender *sender) {
@@ -217,16 +182,6 @@ void DriverSource::write(Sender *sender) {
217 if (data != NULL) { 182 if (data != NULL) {
218 sender->writeData(data, mLength, RESPONSE_APC_DATA); 183 sender->writeData(data, mLength, RESPONSE_APC_DATA);
219 mFifo->release(); 184 mFifo->release();
220 // Assume the summary packet is in the first block received from the driver
221 gSessionData->mSentSummary = true;
222 }
223 if (mBuffer != NULL && !mBuffer->isDone()) {
224 mBuffer->write(sender);
225 if (mBuffer->isDone()) {
226 Buffer *buf = mBuffer;
227 mBuffer = NULL;
228 delete buf;
229 }
230 } 185 }
231} 186}
232 187
@@ -272,7 +227,7 @@ int DriverSource::readInt64Driver(const char *fullpath, int64_t *value) {
272 char *endptr; 227 char *endptr;
273 errno = 0; 228 errno = 0;
274 *value = strtoll(data, &endptr, 10); 229 *value = strtoll(data, &endptr, 10);
275 if (errno != 0 || (*endptr != '\n' && *endptr != '\0')) { 230 if (errno != 0 || *endptr != '\n') {
276 logg->logMessage("Invalid value in file %s", fullpath); 231 logg->logMessage("Invalid value in file %s", fullpath);
277 return -1; 232 return -1;
278 } 233 }
diff --git a/daemon/DriverSource.h b/daemon/DriverSource.h
index ec27b08..dcf1078 100644
--- a/daemon/DriverSource.h
+++ b/daemon/DriverSource.h
@@ -14,7 +14,6 @@
14 14
15#include "Source.h" 15#include "Source.h"
16 16
17class Buffer;
18class Fifo; 17class Fifo;
19 18
20class DriverSource : public Source { 19class DriverSource : public Source {
@@ -38,10 +37,6 @@ public:
38 static int writeReadDriver(const char *path, int64_t *value); 37 static int writeReadDriver(const char *path, int64_t *value);
39 38
40private: 39private:
41 static void *bootstrapThreadStatic(void *arg);
42 void bootstrapThread();
43
44 Buffer *mBuffer;
45 Fifo *mFifo; 40 Fifo *mFifo;
46 sem_t *const mSenderSem; 41 sem_t *const mSenderSem;
47 sem_t *const mStartProfile; 42 sem_t *const mStartProfile;
diff --git a/daemon/EventsXML.cpp b/daemon/EventsXML.cpp
index cf0192e..a07a046 100644
--- a/daemon/EventsXML.cpp
+++ b/daemon/EventsXML.cpp
@@ -13,7 +13,7 @@
13#include "OlyUtility.h" 13#include "OlyUtility.h"
14#include "SessionData.h" 14#include "SessionData.h"
15 15
16mxml_node_t *EventsXML::getTree() { 16char* EventsXML::getXML() {
17#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len 17#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len
18 char path[PATH_MAX]; 18 char path[PATH_MAX];
19 mxml_node_t *xml; 19 mxml_node_t *xml;
@@ -38,12 +38,6 @@ mxml_node_t *EventsXML::getTree() {
38 xml = mxmlLoadString(NULL, (const char *)events_xml, MXML_NO_CALLBACK); 38 xml = mxmlLoadString(NULL, (const char *)events_xml, MXML_NO_CALLBACK);
39 } 39 }
40 40
41 return xml;
42}
43
44char *EventsXML::getXML() {
45 mxml_node_t *xml = getTree();
46
47 // Add dynamic events from the drivers 41 // Add dynamic events from the drivers
48 mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND); 42 mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND);
49 if (!events) { 43 if (!events) {
@@ -54,19 +48,19 @@ char *EventsXML::getXML() {
54 driver->writeEvents(events); 48 driver->writeEvents(events);
55 } 49 }
56 50
57 char *string = mxmlSaveAllocString(xml, mxmlWhitespaceCB); 51 char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
58 mxmlDelete(xml); 52 mxmlDelete(xml);
59 53
60 return string; 54 return string;
61} 55}
62 56
63void EventsXML::write(const char *path) { 57void EventsXML::write(const char* path) {
64 char file[PATH_MAX]; 58 char file[PATH_MAX];
65 59
66 // Set full path 60 // Set full path
67 snprintf(file, PATH_MAX, "%s/events.xml", path); 61 snprintf(file, PATH_MAX, "%s/events.xml", path);
68 62
69 char *buf = getXML(); 63 char* buf = getXML();
70 if (util->writeToDisk(file, buf) < 0) { 64 if (util->writeToDisk(file, buf) < 0) {
71 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file); 65 logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
72 handleException(); 66 handleException();
diff --git a/daemon/EventsXML.h b/daemon/EventsXML.h
index ff7a02f..6cd1560 100644
--- a/daemon/EventsXML.h
+++ b/daemon/EventsXML.h
@@ -9,12 +9,9 @@
9#ifndef EVENTS_XML 9#ifndef EVENTS_XML
10#define EVENTS_XML 10#define EVENTS_XML
11 11
12#include "mxml/mxml.h"
13
14class EventsXML { 12class EventsXML {
15public: 13public:
16 mxml_node_t *getTree(); 14 char* getXML();
17 char *getXML();
18 void write(const char* path); 15 void write(const char* path);
19}; 16};
20 17
diff --git a/daemon/ExternalSource.cpp b/daemon/ExternalSource.cpp
index b6ec301..fe5824b 100644
--- a/daemon/ExternalSource.cpp
+++ b/daemon/ExternalSource.cpp
@@ -8,195 +8,41 @@
8 8
9#include "ExternalSource.h" 9#include "ExternalSource.h"
10 10
11#include <fcntl.h>
12#include <sys/prctl.h> 11#include <sys/prctl.h>
13#include <unistd.h>
14 12
15#include "Logging.h" 13#include "Logging.h"
16#include "OlySocket.h" 14#include "OlySocket.h"
17#include "SessionData.h" 15#include "SessionData.h"
18 16
19static const char MALI_VIDEO[] = "\0mali-video"; 17ExternalSource::ExternalSource(sem_t *senderSem) : mBuffer(0, FRAME_EXTERNAL, 1024, senderSem), mSock("/tmp/gator") {
20static const char MALI_VIDEO_STARTUP[] = "\0mali-video-startup";
21static const char MALI_VIDEO_V1[] = "MALI_VIDEO 1\n";
22
23static bool setNonblock(const int fd) {
24 int flags;
25
26 flags = fcntl(fd, F_GETFL);
27 if (flags < 0) {
28 logg->logMessage("fcntl getfl failed");
29 return false;
30 }
31
32 if (fcntl(fd, F_SETFL, flags | O_NONBLOCK) != 0) {
33 logg->logMessage("fcntl setfl failed");
34 return false;
35 }
36
37 return true;
38}
39
40ExternalSource::ExternalSource(sem_t *senderSem) : mBuffer(0, FRAME_EXTERNAL, 128*1024, senderSem), mMonitor(), mMveStartupUds(MALI_VIDEO_STARTUP, sizeof(MALI_VIDEO_STARTUP)), mInterruptFd(-1), mMveUds(-1) {
41 sem_init(&mBufferSem, 0, 0);
42} 18}
43 19
44ExternalSource::~ExternalSource() { 20ExternalSource::~ExternalSource() {
45} 21}
46 22
47void ExternalSource::waitFor(const uint64_t currTime, const int bytes) {
48 while (mBuffer.bytesAvailable() <= bytes) {
49 mBuffer.check(currTime);
50 sem_wait(&mBufferSem);
51 }
52}
53
54void ExternalSource::configureConnection(const int fd, const char *const handshake, size_t size) {
55 if (!setNonblock(fd)) {
56 logg->logError(__FILE__, __LINE__, "Unable to set nonblock on fh");
57 handleException();
58 }
59
60 if (!mMonitor.add(fd)) {
61 logg->logError(__FILE__, __LINE__, "Unable to add fh to monitor");
62 handleException();
63 }
64
65 // Write the handshake to the circular buffer
66 waitFor(1, Buffer::MAXSIZE_PACK32 + 4 + size - 1);
67 mBuffer.packInt(fd);
68 mBuffer.writeLEInt((unsigned char *)mBuffer.getWritePos(), size - 1);
69 mBuffer.advanceWrite(4);
70 mBuffer.writeBytes(handshake, size - 1);
71}
72
73bool ExternalSource::connectMve() {
74 if (!gSessionData->maliVideo.countersEnabled()) {
75 return true;
76 }
77
78 mMveUds = OlySocket::connect(MALI_VIDEO, sizeof(MALI_VIDEO));
79 if (mMveUds < 0) {
80 return false;
81 }
82
83 if (!gSessionData->maliVideo.start(mMveUds)) {
84 return false;
85 }
86
87 configureConnection(mMveUds, MALI_VIDEO_V1, sizeof(MALI_VIDEO_V1));
88
89 return true;
90}
91
92bool ExternalSource::prepare() { 23bool ExternalSource::prepare() {
93 if (!mMonitor.init() || !setNonblock(mMveStartupUds.getFd()) || !mMonitor.add(mMveStartupUds.getFd())) {
94 return false;
95 }
96
97 connectMve();
98
99 return true; 24 return true;
100} 25}
101 26
102void ExternalSource::run() { 27void ExternalSource::run() {
103 int pipefd[2]; 28 prctl(PR_SET_NAME, (unsigned long)&"gatord-uds", 0, 0, 0);
104
105 prctl(PR_SET_NAME, (unsigned long)&"gatord-external", 0, 0, 0);
106
107 if (pipe(pipefd) != 0) {
108 logg->logError(__FILE__, __LINE__, "pipe failed");
109 handleException();
110 }
111 mInterruptFd = pipefd[1];
112
113 if (!mMonitor.add(pipefd[0])) {
114 logg->logError(__FILE__, __LINE__, "Monitor::add failed");
115 handleException();
116 }
117 29
118 while (gSessionData->mSessionIsActive) { 30 while (gSessionData->mSessionIsActive) {
119 struct epoll_event events[16]; 31 // Will be aborted when the socket is closed at the end of the capture
120 // Clear any pending sem posts 32 int length = mSock.receive(mBuffer.getWritePos(), mBuffer.contiguousSpaceAvailable());
121 while (sem_trywait(&mBufferSem) == 0); 33 if (length <= 0) {
122 int ready = mMonitor.wait(events, ARRAY_LENGTH(events), -1); 34 break;
123 if (ready < 0) {
124 logg->logError(__FILE__, __LINE__, "Monitor::wait failed");
125 handleException();
126 } 35 }
127 36
128 const uint64_t currTime = getTime(); 37 mBuffer.advanceWrite(length);
129 38 mBuffer.check(0);
130 for (int i = 0; i < ready; ++i) {
131 const int fd = events[i].data.fd;
132 if (fd == mMveStartupUds.getFd()) {
133 // Mali Video Engine says it's alive
134 int client = mMveStartupUds.acceptConnection();
135 // Don't read from this connection, establish a new connection to Mali-V500
136 close(client);
137 if (!connectMve()) {
138 logg->logError(__FILE__, __LINE__, "Unable to configure incoming Mali video connection");
139 handleException();
140 }
141 } else if (fd == pipefd[0]) {
142 // Means interrupt has been called and mSessionIsActive should be reread
143 } else {
144 while (true) {
145 waitFor(currTime, Buffer::MAXSIZE_PACK32 + 4);
146
147 mBuffer.packInt(fd);
148 char *const bytesPos = mBuffer.getWritePos();
149 mBuffer.advanceWrite(4);
150 const int contiguous = mBuffer.contiguousSpaceAvailable();
151 const int bytes = read(fd, mBuffer.getWritePos(), contiguous);
152 if (bytes < 0) {
153 if (errno == EAGAIN) {
154 // Nothing left to read, and Buffer convention dictates that writePos can't go backwards
155 mBuffer.writeLEInt((unsigned char *)bytesPos, 0);
156 break;
157 }
158 // Something else failed, close the socket
159 mBuffer.writeLEInt((unsigned char *)bytesPos, -1);
160 close(fd);
161 break;
162 } else if (bytes == 0) {
163 // The other side is closed
164 mBuffer.writeLEInt((unsigned char *)bytesPos, -1);
165 close(fd);
166 break;
167 }
168
169 mBuffer.writeLEInt((unsigned char *)bytesPos, bytes);
170 mBuffer.advanceWrite(bytes);
171
172 // Short reads also mean nothing is left to read
173 if (bytes < contiguous) {
174 break;
175 }
176 }
177 }
178 }
179
180 // Only call mBufferCheck once per iteration
181 mBuffer.check(currTime);
182 } 39 }
183 40
184 mBuffer.setDone(); 41 mBuffer.setDone();
185
186 mInterruptFd = -1;
187 close(pipefd[0]);
188 close(pipefd[1]);
189} 42}
190 43
191void ExternalSource::interrupt() { 44void ExternalSource::interrupt() {
192 if (mInterruptFd >= 0) { 45 // Do nothing
193 int8_t c = 0;
194 // Write to the pipe to wake the monitor which will cause mSessionIsActive to be reread
195 if (::write(mInterruptFd, &c, sizeof(c)) != sizeof(c)) {
196 logg->logError(__FILE__, __LINE__, "write failed");
197 handleException();
198 }
199 }
200} 46}
201 47
202bool ExternalSource::isDone() { 48bool ExternalSource::isDone() {
@@ -204,12 +50,7 @@ bool ExternalSource::isDone() {
204} 50}
205 51
206void ExternalSource::write(Sender *sender) { 52void ExternalSource::write(Sender *sender) {
207 // Don't send external data until the summary packet is sent so that monotonic delta is available
208 if (!gSessionData->mSentSummary) {
209 return;
210 }
211 if (!mBuffer.isDone()) { 53 if (!mBuffer.isDone()) {
212 mBuffer.write(sender); 54 mBuffer.write(sender);
213 sem_post(&mBufferSem);
214 } 55 }
215} 56}
diff --git a/daemon/ExternalSource.h b/daemon/ExternalSource.h
index 2e7ed27..2052bdf 100644
--- a/daemon/ExternalSource.h
+++ b/daemon/ExternalSource.h
@@ -12,7 +12,6 @@
12#include <semaphore.h> 12#include <semaphore.h>
13 13
14#include "Buffer.h" 14#include "Buffer.h"
15#include "Monitor.h"
16#include "OlySocket.h" 15#include "OlySocket.h"
17#include "Source.h" 16#include "Source.h"
18 17
@@ -30,16 +29,8 @@ public:
30 void write(Sender *sender); 29 void write(Sender *sender);
31 30
32private: 31private:
33 void waitFor(const uint64_t currTime, const int bytes);
34 void configureConnection(const int fd, const char *const handshake, size_t size);
35 bool connectMve();
36
37 sem_t mBufferSem;
38 Buffer mBuffer; 32 Buffer mBuffer;
39 Monitor mMonitor; 33 OlySocket mSock;
40 OlyServerSocket mMveStartupUds;
41 int mInterruptFd;
42 int mMveUds;
43 34
44 // Intentionally unimplemented 35 // Intentionally unimplemented
45 ExternalSource(const ExternalSource &); 36 ExternalSource(const ExternalSource &);
diff --git a/daemon/Fifo.h b/daemon/Fifo.h
index bdda3f5..7dd7426 100644
--- a/daemon/Fifo.h
+++ b/daemon/Fifo.h
@@ -45,4 +45,4 @@ private:
45 Fifo &operator=(const Fifo &); 45 Fifo &operator=(const Fifo &);
46}; 46};
47 47
48#endif //__FIFO_H__ 48#endif //__FIFO_H__
diff --git a/daemon/Hwmon.cpp b/daemon/Hwmon.cpp
index e444247..778f307 100644
--- a/daemon/Hwmon.cpp
+++ b/daemon/Hwmon.cpp
@@ -28,7 +28,6 @@ public:
28 const char *getTitle() const { return title; } 28 const char *getTitle() const { return title; }
29 bool isDuplicate() const { return duplicate; } 29 bool isDuplicate() const { return duplicate; }
30 const char *getDisplay() const { return display; } 30 const char *getDisplay() const { return display; }
31 const char *getCounterClass() const { return counter_class; }
32 const char *getUnit() const { return unit; } 31 const char *getUnit() const { return unit; }
33 int getModifier() const { return modifier; } 32 int getModifier() const { return modifier; }
34 33
@@ -59,7 +58,6 @@ private:
59 char *label; 58 char *label;
60 const char *title; 59 const char *title;
61 const char *display; 60 const char *display;
62 const char *counter_class;
63 const char *unit; 61 const char *unit;
64 int modifier; 62 int modifier;
65 double previous_value; 63 double previous_value;
@@ -89,8 +87,7 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
89 case SENSORS_FEATURE_IN: 87 case SENSORS_FEATURE_IN:
90 title = "Voltage"; 88 title = "Voltage";
91 input = SENSORS_SUBFEATURE_IN_INPUT; 89 input = SENSORS_SUBFEATURE_IN_INPUT;
92 display = "maximum"; 90 display = "average";
93 counter_class = "absolute";
94 unit = "V"; 91 unit = "V";
95 modifier = 1000; 92 modifier = 1000;
96 monotonic = false; 93 monotonic = false;
@@ -99,7 +96,6 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
99 title = "Fan"; 96 title = "Fan";
100 input = SENSORS_SUBFEATURE_FAN_INPUT; 97 input = SENSORS_SUBFEATURE_FAN_INPUT;
101 display = "average"; 98 display = "average";
102 counter_class = "absolute";
103 unit = "RPM"; 99 unit = "RPM";
104 modifier = 1; 100 modifier = 1;
105 monotonic = false; 101 monotonic = false;
@@ -108,7 +104,6 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
108 title = "Temperature"; 104 title = "Temperature";
109 input = SENSORS_SUBFEATURE_TEMP_INPUT; 105 input = SENSORS_SUBFEATURE_TEMP_INPUT;
110 display = "maximum"; 106 display = "maximum";
111 counter_class = "absolute";
112 unit = "°C"; 107 unit = "°C";
113 modifier = 1000; 108 modifier = 1000;
114 monotonic = false; 109 monotonic = false;
@@ -116,8 +111,7 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
116 case SENSORS_FEATURE_POWER: 111 case SENSORS_FEATURE_POWER:
117 title = "Power"; 112 title = "Power";
118 input = SENSORS_SUBFEATURE_POWER_INPUT; 113 input = SENSORS_SUBFEATURE_POWER_INPUT;
119 display = "maximum"; 114 display = "average";
120 counter_class = "absolute";
121 unit = "W"; 115 unit = "W";
122 modifier = 1000000; 116 modifier = 1000000;
123 monotonic = false; 117 monotonic = false;
@@ -126,7 +120,6 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
126 title = "Energy"; 120 title = "Energy";
127 input = SENSORS_SUBFEATURE_ENERGY_INPUT; 121 input = SENSORS_SUBFEATURE_ENERGY_INPUT;
128 display = "accumulate"; 122 display = "accumulate";
129 counter_class = "delta";
130 unit = "J"; 123 unit = "J";
131 modifier = 1000000; 124 modifier = 1000000;
132 monotonic = true; 125 monotonic = true;
@@ -134,8 +127,7 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
134 case SENSORS_FEATURE_CURR: 127 case SENSORS_FEATURE_CURR:
135 title = "Current"; 128 title = "Current";
136 input = SENSORS_SUBFEATURE_CURR_INPUT; 129 input = SENSORS_SUBFEATURE_CURR_INPUT;
137 display = "maximum"; 130 display = "average";
138 counter_class = "absolute";
139 unit = "A"; 131 unit = "A";
140 modifier = 1000; 132 modifier = 1000;
141 monotonic = false; 133 monotonic = false;
@@ -144,7 +136,6 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, const sensors_chip_name *chip, co
144 title = "Humidity"; 136 title = "Humidity";
145 input = SENSORS_SUBFEATURE_HUMIDITY_INPUT; 137 input = SENSORS_SUBFEATURE_HUMIDITY_INPUT;
146 display = "average"; 138 display = "average";
147 counter_class = "absolute";
148 unit = "%"; 139 unit = "%";
149 modifier = 1000; 140 modifier = 1000;
150 monotonic = false; 141 monotonic = false;
@@ -320,7 +311,6 @@ void Hwmon::writeEvents(mxml_node_t *root) const {
320 mxmlElementSetAttr(node, "name", counter->getLabel()); 311 mxmlElementSetAttr(node, "name", counter->getLabel());
321 } 312 }
322 mxmlElementSetAttr(node, "display", counter->getDisplay()); 313 mxmlElementSetAttr(node, "display", counter->getDisplay());
323 mxmlElementSetAttr(node, "class", counter->getCounterClass());
324 mxmlElementSetAttr(node, "units", counter->getUnit()); 314 mxmlElementSetAttr(node, "units", counter->getUnit());
325 if (counter->getModifier() != 1) { 315 if (counter->getModifier() != 1) {
326 mxmlElementSetAttrf(node, "modifier", "%d", counter->getModifier()); 316 mxmlElementSetAttrf(node, "modifier", "%d", counter->getModifier());
diff --git a/daemon/KMod.cpp b/daemon/KMod.cpp
index 73e123d..9300002 100644
--- a/daemon/KMod.cpp
+++ b/daemon/KMod.cpp
@@ -58,15 +58,10 @@ void KMod::setupCounter(Counter &counter) {
58 return; 58 return;
59 } 59 }
60 60
61 int value = 0;
62 snprintf(text, sizeof(text), "%s/key", base); 61 snprintf(text, sizeof(text), "%s/key", base);
63 DriverSource::readIntDriver(text, &value); 62 int key = 0;
64 counter.setKey(value); 63 DriverSource::readIntDriver(text, &key);
65 64 counter.setKey(key);
66 snprintf(text, sizeof(text), "%s/cores", base);
67 if (DriverSource::readIntDriver(text, &value) == 0) {
68 counter.setCores(value);
69 }
70 65
71 snprintf(text, sizeof(text), "%s/event", base); 66 snprintf(text, sizeof(text), "%s/event", base);
72 DriverSource::writeDriver(text, counter.getEvent()); 67 DriverSource::writeDriver(text, counter.getEvent());
diff --git a/daemon/LocalCapture.h b/daemon/LocalCapture.h
index b1e7219..aadecce 100644
--- a/daemon/LocalCapture.h
+++ b/daemon/LocalCapture.h
@@ -23,4 +23,4 @@ private:
23 int removeDirAndAllContents(char* path); 23 int removeDirAndAllContents(char* path);
24}; 24};
25 25
26#endif //__LOCAL_CAPTURE_H__ 26#endif //__LOCAL_CAPTURE_H__
diff --git a/daemon/Logging.h b/daemon/Logging.h
index 4934bb0..6ae3280 100644
--- a/daemon/Logging.h
+++ b/daemon/Logging.h
@@ -33,4 +33,4 @@ extern Logging* logg;
33 33
34extern void handleException() __attribute__ ((noreturn)); 34extern void handleException() __attribute__ ((noreturn));
35 35
36#endif //__LOGGING_H__ 36#endif //__LOGGING_H__
diff --git a/daemon/Makefile b/daemon/Makefile
index 2ed49fd..24ee940 100644
--- a/daemon/Makefile
+++ b/daemon/Makefile
@@ -8,14 +8,14 @@
8# targets run 'make SOFTFLOAT=1 SYSROOT=/path/to/sysroot', see 8# targets run 'make SOFTFLOAT=1 SYSROOT=/path/to/sysroot', see
9# README_Streamline.txt for more details 9# README_Streamline.txt for more details
10 10
11CC = $(CROSS_COMPILE)gcc 11CPP = $(CROSS_COMPILE)g++
12CXX = $(CROSS_COMPILE)g++ 12GCC = $(CROSS_COMPILE)gcc
13 13
14# -mthumb-interwork is required for interworking to ARM or Thumb stdlibc 14# -mthumb-interwork is required for interworking to ARM or Thumb stdlibc
15CPPFLAGS += -mthumb-interwork 15CFLAGS += -mthumb-interwork
16 16
17ifeq ($(SOFTFLOAT),1) 17ifeq ($(SOFTFLOAT),1)
18 CPPFLAGS += -marm -march=armv4t -mfloat-abi=soft 18 CFLAGS += -marm -march=armv4t -mfloat-abi=soft
19 LDFLAGS += -marm -march=armv4t -mfloat-abi=soft 19 LDFLAGS += -marm -march=armv4t -mfloat-abi=soft
20endif 20endif
21ifneq ($(SYSROOT),) 21ifneq ($(SYSROOT),)
diff --git a/daemon/Makefile_aarch64 b/daemon/Makefile_aarch64
index efd1fa0..10b4b4a 100644
--- a/daemon/Makefile_aarch64
+++ b/daemon/Makefile_aarch64
@@ -4,9 +4,12 @@
4# 4#
5 5
6# Uncomment and define CROSS_COMPILE if it is not already defined 6# Uncomment and define CROSS_COMPILE if it is not already defined
7# CROSS_COMPILE=/path/to/cross-compiler/aarch64-linux-gnu- 7# CROSS_COMPILE=/path/to/cross-compiler/arm-linux-gnueabihf-
8# NOTE: This toolchain uses the hardfloat abi by default. For non-hardfloat
9# targets it is necessary to add options
10# '-marm -march=armv4t -mfloat-abi=soft'.
8 11
9CC = $(CROSS_COMPILE)gcc 12CPP = $(CROSS_COMPILE)g++
10CXX = $(CROSS_COMPILE)g++ 13GCC = $(CROSS_COMPILE)gcc
11 14
12include common.mk 15include common.mk
diff --git a/daemon/Monitor.cpp b/daemon/Monitor.cpp
index b34a15f..90d5c47 100644
--- a/daemon/Monitor.cpp
+++ b/daemon/Monitor.cpp
@@ -18,15 +18,8 @@ Monitor::Monitor() : mFd(-1) {
18} 18}
19 19
20Monitor::~Monitor() { 20Monitor::~Monitor() {
21 if (mFd >= 0) { 21 if (mFd >= -1) {
22 ::close(mFd); 22 close(mFd);
23 }
24}
25
26void Monitor::close() {
27 if (mFd >= 0) {
28 ::close(mFd);
29 mFd = -1;
30 } 23 }
31} 24}
32 25
diff --git a/daemon/Monitor.h b/daemon/Monitor.h
index 7194e0e..6e268b6 100644
--- a/daemon/Monitor.h
+++ b/daemon/Monitor.h
@@ -16,7 +16,6 @@ public:
16 Monitor(); 16 Monitor();
17 ~Monitor(); 17 ~Monitor();
18 18
19 void close();
20 bool init(); 19 bool init();
21 bool add(const int fd); 20 bool add(const int fd);
22 int wait(struct epoll_event *const events, int maxevents, int timeout); 21 int wait(struct epoll_event *const events, int maxevents, int timeout);
diff --git a/daemon/OlySocket.cpp b/daemon/OlySocket.cpp
index 28774e3..26e4768 100644
--- a/daemon/OlySocket.cpp
+++ b/daemon/OlySocket.cpp
@@ -9,7 +9,6 @@
9#include "OlySocket.h" 9#include "OlySocket.h"
10 10
11#include <stdio.h> 11#include <stdio.h>
12#include <string.h>
13#ifdef WIN32 12#ifdef WIN32
14#include <Winsock2.h> 13#include <Winsock2.h>
15#include <ws2tcpip.h> 14#include <ws2tcpip.h>
@@ -44,18 +43,16 @@ OlyServerSocket::OlyServerSocket(int port) {
44 createServerSocket(port); 43 createServerSocket(port);
45} 44}
46 45
46OlySocket::OlySocket(int port, const char* host) {
47 createClientSocket(host, port);
48}
49
47OlySocket::OlySocket(int socketID) : mSocketID(socketID) { 50OlySocket::OlySocket(int socketID) : mSocketID(socketID) {
48} 51}
49 52
50#ifndef WIN32 53#ifndef WIN32
51 54
52#define MIN(A, B) ({ \ 55OlyServerSocket::OlyServerSocket(const char* path) {
53 const __typeof__(A) __a = A; \
54 const __typeof__(B) __b = B; \
55 __a > __b ? __b : __a; \
56})
57
58OlyServerSocket::OlyServerSocket(const char* path, const size_t pathSize) {
59 // Create socket 56 // Create socket
60 mFDServer = socket(PF_UNIX, SOCK_STREAM, 0); 57 mFDServer = socket(PF_UNIX, SOCK_STREAM, 0);
61 if (mFDServer < 0) { 58 if (mFDServer < 0) {
@@ -63,11 +60,13 @@ OlyServerSocket::OlyServerSocket(const char* path, const size_t pathSize) {
63 handleException(); 60 handleException();
64 } 61 }
65 62
63 unlink(path);
64
66 // Create sockaddr_in structure, ensuring non-populated fields are zero 65 // Create sockaddr_in structure, ensuring non-populated fields are zero
67 struct sockaddr_un sockaddr; 66 struct sockaddr_un sockaddr;
68 memset((void*)&sockaddr, 0, sizeof(sockaddr)); 67 memset((void*)&sockaddr, 0, sizeof(sockaddr));
69 sockaddr.sun_family = AF_UNIX; 68 sockaddr.sun_family = AF_UNIX;
70 memcpy(sockaddr.sun_path, path, MIN(pathSize, sizeof(sockaddr.sun_path))); 69 strncpy(sockaddr.sun_path, path, sizeof(sockaddr.sun_path) - 1);
71 sockaddr.sun_path[sizeof(sockaddr.sun_path) - 1] = '\0'; 70 sockaddr.sun_path[sizeof(sockaddr.sun_path) - 1] = '\0';
72 71
73 // Bind the socket to an address 72 // Bind the socket to an address
@@ -83,25 +82,24 @@ OlyServerSocket::OlyServerSocket(const char* path, const size_t pathSize) {
83 } 82 }
84} 83}
85 84
86int OlySocket::connect(const char* path, const size_t pathSize) { 85OlySocket::OlySocket(const char* path) {
87 int fd = socket(PF_UNIX, SOCK_STREAM, 0); 86 mSocketID = socket(PF_UNIX, SOCK_STREAM, 0);
88 if (fd < 0) { 87 if (mSocketID < 0) {
89 return -1; 88 return;
90 } 89 }
91 90
92 // Create sockaddr_in structure, ensuring non-populated fields are zero 91 // Create sockaddr_in structure, ensuring non-populated fields are zero
93 struct sockaddr_un sockaddr; 92 struct sockaddr_un sockaddr;
94 memset((void*)&sockaddr, 0, sizeof(sockaddr)); 93 memset((void*)&sockaddr, 0, sizeof(sockaddr));
95 sockaddr.sun_family = AF_UNIX; 94 sockaddr.sun_family = AF_UNIX;
96 memcpy(sockaddr.sun_path, path, MIN(pathSize, sizeof(sockaddr.sun_path))); 95 strncpy(sockaddr.sun_path, path, sizeof(sockaddr.sun_path) - 1);
97 sockaddr.sun_path[sizeof(sockaddr.sun_path) - 1] = '\0'; 96 sockaddr.sun_path[sizeof(sockaddr.sun_path) - 1] = '\0';
98 97
99 if (::connect(fd, (const struct sockaddr*)&sockaddr, sizeof(sockaddr)) < 0) { 98 if (connect(mSocketID, (const struct sockaddr*)&sockaddr, sizeof(sockaddr)) < 0) {
100 close(fd); 99 close(mSocketID);
101 return -1; 100 mSocketID = -1;
101 return;
102 } 102 }
103
104 return fd;
105} 103}
106 104
107#endif 105#endif
@@ -139,6 +137,47 @@ void OlyServerSocket::closeServerSocket() {
139 mFDServer = 0; 137 mFDServer = 0;
140} 138}
141 139
140void OlySocket::createClientSocket(const char* hostname, int portno) {
141#ifdef WIN32
142 // TODO: Implement for Windows
143#else
144 char buf[32];
145 struct addrinfo hints, *res, *res0;
146
147 snprintf(buf, sizeof(buf), "%d", portno);
148 mSocketID = -1;
149 memset((void*)&hints, 0, sizeof(hints));
150 hints.ai_family = PF_UNSPEC;
151 hints.ai_socktype = SOCK_STREAM;
152
153 if (getaddrinfo(hostname, buf, &hints, &res0)) {
154 logg->logError(__FILE__, __LINE__, "Client socket failed to get address info for %s", hostname);
155 handleException();
156 }
157 for (res=res0; res!=NULL; res = res->ai_next) {
158 if ( res->ai_family != PF_INET || res->ai_socktype != SOCK_STREAM ) {
159 continue;
160 }
161 mSocketID = socket(res->ai_family, res->ai_socktype, res->ai_protocol);
162 if (mSocketID < 0) {
163 continue;
164 }
165 if (connect(mSocketID, res->ai_addr, res->ai_addrlen) < 0) {
166 close(mSocketID);
167 mSocketID = -1;
168 }
169 if (mSocketID > 0) {
170 break;
171 }
172 }
173 freeaddrinfo(res0);
174 if (mSocketID <= 0) {
175 logg->logError(__FILE__, __LINE__, "Could not connect to client socket. Ensure ARM Streamline is running.");
176 handleException();
177 }
178#endif
179}
180
142void OlyServerSocket::createServerSocket(int port) { 181void OlyServerSocket::createServerSocket(int port) {
143 int family = AF_INET6; 182 int family = AF_INET6;
144 183
diff --git a/daemon/OlySocket.h b/daemon/OlySocket.h
index 20c67cc..eab786b 100644
--- a/daemon/OlySocket.h
+++ b/daemon/OlySocket.h
@@ -9,15 +9,13 @@
9#ifndef __OLY_SOCKET_H__ 9#ifndef __OLY_SOCKET_H__
10#define __OLY_SOCKET_H__ 10#define __OLY_SOCKET_H__
11 11
12#include <stddef.h>
13
14class OlySocket { 12class OlySocket {
15public: 13public:
14 OlySocket(int port, const char* hostname);
15 OlySocket(int socketID);
16#ifndef WIN32 16#ifndef WIN32
17 static int connect(const char* path, const size_t pathSize); 17 OlySocket(const char* path);
18#endif 18#endif
19
20 OlySocket(int socketID);
21 ~OlySocket(); 19 ~OlySocket();
22 20
23 void closeSocket(); 21 void closeSocket();
@@ -31,21 +29,21 @@ public:
31 29
32private: 30private:
33 int mSocketID; 31 int mSocketID;
32
33 void createClientSocket(const char* hostname, int port);
34}; 34};
35 35
36class OlyServerSocket { 36class OlyServerSocket {
37public: 37public:
38 OlyServerSocket(int port); 38 OlyServerSocket(int port);
39#ifndef WIN32 39#ifndef WIN32
40 OlyServerSocket(const char* path, const size_t pathSize); 40 OlyServerSocket(const char* path);
41#endif 41#endif
42 ~OlyServerSocket(); 42 ~OlyServerSocket();
43 43
44 int acceptConnection(); 44 int acceptConnection();
45 void closeServerSocket(); 45 void closeServerSocket();
46 46
47 int getFd() { return mFDServer; }
48
49private: 47private:
50 int mFDServer; 48 int mFDServer;
51 49
diff --git a/daemon/PerfDriver.cpp b/daemon/PerfDriver.cpp
index ac97a07..8e25c22 100644
--- a/daemon/PerfDriver.cpp
+++ b/daemon/PerfDriver.cpp
@@ -11,7 +11,6 @@
11#include <dirent.h> 11#include <dirent.h>
12#include <sys/utsname.h> 12#include <sys/utsname.h>
13#include <time.h> 13#include <time.h>
14#include <unistd.h>
15 14
16#include "Buffer.h" 15#include "Buffer.h"
17#include "Config.h" 16#include "Config.h"
@@ -31,7 +30,7 @@
31struct gator_cpu { 30struct gator_cpu {
32 const int cpuid; 31 const int cpuid;
33 // Human readable name 32 // Human readable name
34 const char *const core_name; 33 const char core_name[32];
35 // gatorfs event and Perf PMU name 34 // gatorfs event and Perf PMU name
36 const char *const pmnc_name; 35 const char *const pmnc_name;
37 const int pmnc_counters; 36 const int pmnc_counters;
@@ -63,20 +62,9 @@ static const struct gator_cpu gator_cpus[] = {
63static const char OLD_PMU_PREFIX[] = "ARMv7 Cortex-"; 62static const char OLD_PMU_PREFIX[] = "ARMv7 Cortex-";
64static const char NEW_PMU_PREFIX[] = "ARMv7_Cortex_"; 63static const char NEW_PMU_PREFIX[] = "ARMv7_Cortex_";
65 64
66struct uncore_counter {
67 // gatorfs event and Perf PMU name
68 const char *const name;
69 const int count;
70};
71
72static const struct uncore_counter uncore_counters[] = {
73 { "CCI_400", 4 },
74 { "CCI_400-r1", 4 },
75};
76
77class PerfCounter { 65class PerfCounter {
78public: 66public:
79 PerfCounter(PerfCounter *next, const char *name, uint32_t type, uint64_t config, bool perCpu) : mNext(next), mName(name), mType(type), mCount(0), mKey(getEventKey()), mConfig(config), mEnabled(false), mPerCpu(perCpu) {} 67 PerfCounter(PerfCounter *next, const char *name, uint32_t type, uint64_t config) : mNext(next), mName(name), mType(type), mCount(0), mKey(getEventKey()), mConfig(config), mEnabled(false) {}
80 ~PerfCounter() { 68 ~PerfCounter() {
81 delete [] mName; 69 delete [] mName;
82 } 70 }
@@ -91,7 +79,6 @@ public:
91 void setConfig(const uint64_t config) { mConfig = config; } 79 void setConfig(const uint64_t config) { mConfig = config; }
92 bool isEnabled() const { return mEnabled; } 80 bool isEnabled() const { return mEnabled; }
93 void setEnabled(const bool enabled) { mEnabled = enabled; } 81 void setEnabled(const bool enabled) { mEnabled = enabled; }
94 bool isPerCpu() const { return mPerCpu; }
95 82
96private: 83private:
97 PerfCounter *const mNext; 84 PerfCounter *const mNext;
@@ -100,11 +87,10 @@ private:
100 int mCount; 87 int mCount;
101 const int mKey; 88 const int mKey;
102 uint64_t mConfig; 89 uint64_t mConfig;
103 int mEnabled : 1, 90 bool mEnabled;
104 mPerCpu : 1;
105}; 91};
106 92
107PerfDriver::PerfDriver() : mCounters(NULL), mIsSetup(false), mLegacySupport(false) { 93PerfDriver::PerfDriver() : mCounters(NULL), mIsSetup(false) {
108} 94}
109 95
110PerfDriver::~PerfDriver() { 96PerfDriver::~PerfDriver() {
@@ -119,27 +105,13 @@ void PerfDriver::addCpuCounters(const char *const counterName, const int type, c
119 int len = snprintf(NULL, 0, "%s_ccnt", counterName) + 1; 105 int len = snprintf(NULL, 0, "%s_ccnt", counterName) + 1;
120 char *name = new char[len]; 106 char *name = new char[len];
121 snprintf(name, len, "%s_ccnt", counterName); 107 snprintf(name, len, "%s_ccnt", counterName);
122 mCounters = new PerfCounter(mCounters, name, type, -1, true); 108 mCounters = new PerfCounter(mCounters, name, type, -1);
123 109
124 for (int j = 0; j < numCounters; ++j) { 110 for (int j = 0; j < numCounters; ++j) {
125 len = snprintf(NULL, 0, "%s_cnt%d", counterName, j) + 1; 111 len = snprintf(NULL, 0, "%s_cnt%d", counterName, j) + 1;
126 name = new char[len]; 112 name = new char[len];
127 snprintf(name, len, "%s_cnt%d", counterName, j); 113 snprintf(name, len, "%s_cnt%d", counterName, j);
128 mCounters = new PerfCounter(mCounters, name, type, -1, true); 114 mCounters = new PerfCounter(mCounters, name, type, -1);
129 }
130}
131
132void PerfDriver::addUncoreCounters(const char *const counterName, const int type, const int numCounters) {
133 int len = snprintf(NULL, 0, "%s_ccnt", counterName) + 1;
134 char *name = new char[len];
135 snprintf(name, len, "%s_ccnt", counterName);
136 mCounters = new PerfCounter(mCounters, name, type, -1, false);
137
138 for (int j = 0; j < numCounters; ++j) {
139 len = snprintf(NULL, 0, "%s_cnt%d", counterName, j) + 1;
140 name = new char[len];
141 snprintf(name, len, "%s_cnt%d", counterName, j);
142 mCounters = new PerfCounter(mCounters, name, type, -1, false);
143 } 115 }
144} 116}
145 117
@@ -167,16 +139,10 @@ bool PerfDriver::setup() {
167 } 139 }
168 } 140 }
169 141
170 if (KERNEL_VERSION(release[0], release[1], release[2]) < KERNEL_VERSION(3, 4, 0)) { 142 if (KERNEL_VERSION(release[0], release[1], release[2]) < KERNEL_VERSION(3, 12, 0)) {
171 logg->logMessage("%s(%s:%i): Unsupported kernel version", __FUNCTION__, __FILE__, __LINE__); 143 logg->logMessage("%s(%s:%i): Unsupported kernel version", __FUNCTION__, __FILE__, __LINE__);
172 return false; 144 return false;
173 } 145 }
174 mLegacySupport = KERNEL_VERSION(release[0], release[1], release[2]) < KERNEL_VERSION(3, 12, 0);
175
176 if (access(EVENTS_PATH, R_OK) != 0) {
177 logg->logMessage("%s(%s:%i): " EVENTS_PATH " does not exist, is CONFIG_TRACING enabled?", __FUNCTION__, __FILE__, __LINE__);
178 return false;
179 }
180 146
181 // Add supported PMUs 147 // Add supported PMUs
182 bool foundCpu = false; 148 bool foundCpu = false;
@@ -208,21 +174,6 @@ bool PerfDriver::setup() {
208 foundCpu = true; 174 foundCpu = true;
209 addCpuCounters(gator_cpus[i].pmnc_name, type, gator_cpus[i].pmnc_counters); 175 addCpuCounters(gator_cpus[i].pmnc_name, type, gator_cpus[i].pmnc_counters);
210 } 176 }
211
212 for (int i = 0; i < ARRAY_LENGTH(uncore_counters); ++i) {
213 if (strcmp(dirent->d_name, uncore_counters[i].name) != 0) {
214 continue;
215 }
216
217 int type;
218 char buf[256];
219 snprintf(buf, sizeof(buf), PERF_DEVICES "/%s/type", dirent->d_name);
220 if (DriverSource::readIntDriver(buf, &type) != 0) {
221 continue;
222 }
223
224 addUncoreCounters(uncore_counters[i].name, type, uncore_counters[i].count);
225 }
226 } 177 }
227 closedir(dir); 178 closedir(dir);
228 179
@@ -252,12 +203,12 @@ bool PerfDriver::setup() {
252 203
253 id = getTracepointId("irq/softirq_exit", &printb); 204 id = getTracepointId("irq/softirq_exit", &printb);
254 if (id >= 0) { 205 if (id >= 0) {
255 mCounters = new PerfCounter(mCounters, "Linux_irq_softirq", PERF_TYPE_TRACEPOINT, id, true); 206 mCounters = new PerfCounter(mCounters, "Linux_irq_softirq", PERF_TYPE_TRACEPOINT, id);
256 } 207 }
257 208
258 id = getTracepointId("irq/irq_handler_exit", &printb); 209 id = getTracepointId("irq/irq_handler_exit", &printb);
259 if (id >= 0) { 210 if (id >= 0) {
260 mCounters = new PerfCounter(mCounters, "Linux_irq_irq", PERF_TYPE_TRACEPOINT, id, true); 211 mCounters = new PerfCounter(mCounters, "Linux_irq_irq", PERF_TYPE_TRACEPOINT, id);
261 } 212 }
262 213
263 //Linux_block_rq_wr 214 //Linux_block_rq_wr
@@ -267,7 +218,7 @@ bool PerfDriver::setup() {
267 218
268 id = getTracepointId(SCHED_SWITCH, &printb); 219 id = getTracepointId(SCHED_SWITCH, &printb);
269 if (id >= 0) { 220 if (id >= 0) {
270 mCounters = new PerfCounter(mCounters, "Linux_sched_switch", PERF_TYPE_TRACEPOINT, id, true); 221 mCounters = new PerfCounter(mCounters, "Linux_sched_switch", PERF_TYPE_TRACEPOINT, id);
271 } 222 }
272 223
273 //Linux_meminfo_memused 224 //Linux_meminfo_memused
@@ -276,7 +227,7 @@ bool PerfDriver::setup() {
276 //Linux_power_cpu_freq 227 //Linux_power_cpu_freq
277 //Linux_power_cpu_idle 228 //Linux_power_cpu_idle
278 229
279 mCounters = new PerfCounter(mCounters, "Linux_cpu_wait_contention", TYPE_DERIVED, -1, false); 230 mCounters = new PerfCounter(mCounters, "Linux_cpu_wait_contention", TYPE_DERIVED, -1);
280 231
281 //Linux_cpu_wait_io 232 //Linux_cpu_wait_io
282 233
@@ -301,16 +252,15 @@ bool PerfDriver::summary(Buffer *const buffer) {
301 } 252 }
302 const int64_t timestamp = (int64_t)ts.tv_sec * 1000000000L + ts.tv_nsec; 253 const int64_t timestamp = (int64_t)ts.tv_sec * 1000000000L + ts.tv_nsec;
303 254
304 const int64_t uptime = getTime(); 255 if (clock_gettime(CLOCK_MONOTONIC, &ts) != 0) {
256 logg->logMessage("%s(%s:%i): clock_gettime failed", __FUNCTION__, __FILE__, __LINE__);
257 return false;
258 }
259 const int64_t uptime = (int64_t)ts.tv_sec * 1000000000L + ts.tv_nsec;
305 260
306 buffer->summary(timestamp, uptime, 0, buf); 261 buffer->summary(timestamp, uptime, 0, buf);
307 262
308 for (int i = 0; i < gSessionData->mCores; ++i) { 263 for (int i = 0; i < gSessionData->mCores; ++i) {
309 // Don't send information on a cpu we know nothing about
310 if (gSessionData->mCpuIds[i] == -1) {
311 continue;
312 }
313
314 int j; 264 int j;
315 for (j = 0; j < ARRAY_LENGTH(gator_cpus); ++j) { 265 for (j = 0; j < ARRAY_LENGTH(gator_cpus); ++j) {
316 if (gator_cpus[j].cpuid == gSessionData->mCpuIds[i]) { 266 if (gator_cpus[j].cpuid == gSessionData->mCpuIds[i]) {
@@ -320,11 +270,7 @@ bool PerfDriver::summary(Buffer *const buffer) {
320 if (gator_cpus[j].cpuid == gSessionData->mCpuIds[i]) { 270 if (gator_cpus[j].cpuid == gSessionData->mCpuIds[i]) {
321 buffer->coreName(i, gSessionData->mCpuIds[i], gator_cpus[j].core_name); 271 buffer->coreName(i, gSessionData->mCpuIds[i], gator_cpus[j].core_name);
322 } else { 272 } else {
323 if (gSessionData->mCpuIds[i] == -1) { 273 snprintf(buf, sizeof(buf), "Unknown (0x%.3x)", gSessionData->mCpuIds[i]);
324 snprintf(buf, sizeof(buf), "Unknown");
325 } else {
326 snprintf(buf, sizeof(buf), "Unknown (0x%.3x)", gSessionData->mCpuIds[i]);
327 }
328 buffer->coreName(i, gSessionData->mCpuIds[i], buf); 274 buffer->coreName(i, gSessionData->mCpuIds[i], buf);
329 } 275 }
330 } 276 }
@@ -380,10 +326,10 @@ int PerfDriver::writeCounters(mxml_node_t *root) const {
380 return count; 326 return count;
381} 327}
382 328
383bool PerfDriver::enable(PerfGroup *const group, Buffer *const buffer) const { 329bool PerfDriver::enable(PerfGroup *group, Buffer *const buffer) const {
384 for (PerfCounter * counter = mCounters; counter != NULL; counter = counter->getNext()) { 330 for (PerfCounter * counter = mCounters; counter != NULL; counter = counter->getNext()) {
385 if (counter->isEnabled() && (counter->getType() != TYPE_DERIVED)) { 331 if (counter->isEnabled() && (counter->getType() != TYPE_DERIVED)) {
386 if (!group->add(buffer, counter->getKey(), counter->getType(), counter->getConfig(), counter->getCount(), counter->getCount() > 0 ? PERF_SAMPLE_TID | PERF_SAMPLE_IP : 0, counter->isPerCpu() ? PERF_GROUP_PER_CPU : 0)) { 332 if (!group->add(buffer, counter->getKey(), counter->getType(), counter->getConfig(), counter->getCount(), 0, 0)) {
387 logg->logMessage("%s(%s:%i): PerfGroup::add failed", __FUNCTION__, __FILE__, __LINE__); 333 logg->logMessage("%s(%s:%i): PerfGroup::add failed", __FUNCTION__, __FILE__, __LINE__);
388 return false; 334 return false;
389 } 335 }
diff --git a/daemon/PerfDriver.h b/daemon/PerfDriver.h
index 2cae575..3181b74 100644
--- a/daemon/PerfDriver.h
+++ b/daemon/PerfDriver.h
@@ -27,8 +27,6 @@ public:
27 PerfDriver(); 27 PerfDriver();
28 ~PerfDriver(); 28 ~PerfDriver();
29 29
30 bool getLegacySupport() const { return mLegacySupport; }
31
32 bool setup(); 30 bool setup();
33 bool summary(Buffer *const buffer); 31 bool summary(Buffer *const buffer);
34 bool isSetup() const { return mIsSetup; } 32 bool isSetup() const { return mIsSetup; }
@@ -39,18 +37,16 @@ public:
39 37
40 int writeCounters(mxml_node_t *root) const; 38 int writeCounters(mxml_node_t *root) const;
41 39
42 bool enable(PerfGroup *const group, Buffer *const buffer) const; 40 bool enable(PerfGroup *group, Buffer *const buffer) const;
43 41
44 static long long getTracepointId(const char *const name, DynBuf *const printb); 42 static long long getTracepointId(const char *const name, DynBuf *const printb);
45 43
46private: 44private:
47 PerfCounter *findCounter(const Counter &counter) const; 45 PerfCounter *findCounter(const Counter &counter) const;
48 void addCpuCounters(const char *const counterName, const int type, const int numCounters); 46 void addCpuCounters(const char *const counterName, const int type, const int numCounters);
49 void addUncoreCounters(const char *const counterName, const int type, const int numCounters);
50 47
51 PerfCounter *mCounters; 48 PerfCounter *mCounters;
52 bool mIsSetup; 49 bool mIsSetup;
53 bool mLegacySupport;
54 50
55 // Intentionally undefined 51 // Intentionally undefined
56 PerfDriver(const PerfDriver &); 52 PerfDriver(const PerfDriver &);
diff --git a/daemon/PerfGroup.cpp b/daemon/PerfGroup.cpp
index 2a0239f..faf5fca 100644
--- a/daemon/PerfGroup.cpp
+++ b/daemon/PerfGroup.cpp
@@ -23,9 +23,7 @@
23#define DEFAULT_PEA_ARGS(pea, additionalSampleType) \ 23#define DEFAULT_PEA_ARGS(pea, additionalSampleType) \
24 pea.size = sizeof(pea); \ 24 pea.size = sizeof(pea); \
25 /* Emit time, read_format below, group leader id, and raw tracepoint info */ \ 25 /* Emit time, read_format below, group leader id, and raw tracepoint info */ \
26 pea.sample_type = (gSessionData->perf.getLegacySupport() \ 26 pea.sample_type = PERF_SAMPLE_TIME | PERF_SAMPLE_READ | PERF_SAMPLE_IDENTIFIER | additionalSampleType; \
27 ? PERF_SAMPLE_TID | PERF_SAMPLE_IP | PERF_SAMPLE_TIME | PERF_SAMPLE_READ | PERF_SAMPLE_ID \
28 : PERF_SAMPLE_TIME | PERF_SAMPLE_READ | PERF_SAMPLE_IDENTIFIER ) | additionalSampleType; \
29 /* Emit emit value in group format */ \ 27 /* Emit emit value in group format */ \
30 pea.read_format = PERF_FORMAT_ID | PERF_FORMAT_GROUP; \ 28 pea.read_format = PERF_FORMAT_ID | PERF_FORMAT_GROUP; \
31 /* start out disabled */ \ 29 /* start out disabled */ \
@@ -41,7 +39,6 @@ static int sys_perf_event_open(struct perf_event_attr *const attr, const pid_t p
41 39
42PerfGroup::PerfGroup(PerfBuffer *const pb) : mPb(pb) { 40PerfGroup::PerfGroup(PerfBuffer *const pb) : mPb(pb) {
43 memset(&mAttrs, 0, sizeof(mAttrs)); 41 memset(&mAttrs, 0, sizeof(mAttrs));
44 memset(&mPerCpu, 0, sizeof(mPerCpu));
45 memset(&mKeys, -1, sizeof(mKeys)); 42 memset(&mKeys, -1, sizeof(mKeys));
46 memset(&mFds, -1, sizeof(mFds)); 43 memset(&mFds, -1, sizeof(mFds));
47} 44}
@@ -78,7 +75,6 @@ bool PerfGroup::add(Buffer *const buffer, const int key, const __u32 type, const
78 mAttrs[i].freq = (flags & PERF_GROUP_FREQ ? 1 : 0); 75 mAttrs[i].freq = (flags & PERF_GROUP_FREQ ? 1 : 0);
79 mAttrs[i].task = (flags & PERF_GROUP_TASK ? 1 : 0); 76 mAttrs[i].task = (flags & PERF_GROUP_TASK ? 1 : 0);
80 mAttrs[i].sample_id_all = (flags & PERF_GROUP_SAMPLE_ID_ALL ? 1 : 0); 77 mAttrs[i].sample_id_all = (flags & PERF_GROUP_SAMPLE_ID_ALL ? 1 : 0);
81 mPerCpu[i] = (flags & PERF_GROUP_PER_CPU);
82 78
83 mKeys[i] = key; 79 mKeys[i] = key;
84 80
@@ -95,17 +91,13 @@ bool PerfGroup::prepareCPU(const int cpu) {
95 continue; 91 continue;
96 } 92 }
97 93
98 if ((cpu != 0) && !mPerCpu[i]) {
99 continue;
100 }
101
102 const int offset = i * gSessionData->mCores; 94 const int offset = i * gSessionData->mCores;
103 if (mFds[cpu + offset] >= 0) { 95 if (mFds[cpu + offset] >= 0) {
104 logg->logMessage("%s(%s:%i): cpu already online or not correctly cleaned up", __FUNCTION__, __FILE__, __LINE__); 96 logg->logMessage("%s(%s:%i): cpu already online or not correctly cleaned up", __FUNCTION__, __FILE__, __LINE__);
105 return false; 97 return false;
106 } 98 }
107 99
108 logg->logMessage("%s(%s:%i): perf_event_open cpu: %i type: %lli config: %lli sample: %lli sample_type: 0x%llx pinned: %i mmap: %i comm: %i freq: %i task: %i sample_id_all: %i", __FUNCTION__, __FILE__, __LINE__, cpu, (long long)mAttrs[i].type, (long long)mAttrs[i].config, (long long)mAttrs[i].sample_period, (long long)mAttrs[i].sample_type, mAttrs[i].pinned, mAttrs[i].mmap, mAttrs[i].comm, mAttrs[i].freq, mAttrs[i].task, mAttrs[i].sample_id_all); 100 logg->logMessage("%s(%s:%i): perf_event_open cpu: %i type: %lli config: %lli sample: %lli sample_type: %lli", __FUNCTION__, __FILE__, __LINE__, cpu, (long long)mAttrs[i].type, (long long)mAttrs[i].config, (long long)mAttrs[i].sample_period, (long long)mAttrs[i].sample_type);
109 mFds[cpu + offset] = sys_perf_event_open(&mAttrs[i], -1, cpu, i == 0 ? -1 : mFds[cpu], i == 0 ? 0 : PERF_FLAG_FD_OUTPUT); 101 mFds[cpu + offset] = sys_perf_event_open(&mAttrs[i], -1, cpu, i == 0 ? -1 : mFds[cpu], i == 0 ? 0 : PERF_FLAG_FD_OUTPUT);
110 if (mFds[cpu + offset] < 0) { 102 if (mFds[cpu + offset] < 0) {
111 logg->logMessage("%s(%s:%i): failed %s", __FUNCTION__, __FILE__, __LINE__, strerror(errno)); 103 logg->logMessage("%s(%s:%i): failed %s", __FUNCTION__, __FILE__, __LINE__, strerror(errno));
@@ -133,9 +125,7 @@ int PerfGroup::onlineCPU(const int cpu, const bool start, Buffer *const buffer,
133 } 125 }
134 126
135 coreKeys[idCount] = mKeys[i]; 127 coreKeys[idCount] = mKeys[i];
136 if (!gSessionData->perf.getLegacySupport() && ioctl(fd, PERF_EVENT_IOC_ID, &ids[idCount]) != 0 && 128 if (ioctl(fd, PERF_EVENT_IOC_ID, &ids[idCount]) != 0) {
137 // Workaround for running 32-bit gatord on 64-bit systems, kernel patch in the works
138 ioctl(fd, (PERF_EVENT_IOC_ID & ~IOCSIZE_MASK) | (8 << _IOC_SIZESHIFT), &ids[idCount]) != 0) {
139 logg->logMessage("%s(%s:%i): ioctl failed", __FUNCTION__, __FILE__, __LINE__); 129 logg->logMessage("%s(%s:%i): ioctl failed", __FUNCTION__, __FILE__, __LINE__);
140 return false; 130 return false;
141 } 131 }
@@ -147,17 +137,7 @@ int PerfGroup::onlineCPU(const int cpu, const bool start, Buffer *const buffer,
147 return false; 137 return false;
148 } 138 }
149 139
150 if (!gSessionData->perf.getLegacySupport()) { 140 buffer->keys(idCount, ids, coreKeys);
151 buffer->keys(idCount, ids, coreKeys);
152 } else {
153 char buf[1024];
154 ssize_t bytes = read(mFds[cpu], buf, sizeof(buf));
155 if (bytes < 0) {
156 logg->logMessage("read failed");
157 return false;
158 }
159 buffer->keysOld(idCount, coreKeys, bytes, buf);
160 }
161 141
162 if (start) { 142 if (start) {
163 for (int i = 0; i < ARRAY_LENGTH(mKeys); ++i) { 143 for (int i = 0; i < ARRAY_LENGTH(mKeys); ++i) {
diff --git a/daemon/PerfGroup.h b/daemon/PerfGroup.h
index 3f1e2bb..af496d4 100644
--- a/daemon/PerfGroup.h
+++ b/daemon/PerfGroup.h
@@ -24,7 +24,6 @@ enum PerfGroupFlags {
24 PERF_GROUP_FREQ = 1 << 2, 24 PERF_GROUP_FREQ = 1 << 2,
25 PERF_GROUP_TASK = 1 << 3, 25 PERF_GROUP_TASK = 1 << 3,
26 PERF_GROUP_SAMPLE_ID_ALL = 1 << 4, 26 PERF_GROUP_SAMPLE_ID_ALL = 1 << 4,
27 PERF_GROUP_PER_CPU = 1 << 5,
28}; 27};
29 28
30class PerfGroup { 29class PerfGroup {
@@ -44,7 +43,6 @@ public:
44private: 43private:
45 // +1 for the group leader 44 // +1 for the group leader
46 struct perf_event_attr mAttrs[MAX_PERFORMANCE_COUNTERS + 1]; 45 struct perf_event_attr mAttrs[MAX_PERFORMANCE_COUNTERS + 1];
47 bool mPerCpu[MAX_PERFORMANCE_COUNTERS + 1];
48 int mKeys[MAX_PERFORMANCE_COUNTERS + 1]; 46 int mKeys[MAX_PERFORMANCE_COUNTERS + 1];
49 int mFds[NR_CPUS * (MAX_PERFORMANCE_COUNTERS + 1)]; 47 int mFds[NR_CPUS * (MAX_PERFORMANCE_COUNTERS + 1)];
50 PerfBuffer *const mPb; 48 PerfBuffer *const mPb;
diff --git a/daemon/PerfSource.cpp b/daemon/PerfSource.cpp
index ecfaa66..1f1cb19 100644
--- a/daemon/PerfSource.cpp
+++ b/daemon/PerfSource.cpp
@@ -37,7 +37,7 @@ static bool sendTracepointFormat(Buffer *const buffer, const char *const name, D
37 return true; 37 return true;
38} 38}
39 39
40PerfSource::PerfSource(sem_t *senderSem, sem_t *startProfile) : mSummary(0, FRAME_SUMMARY, 1024, senderSem), mBuffer(0, FRAME_PERF_ATTRS, 4*1024*1024, senderSem), mCountersBuf(), mCountersGroup(&mCountersBuf), mMonitor(), mUEvent(), mSenderSem(senderSem), mStartProfile(startProfile), mInterruptFd(-1), mIsDone(false) { 40PerfSource::PerfSource(sem_t *senderSem, sem_t *startProfile) : mSummary(0, FRAME_SUMMARY, 1024, senderSem), mBuffer(0, FRAME_PERF_ATTRS, 1024*1024, senderSem), mCountersBuf(), mCountersGroup(&mCountersBuf), mMonitor(), mUEvent(), mSenderSem(senderSem), mStartProfile(startProfile), mInterruptFd(-1), mIsDone(false) {
41 long l = sysconf(_SC_PAGE_SIZE); 41 long l = sysconf(_SC_PAGE_SIZE);
42 if (l < 0) { 42 if (l < 0) {
43 logg->logError(__FILE__, __LINE__, "Unable to obtain the page size"); 43 logg->logError(__FILE__, __LINE__, "Unable to obtain the page size");
@@ -74,9 +74,6 @@ bool PerfSource::prepare() {
74 DynBuf b3; 74 DynBuf b3;
75 long long schedSwitchId; 75 long long schedSwitchId;
76 76
77 // Reread cpuinfo since cores may have changed since startup
78 gSessionData->readCpuInfo();
79
80 if (0 77 if (0
81 || !mMonitor.init() 78 || !mMonitor.init()
82 || !mUEvent.init() 79 || !mUEvent.init()
@@ -86,14 +83,14 @@ bool PerfSource::prepare() {
86 || !sendTracepointFormat(&mBuffer, SCHED_SWITCH, &printb, &b1) 83 || !sendTracepointFormat(&mBuffer, SCHED_SWITCH, &printb, &b1)
87 84
88 // Only want RAW but not IP on sched_switch and don't want TID on SAMPLE_ID 85 // Only want RAW but not IP on sched_switch and don't want TID on SAMPLE_ID
89 || !mCountersGroup.add(&mBuffer, 100/**/, PERF_TYPE_TRACEPOINT, schedSwitchId, 1, PERF_SAMPLE_RAW, PERF_GROUP_MMAP | PERF_GROUP_COMM | PERF_GROUP_TASK | PERF_GROUP_SAMPLE_ID_ALL | PERF_GROUP_PER_CPU) 86 || !mCountersGroup.add(&mBuffer, 100/**/, PERF_TYPE_TRACEPOINT, schedSwitchId, 1, PERF_SAMPLE_RAW, PERF_GROUP_MMAP | PERF_GROUP_COMM | PERF_GROUP_TASK | PERF_GROUP_SAMPLE_ID_ALL)
90 87
91 // Only want TID and IP but not RAW on timer 88 // Only want TID and IP but not RAW on timer
92 || (gSessionData->mSampleRate > 0 && !gSessionData->mIsEBS && !mCountersGroup.add(&mBuffer, 99/**/, PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_CLOCK, 1000000000UL / gSessionData->mSampleRate, PERF_SAMPLE_TID | PERF_SAMPLE_IP, PERF_GROUP_PER_CPU)) 89 || (gSessionData->mSampleRate > 0 && !gSessionData->mIsEBS && !mCountersGroup.add(&mBuffer, 99/**/, PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_CLOCK, 1000000000UL / gSessionData->mSampleRate, PERF_SAMPLE_TID | PERF_SAMPLE_IP, 0))
93 90
94 || !gSessionData->perf.enable(&mCountersGroup, &mBuffer) 91 || !gSessionData->perf.enable(&mCountersGroup, &mBuffer)
95 || 0) { 92 || 0) {
96 logg->logMessage("%s(%s:%i): perf setup failed, are you running Linux 3.4 or later?", __FUNCTION__, __FILE__, __LINE__); 93 logg->logMessage("%s(%s:%i): perf setup failed, are you running Linux 3.12 or later?", __FUNCTION__, __FILE__, __LINE__);
97 return false; 94 return false;
98 } 95 }
99 96
@@ -137,7 +134,7 @@ bool PerfSource::prepare() {
137 return false; 134 return false;
138 } 135 }
139 136
140 if (!readProc(&mBuffer, true, &printb, &b1, &b2, &b3)) { 137 if (!readProc(&mBuffer, &printb, &b1, &b2, &b3)) {
141 logg->logMessage("%s(%s:%i): readProc failed", __FUNCTION__, __FILE__, __LINE__); 138 logg->logMessage("%s(%s:%i): readProc failed", __FUNCTION__, __FILE__, __LINE__);
142 return false; 139 return false;
143 } 140 }
@@ -263,7 +260,6 @@ bool PerfSource::isDone () {
263void PerfSource::write (Sender *sender) { 260void PerfSource::write (Sender *sender) {
264 if (!mSummary.isDone()) { 261 if (!mSummary.isDone()) {
265 mSummary.write(sender); 262 mSummary.write(sender);
266 gSessionData->mSentSummary = true;
267 } 263 }
268 if (!mBuffer.isDone()) { 264 if (!mBuffer.isDone()) {
269 mBuffer.write(sender); 265 mBuffer.write(sender);
diff --git a/daemon/Proc.cpp b/daemon/Proc.cpp
index 9f01770..e0b9e22 100644
--- a/daemon/Proc.cpp
+++ b/daemon/Proc.cpp
@@ -57,57 +57,14 @@ static bool readProcStat(ProcStat *const ps, const char *const pathname, DynBuf
57 return true; 57 return true;
58} 58}
59 59
60static const char *readProcExe(DynBuf *const printb, const int pid, const int tid, DynBuf *const b) { 60static bool readProcTask(Buffer *const buffer, const int pid, const char *const image, DynBuf *const printb, DynBuf *const b) {
61 if (tid == -1 ? !printb->printf("/proc/%i/exe", pid)
62 : !printb->printf("/proc/%i/task/%i/exe", pid, tid)) {
63 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__);
64 return NULL;
65 }
66
67 const int err = b->readlink(printb->getBuf());
68 const char *image;
69 if (err == 0) {
70 image = strrchr(b->getBuf(), '/');
71 if (image == NULL) {
72 image = b->getBuf();
73 } else {
74 ++image;
75 }
76 } else if (err == -ENOENT) {
77 // readlink /proc/[pid]/exe returns ENOENT for kernel threads
78 image = "\0";
79 } else {
80 logg->logMessage("%s(%s:%i): DynBuf::readlink failed", __FUNCTION__, __FILE__, __LINE__);
81 return NULL;
82 }
83
84 // Android apps are run by app_process but the cmdline is changed to reference the actual app name
85 if (strcmp(image, "app_process") != 0) {
86 return image;
87 }
88
89 if (tid == -1 ? !printb->printf("/proc/%i/cmdline", pid)
90 : !printb->printf("/proc/%i/task/%i/cmdline", pid, tid)) {
91 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__);
92 return NULL;
93 }
94
95 if (!b->read(printb->getBuf())) {
96 logg->logMessage("%s(%s:%i): DynBuf::read failed, likely because the thread exited", __FUNCTION__, __FILE__, __LINE__);
97 return NULL;
98 }
99
100 return b->getBuf();
101}
102
103static bool readProcTask(Buffer *const buffer, const int pid, DynBuf *const printb, DynBuf *const b1, DynBuf *const b2) {
104 bool result = false; 61 bool result = false;
105 62
106 if (!b1->printf("/proc/%i/task", pid)) { 63 if (!b->printf("/proc/%i/task", pid)) {
107 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__); 64 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__);
108 return result; 65 return result;
109 } 66 }
110 DIR *task = opendir(b1->getBuf()); 67 DIR *task = opendir(b->getBuf());
111 if (task == NULL) { 68 if (task == NULL) {
112 logg->logMessage("%s(%s:%i): opendir failed", __FUNCTION__, __FILE__, __LINE__); 69 logg->logMessage("%s(%s:%i): opendir failed", __FUNCTION__, __FILE__, __LINE__);
113 return result; 70 return result;
@@ -127,17 +84,11 @@ static bool readProcTask(Buffer *const buffer, const int pid, DynBuf *const prin
127 goto fail; 84 goto fail;
128 } 85 }
129 ProcStat ps; 86 ProcStat ps;
130 if (!readProcStat(&ps, printb->getBuf(), b1)) { 87 if (!readProcStat(&ps, printb->getBuf(), b)) {
131 logg->logMessage("%s(%s:%i): readProcStat failed", __FUNCTION__, __FILE__, __LINE__); 88 logg->logMessage("%s(%s:%i): readProcStat failed", __FUNCTION__, __FILE__, __LINE__);
132 goto fail; 89 goto fail;
133 } 90 }
134 91
135 const char *const image = readProcExe(printb, pid, tid, b2);
136 if (image == NULL) {
137 logg->logMessage("%s(%s:%i): readImage failed", __FUNCTION__, __FILE__, __LINE__);
138 goto fail;
139 }
140
141 buffer->comm(pid, tid, image, ps.comm); 92 buffer->comm(pid, tid, image, ps.comm);
142 } 93 }
143 94
@@ -149,7 +100,7 @@ static bool readProcTask(Buffer *const buffer, const int pid, DynBuf *const prin
149 return result; 100 return result;
150} 101}
151 102
152bool readProc(Buffer *const buffer, bool sendMaps, DynBuf *const printb, DynBuf *const b1, DynBuf *const b2, DynBuf *const b3) { 103bool readProc(Buffer *const buffer, DynBuf *const printb, DynBuf *const b1, DynBuf *const b2, DynBuf *const b3) {
153 bool result = false; 104 bool result = false;
154 105
155 DIR *proc = opendir("/proc"); 106 DIR *proc = opendir("/proc");
@@ -177,29 +128,42 @@ bool readProc(Buffer *const buffer, bool sendMaps, DynBuf *const printb, DynBuf
177 goto fail; 128 goto fail;
178 } 129 }
179 130
180 if (sendMaps) { 131 if (!printb->printf("/proc/%i/exe", pid)) {
181 if (!printb->printf("/proc/%i/maps", pid)) { 132 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__);
182 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__); 133 goto fail;
183 goto fail;
184 }
185 if (!b2->read(printb->getBuf())) {
186 logg->logMessage("%s(%s:%i): DynBuf::read failed, likely because the process exited", __FUNCTION__, __FILE__, __LINE__);
187 // This is not a fatal error - the process just doesn't exist any more
188 continue;
189 }
190
191 buffer->maps(pid, pid, b2->getBuf());
192 } 134 }
193 if (ps.numThreads <= 1) { 135 const int err = b1->readlink(printb->getBuf());
194 const char *const image = readProcExe(printb, pid, -1, b1); 136 const char *image;
137 if (err == 0) {
138 image = strrchr(b1->getBuf(), '/');
195 if (image == NULL) { 139 if (image == NULL) {
196 logg->logMessage("%s(%s:%i): readImage failed", __FUNCTION__, __FILE__, __LINE__); 140 image = b1->getBuf();
197 goto fail; 141 } else {
142 ++image;
198 } 143 }
144 } else if (err == -ENOENT) {
145 // readlink /proc/[pid]/exe returns ENOENT for kernel threads
146 image = "\0";
147 } else {
148 logg->logMessage("%s(%s:%i): DynBuf::readlink failed", __FUNCTION__, __FILE__, __LINE__);
149 goto fail;
150 }
199 151
152 if (!printb->printf("/proc/%i/maps", pid)) {
153 logg->logMessage("%s(%s:%i): DynBuf::printf failed", __FUNCTION__, __FILE__, __LINE__);
154 goto fail;
155 }
156 if (!b2->read(printb->getBuf())) {
157 logg->logMessage("%s(%s:%i): DynBuf::read failed, likely because the process exited", __FUNCTION__, __FILE__, __LINE__);
158 // This is not a fatal error - the process just doesn't exist any more
159 continue;
160 }
161
162 buffer->maps(pid, pid, b2->getBuf());
163 if (ps.numThreads <= 1) {
200 buffer->comm(pid, pid, image, ps.comm); 164 buffer->comm(pid, pid, image, ps.comm);
201 } else { 165 } else {
202 if (!readProcTask(buffer, pid, printb, b1, b3)) { 166 if (!readProcTask(buffer, pid, image, printb, b3)) {
203 logg->logMessage("%s(%s:%i): readProcTask failed", __FUNCTION__, __FILE__, __LINE__); 167 logg->logMessage("%s(%s:%i): readProcTask failed", __FUNCTION__, __FILE__, __LINE__);
204 goto fail; 168 goto fail;
205 } 169 }
diff --git a/daemon/Proc.h b/daemon/Proc.h
index 31c2eec..057b610 100644
--- a/daemon/Proc.h
+++ b/daemon/Proc.h
@@ -12,6 +12,6 @@
12class Buffer; 12class Buffer;
13class DynBuf; 13class DynBuf;
14 14
15bool readProc(Buffer *const buffer, bool sendMaps, DynBuf *const printb, DynBuf *const b1, DynBuf *const b2, DynBuf *const b3); 15bool readProc(Buffer *const buffer, DynBuf *const printb, DynBuf *const b1, DynBuf *const b2, DynBuf *const b3);
16 16
17#endif // PROC_H 17#endif // PROC_H
diff --git a/daemon/Sender.h b/daemon/Sender.h
index 33b6cc3..4c359db 100644
--- a/daemon/Sender.h
+++ b/daemon/Sender.h
@@ -39,4 +39,4 @@ private:
39 Sender &operator=(const Sender &); 39 Sender &operator=(const Sender &);
40}; 40};
41 41
42#endif //__SENDER_H__ 42#endif //__SENDER_H__
diff --git a/daemon/SessionData.cpp b/daemon/SessionData.cpp
index 14d995f..c169299 100644
--- a/daemon/SessionData.cpp
+++ b/daemon/SessionData.cpp
@@ -9,7 +9,6 @@
9#include "SessionData.h" 9#include "SessionData.h"
10 10
11#include <string.h> 11#include <string.h>
12#include <sys/mman.h>
13 12
14#include "SessionXML.h" 13#include "SessionXML.h"
15#include "Logging.h" 14#include "Logging.h"
@@ -28,15 +27,6 @@ void SessionData::initialize() {
28 mSessionIsActive = false; 27 mSessionIsActive = false;
29 mLocalCapture = false; 28 mLocalCapture = false;
30 mOneShot = false; 29 mOneShot = false;
31 mSentSummary = false;
32 const size_t cpuIdSize = sizeof(int)*NR_CPUS;
33 // Share mCpuIds across all instances of gatord
34 mCpuIds = (int *)mmap(NULL, cpuIdSize, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_ANONYMOUS, -1, 0);
35 if (mCpuIds == MAP_FAILED) {
36 logg->logError(__FILE__, __LINE__, "Unable to mmap shared memory for cpuids");
37 handleException();
38 }
39 memset(mCpuIds, -1, cpuIdSize);
40 readCpuInfo(); 30 readCpuInfo();
41 mConfigurationXMLPath = NULL; 31 mConfigurationXMLPath = NULL;
42 mSessionXMLPath = NULL; 32 mSessionXMLPath = NULL;
@@ -101,9 +91,10 @@ void SessionData::parseSessionXML(char* xmlString) {
101void SessionData::readCpuInfo() { 91void SessionData::readCpuInfo() {
102 char temp[256]; // arbitrarily large amount 92 char temp[256]; // arbitrarily large amount
103 strcpy(mCoreName, "unknown"); 93 strcpy(mCoreName, "unknown");
94 memset(&mCpuIds, -1, sizeof(mCpuIds));
104 mMaxCpuId = -1; 95 mMaxCpuId = -1;
105 96
106 FILE* f = fopen("/proc/cpuinfo", "r"); 97 FILE* f = fopen("/proc/cpuinfo", "r");
107 if (f == NULL) { 98 if (f == NULL) {
108 logg->logMessage("Error opening /proc/cpuinfo\n" 99 logg->logMessage("Error opening /proc/cpuinfo\n"
109 "The core name in the captured xml file will be 'unknown'."); 100 "The core name in the captured xml file will be 'unknown'.");
@@ -111,18 +102,10 @@ void SessionData::readCpuInfo() {
111 } 102 }
112 103
113 bool foundCoreName = false; 104 bool foundCoreName = false;
114 int processor = -1; 105 int processor = 0;
115 while (fgets(temp, sizeof(temp), f)) { 106 while (fgets(temp, sizeof(temp), f)) {
116 const size_t len = strlen(temp); 107 if (strlen(temp) > 0) {
117 108 temp[strlen(temp) - 1] = 0; // Replace the line feed with a null
118 if (len == 1) {
119 // New section, clear the processor. Streamline will not know the cpus if the pre Linux 3.8 format of cpuinfo is encountered but also that no incorrect information will be transmitted.
120 processor = -1;
121 continue;
122 }
123
124 if (len > 0) {
125 temp[len - 1] = '\0'; // Replace the line feed with a null
126 } 109 }
127 110
128 const bool foundHardware = strstr(temp, "Hardware") != 0; 111 const bool foundHardware = strstr(temp, "Hardware") != 0;
@@ -144,15 +127,10 @@ void SessionData::readCpuInfo() {
144 } 127 }
145 128
146 if (foundCPUPart) { 129 if (foundCPUPart) {
147 const int cpuId = strtol(position, NULL, 0); 130 mCpuIds[processor] = strtol(position, NULL, 0);
148 // If this does not have the full topology in /proc/cpuinfo, mCpuIds[0] may not have the 1 CPU part emitted - this guarantees it's in mMaxCpuId 131 // If this does not have the full topology in /proc/cpuinfo, mCpuIds[0] may not have the 1 CPU part emitted - this guarantees it's in mMaxCpuId
149 if (cpuId > mMaxCpuId) { 132 if (mCpuIds[processor] > mMaxCpuId) {
150 mMaxCpuId = cpuId; 133 mMaxCpuId = mCpuIds[processor];
151 }
152 if (processor >= NR_CPUS) {
153 logg->logMessage("Too many processors, please increase NR_CPUS");
154 } else if (processor >= 0) {
155 mCpuIds[processor] = cpuId;
156 } 134 }
157 } 135 }
158 136
@@ -164,23 +142,10 @@ void SessionData::readCpuInfo() {
164 142
165 if (!foundCoreName) { 143 if (!foundCoreName) {
166 logg->logMessage("Could not determine core name from /proc/cpuinfo\n" 144 logg->logMessage("Could not determine core name from /proc/cpuinfo\n"
167 "The core name in the captured xml file will be 'unknown'."); 145 "The core name in the captured xml file will be 'unknown'.");
168 } 146 }
169 fclose(f); 147 fclose(f);
170} 148 }
171
172uint64_t getTime() {
173 struct timespec ts;
174#ifndef CLOCK_MONOTONIC_RAW
175 // Android doesn't have this defined but it was added in Linux 2.6.28
176#define CLOCK_MONOTONIC_RAW 4
177#endif
178 if (clock_gettime(CLOCK_MONOTONIC_RAW, &ts) != 0) {
179 logg->logError(__FILE__, __LINE__, "Failed to get uptime");
180 handleException();
181 }
182 return (NS_PER_S*ts.tv_sec + ts.tv_nsec);
183}
184 149
185int getEventKey() { 150int getEventKey() {
186 // key 0 is reserved as a timestamp 151 // key 0 is reserved as a timestamp
diff --git a/daemon/SessionData.h b/daemon/SessionData.h
index 835082d..ea34240 100644
--- a/daemon/SessionData.h
+++ b/daemon/SessionData.h
@@ -13,16 +13,12 @@
13 13
14#include "Config.h" 14#include "Config.h"
15#include "Counter.h" 15#include "Counter.h"
16#include "FSDriver.h"
17#include "Hwmon.h" 16#include "Hwmon.h"
18#include "MaliVideoDriver.h"
19#include "PerfDriver.h" 17#include "PerfDriver.h"
20 18
21#define PROTOCOL_VERSION 19 19#define PROTOCOL_VERSION 18
22#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions 20#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions
23 21
24#define NS_PER_S ((uint64_t)1000000000)
25
26struct ImageLinkList { 22struct ImageLinkList {
27 char* path; 23 char* path;
28 struct ImageLinkList *next; 24 struct ImageLinkList *next;
@@ -36,12 +32,9 @@ public:
36 ~SessionData(); 32 ~SessionData();
37 void initialize(); 33 void initialize();
38 void parseSessionXML(char* xmlString); 34 void parseSessionXML(char* xmlString);
39 void readCpuInfo();
40 35
41 Hwmon hwmon; 36 Hwmon hwmon;
42 FSDriver fsDriver;
43 PerfDriver perf; 37 PerfDriver perf;
44 MaliVideoDriver maliVideo;
45 38
46 char mCoreName[MAX_STRING_LEN]; 39 char mCoreName[MAX_STRING_LEN];
47 struct ImageLinkList *mImages; 40 struct ImageLinkList *mImages;
@@ -56,8 +49,7 @@ public:
56 bool mLocalCapture; 49 bool mLocalCapture;
57 bool mOneShot; // halt processing of the driver data until profiling is complete or the buffer is filled 50 bool mOneShot; // halt processing of the driver data until profiling is complete or the buffer is filled
58 bool mIsEBS; 51 bool mIsEBS;
59 bool mSentSummary; 52
60
61 int mBacktraceDepth; 53 int mBacktraceDepth;
62 int mTotalBufferSize; // number of MB to use for the entire collection buffer 54 int mTotalBufferSize; // number of MB to use for the entire collection buffer
63 int mSampleRate; 55 int mSampleRate;
@@ -65,7 +57,7 @@ public:
65 int mDuration; 57 int mDuration;
66 int mCores; 58 int mCores;
67 int mPageSize; 59 int mPageSize;
68 int *mCpuIds; 60 int mCpuIds[NR_CPUS];
69 int mMaxCpuId; 61 int mMaxCpuId;
70 62
71 // PMU Counters 63 // PMU Counters
@@ -73,6 +65,8 @@ public:
73 Counter mCounters[MAX_PERFORMANCE_COUNTERS]; 65 Counter mCounters[MAX_PERFORMANCE_COUNTERS];
74 66
75private: 67private:
68 void readCpuInfo();
69
76 // Intentionally unimplemented 70 // Intentionally unimplemented
77 SessionData(const SessionData &); 71 SessionData(const SessionData &);
78 SessionData &operator=(const SessionData &); 72 SessionData &operator=(const SessionData &);
@@ -80,7 +74,6 @@ private:
80 74
81extern SessionData* gSessionData; 75extern SessionData* gSessionData;
82 76
83uint64_t getTime();
84int getEventKey(); 77int getEventKey();
85 78
86#endif // SESSION_DATA_H 79#endif // SESSION_DATA_H
diff --git a/daemon/SessionXML.cpp b/daemon/SessionXML.cpp
index 8cdc940..55b2f92 100644
--- a/daemon/SessionXML.cpp
+++ b/daemon/SessionXML.cpp
@@ -17,15 +17,15 @@
17#include "SessionData.h" 17#include "SessionData.h"
18 18
19static const char* TAG_SESSION = "session"; 19static const char* TAG_SESSION = "session";
20static const char* TAG_IMAGE = "image"; 20static const char* TAG_IMAGE = "image";
21 21
22static const char* ATTR_VERSION = "version"; 22static const char* ATTR_VERSION = "version";
23static const char* ATTR_CALL_STACK_UNWINDING = "call_stack_unwinding"; 23static const char* ATTR_CALL_STACK_UNWINDING = "call_stack_unwinding";
24static const char* ATTR_BUFFER_MODE = "buffer_mode"; 24static const char* ATTR_BUFFER_MODE = "buffer_mode";
25static const char* ATTR_SAMPLE_RATE = "sample_rate"; 25static const char* ATTR_SAMPLE_RATE = "sample_rate";
26static const char* ATTR_DURATION = "duration"; 26static const char* ATTR_DURATION = "duration";
27static const char* ATTR_PATH = "path"; 27static const char* ATTR_PATH = "path";
28static const char* ATTR_LIVE_RATE = "live_rate"; 28static const char* ATTR_LIVE_RATE = "live_rate";
29 29
30SessionXML::SessionXML(const char *str) { 30SessionXML::SessionXML(const char *str) {
31 parameters.buffer_mode[0] = 0; 31 parameters.buffer_mode[0] = 0;
diff --git a/daemon/StreamlineSetup.cpp b/daemon/StreamlineSetup.cpp
index 2b61eae..caa665e 100644
--- a/daemon/StreamlineSetup.cpp
+++ b/daemon/StreamlineSetup.cpp
@@ -266,7 +266,7 @@ void StreamlineSetup::writeConfiguration(char* xml) {
266 { ConfigurationXML configuration; } 266 { ConfigurationXML configuration; }
267 267
268 if (gSessionData->mCounterOverflow > 0) { 268 if (gSessionData->mCounterOverflow > 0) {
269 logg->logError(__FILE__, __LINE__, "Only %i performance counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow); 269 logg->logError(__FILE__, __LINE__, "Only %i performance counters counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
270 handleException(); 270 handleException();
271 } 271 }
272} 272}
diff --git a/daemon/StreamlineSetup.h b/daemon/StreamlineSetup.h
index b380f46..74bb197 100644
--- a/daemon/StreamlineSetup.h
+++ b/daemon/StreamlineSetup.h
@@ -21,7 +21,7 @@ enum {
21 COMMAND_APC_START = 2, 21 COMMAND_APC_START = 2,
22 COMMAND_APC_STOP = 3, 22 COMMAND_APC_STOP = 3,
23 COMMAND_DISCONNECT = 4, 23 COMMAND_DISCONNECT = 4,
24 COMMAND_PING = 5 24 COMMAND_PING = 5
25}; 25};
26 26
27class StreamlineSetup { 27class StreamlineSetup {
@@ -47,4 +47,4 @@ private:
47 StreamlineSetup &operator=(const StreamlineSetup &); 47 StreamlineSetup &operator=(const StreamlineSetup &);
48}; 48};
49 49
50#endif //__STREAMLINE_SETUP_H__ 50#endif //__STREAMLINE_SETUP_H__
diff --git a/daemon/UEvent.cpp b/daemon/UEvent.cpp
index 54d4575..d977cd0 100644
--- a/daemon/UEvent.cpp
+++ b/daemon/UEvent.cpp
@@ -8,11 +8,11 @@
8 8
9#include "UEvent.h" 9#include "UEvent.h"
10 10
11#include <string.h>
12#include <sys/socket.h> 11#include <sys/socket.h>
13#include <unistd.h>
14
15#include <linux/netlink.h> 12#include <linux/netlink.h>
13#include <string.h>
14
15#include <unistd.h>
16 16
17#include "Logging.h" 17#include "Logging.h"
18 18
diff --git a/daemon/UserSpaceSource.cpp b/daemon/UserSpaceSource.cpp
index 8c328e0..debe696 100644
--- a/daemon/UserSpaceSource.cpp
+++ b/daemon/UserSpaceSource.cpp
@@ -16,6 +16,7 @@
16#include "Logging.h" 16#include "Logging.h"
17#include "SessionData.h" 17#include "SessionData.h"
18 18
19#define NS_PER_S ((uint64_t)1000000000)
19#define NS_PER_US 1000 20#define NS_PER_US 1000
20 21
21extern Child *child; 22extern Child *child;
@@ -34,7 +35,6 @@ void UserSpaceSource::run() {
34 prctl(PR_SET_NAME, (unsigned long)&"gatord-counters", 0, 0, 0); 35 prctl(PR_SET_NAME, (unsigned long)&"gatord-counters", 0, 0, 0);
35 36
36 gSessionData->hwmon.start(); 37 gSessionData->hwmon.start();
37 gSessionData->fsDriver.start();
38 38
39 int64_t monotonic_started = 0; 39 int64_t monotonic_started = 0;
40 while (monotonic_started <= 0) { 40 while (monotonic_started <= 0) {
@@ -48,7 +48,16 @@ void UserSpaceSource::run() {
48 48
49 uint64_t next_time = 0; 49 uint64_t next_time = 0;
50 while (gSessionData->mSessionIsActive) { 50 while (gSessionData->mSessionIsActive) {
51 const uint64_t curr_time = getTime() - monotonic_started; 51 struct timespec ts;
52#ifndef CLOCK_MONOTONIC_RAW
53 // Android doesn't have this defined but it was added in Linux 2.6.28
54#define CLOCK_MONOTONIC_RAW 4
55#endif
56 if (clock_gettime(CLOCK_MONOTONIC_RAW, &ts) != 0) {
57 logg->logError(__FILE__, __LINE__, "Failed to get uptime");
58 handleException();
59 }
60 const uint64_t curr_time = (NS_PER_S*ts.tv_sec + ts.tv_nsec) - monotonic_started;
52 // Sample ten times a second ignoring gSessionData->mSampleRate 61 // Sample ten times a second ignoring gSessionData->mSampleRate
53 next_time += NS_PER_S/10;//gSessionData->mSampleRate; 62 next_time += NS_PER_S/10;//gSessionData->mSampleRate;
54 if (next_time < curr_time) { 63 if (next_time < curr_time) {
@@ -58,7 +67,6 @@ void UserSpaceSource::run() {
58 67
59 if (mBuffer.eventHeader(curr_time)) { 68 if (mBuffer.eventHeader(curr_time)) {
60 gSessionData->hwmon.read(&mBuffer); 69 gSessionData->hwmon.read(&mBuffer);
61 gSessionData->fsDriver.read(&mBuffer);
62 // Only check after writing all counters so that time and corresponding counters appear in the same frame 70 // Only check after writing all counters so that time and corresponding counters appear in the same frame
63 mBuffer.check(curr_time); 71 mBuffer.check(curr_time);
64 } 72 }
diff --git a/daemon/UserSpaceSource.h b/daemon/UserSpaceSource.h
index 9b36660..fb5889d 100644
--- a/daemon/UserSpaceSource.h
+++ b/daemon/UserSpaceSource.h
@@ -14,7 +14,7 @@
14#include "Buffer.h" 14#include "Buffer.h"
15#include "Source.h" 15#include "Source.h"
16 16
17// User space counters 17// User space counters - currently just hwmon
18class UserSpaceSource : public Source { 18class UserSpaceSource : public Source {
19public: 19public:
20 UserSpaceSource(sem_t *senderSem); 20 UserSpaceSource(sem_t *senderSem);
diff --git a/daemon/common.mk b/daemon/common.mk
index 769a92e..d9dc146 100644
--- a/daemon/common.mk
+++ b/daemon/common.mk
@@ -5,17 +5,16 @@
5# -Werror treats warnings as errors 5# -Werror treats warnings as errors
6# -std=c++0x is the planned new c++ standard 6# -std=c++0x is the planned new c++ standard
7# -std=c++98 is the 1998 c++ standard 7# -std=c++98 is the 1998 c++ standard
8CPPFLAGS += -O3 -Wall -fno-exceptions -pthread -MMD -DETCDIR=\"/etc\" -Ilibsensors 8CFLAGS += -O3 -Wall -fno-exceptions -pthread -MMD -DETCDIR=\"/etc\" -Ilibsensors
9CXXFLAGS += -fno-rtti -Wextra # -Weffc++ 9CXXFLAGS += -fno-rtti -Wextra # -Weffc++
10ifeq ($(WERROR),1) 10ifeq ($(WERROR),1)
11 CPPFLAGS += -Werror 11 CFLAGS += -Werror
12endif 12endif
13# -s strips the binary of debug info 13# -s strips the binary of debug info
14LDFLAGS += -s 14LDFLAGS += -s
15LDLIBS += -lrt -lm -pthread
16TARGET = gatord 15TARGET = gatord
17C_SRC = $(wildcard mxml/*.c) $(wildcard libsensors/*.c) 16C_SRC = $(wildcard mxml/*.c) $(wildcard libsensors/*.c)
18CXX_SRC = $(wildcard *.cpp) 17CPP_SRC = $(wildcard *.cpp)
19 18
20all: $(TARGET) 19all: $(TARGET)
21 20
@@ -36,15 +35,14 @@ libsensors/conf-parse.c: ;
36 ./escape $< > $@ 35 ./escape $< > $@
37 36
38%.o: %.c 37%.o: %.c
39 $(CC) $(CFLAGS) $(CPPFLAGS) -c -o $@ $< 38 $(GCC) -c $(CFLAGS) -o $@ $<
40 39
41%.o: %.cpp 40%.o: %.cpp
42 $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $< 41 $(CPP) -c $(CFLAGS) $(CXXFLAGS) -o $@ $<
43 42
44$(TARGET): $(CXX_SRC:%.cpp=%.o) $(C_SRC:%.c=%.o) 43$(TARGET): $(CPP_SRC:%.cpp=%.o) $(C_SRC:%.c=%.o)
45 $(CC) $(LDFLAGS) $^ $(LDLIBS) -o $@ 44 $(CPP) $(LDFLAGS) -o $@ $^ -lrt -pthread
46 45
47# Intentionally ignore CC as a native binary is required
48escape: escape.c 46escape: escape.c
49 gcc $^ -o $@ 47 gcc $^ -o $@
50 48
diff --git a/daemon/defaults.xml b/daemon/defaults.xml
index 39a0f65..5bf096c 100644
--- a/daemon/defaults.xml
+++ b/daemon/defaults.xml
@@ -58,10 +58,5 @@
58 <configuration counter="Linux_meminfo_memused"/> 58 <configuration counter="Linux_meminfo_memused"/>
59 <configuration counter="Linux_meminfo_memfree"/> 59 <configuration counter="Linux_meminfo_memfree"/>
60 <configuration counter="Linux_power_cpu_freq"/> 60 <configuration counter="Linux_power_cpu_freq"/>
61 <configuration counter="ARM_Mali-4xx_fragment"/>
62 <configuration counter="ARM_Mali-4xx_vertex"/>
63 <configuration counter="ARM_Mali-T6xx_fragment" cores="1"/>
64 <configuration counter="ARM_Mali-T6xx_vertex" cores="1"/>
65 <configuration counter="ARM_Mali-T6xx_opencl" cores="1"/>
66 <configuration counter="L2C-310_cnt0" event="0x1"/> 61 <configuration counter="L2C-310_cnt0" event="0x1"/>
67</configurations> 62</configurations>
diff --git a/daemon/defaults_xml.h b/daemon/defaults_xml.h
new file mode 100644
index 0000000..b00e814
--- /dev/null
+++ b/daemon/defaults_xml.h
@@ -0,0 +1,306 @@
1static const unsigned char defaults_xml[] = {
2 0x3c, 0x3f, 0x78, 0x6d, 0x6c, 0x20, 0x76, 0x65, 0x72, 0x73, 0x69, 0x6f,
3 0x6e, 0x3d, 0x22, 0x31, 0x2e, 0x30, 0x22, 0x20, 0x65, 0x6e, 0x63, 0x6f,
4 0x64, 0x69, 0x6e, 0x67, 0x3d, 0x22, 0x55, 0x54, 0x46, 0x2d, 0x38, 0x22,
5 0x3f, 0x3e, 0x0a, 0x3c, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72,
6 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x20, 0x72, 0x65, 0x76, 0x69, 0x73,
7 0x69, 0x6f, 0x6e, 0x3d, 0x22, 0x33, 0x22, 0x3e, 0x0a, 0x20, 0x20, 0x3c,
8 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f,
9 0x6e, 0x20, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x65, 0x72, 0x3d, 0x22, 0x41,
10 0x52, 0x4d, 0x5f, 0x41, 0x52, 0x4d, 0x31, 0x31, 0x5f, 0x63, 0x63, 0x6e,
11 0x74, 0x22, 0x20, 0x65, 0x76, 0x65, 0x6e, 0x74, 0x3d, 0x22, 0x30, 0x78,
12 0x66, 0x66, 0x22, 0x2f, 0x3e, 0x0a, 0x20, 0x20, 0x3c, 0x63, 0x6f, 0x6e,
13 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x63,
14 0x6f, 0x75, 0x6e, 0x74, 0x65, 0x72, 0x3d, 0x22, 0x41, 0x52, 0x4d, 0x5f,
15 0x41, 0x52, 0x4d, 0x31, 0x31, 0x5f, 0x63, 0x6e, 0x74, 0x30, 0x22, 0x20,
16 0x65, 0x76, 0x65, 0x6e, 0x74, 0x3d, 0x22, 0x30, 0x78, 0x37, 0x22, 0x2f,
17 0x3e, 0x0a, 0x20, 0x20, 0x3c, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75,
18 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x63, 0x6f, 0x75, 0x6e, 0x74,
19 0x65, 0x72, 0x3d, 0x22, 0x41, 0x52, 0x4d, 0x5f, 0x41, 0x52, 0x4d, 0x31,
20 0x31, 0x5f, 0x63, 0x6e, 0x74, 0x31, 0x22, 0x20, 0x65, 0x76, 0x65, 0x6e,
21 0x74, 0x3d, 0x22, 0x30, 0x78, 0x62, 0x22, 0x2f, 0x3e, 0x0a, 0x20, 0x20,
22 0x3c, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69,
23 0x6f, 0x6e, 0x20, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x65, 0x72, 0x3d, 0x22,
24 0x41, 0x52, 0x4d, 0x5f, 0x41, 0x52, 0x4d, 0x31, 0x31, 0x4d, 0x50, 0x43,
25 0x6f, 0x72, 0x65, 0x5f, 0x63, 0x63, 0x6e, 0x74, 0x22, 0x20, 0x65, 0x76,
26 0x65, 0x6e, 0x74, 0x3d, 0x22, 0x30, 0x78, 0x66, 0x66, 0x22, 0x2f, 0x3e,
27 0x0a, 0x20, 0x20, 0x3c, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72,
28 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x65,
29 0x72, 0x3d, 0x22, 0x41, 0x52, 0x4d, 0x5f, 0x41, 0x52, 0x4d, 0x31, 0x31,
30 0x4d, 0x50, 0x43, 0x6f, 0x72, 0x65, 0x5f, 0x63, 0x6e, 0x74, 0x30, 0x22,
31 0x20, 0x65, 0x76, 0x65, 0x6e, 0x74, 0x3d, 0x22, 0x30, 0x78, 0x30, 0x38,
32 0x22, 0x2f, 0x3e, 0x0a, 0x20, 0x20, 0x3c, 0x63, 0x6f, 0x6e, 0x66, 0x69,
33 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x63, 0x6f, 0x75,
34 0x6e, 0x74, 0x65, 0x72, 0x3d, 0x22, 0x41, 0x52, 0x4d, 0x5f, 0x41, 0x52,
35 0x4d, 0x31, 0x31, 0x4d, 0x50, 0x43, 0x6f, 0x72, 0x65, 0x5f, 0x63, 0x6e,
36 0x74, 0x31, 0x22, 0x20, 0x65, 0x76, 0x65, 0x6e, 0x74, 0x3d, 0x22, 0x30,
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293 0x5f, 0x6d, 0x65, 0x6d, 0x69, 0x6e, 0x66, 0x6f, 0x5f, 0x6d, 0x65, 0x6d,
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297 0x6e, 0x75, 0x78, 0x5f, 0x70, 0x6f, 0x77, 0x65, 0x72, 0x5f, 0x63, 0x70,
298 0x75, 0x5f, 0x66, 0x72, 0x65, 0x71, 0x22, 0x2f, 0x3e, 0x0a, 0x20, 0x20,
299 0x3c, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69,
300 0x6f, 0x6e, 0x20, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x65, 0x72, 0x3d, 0x22,
301 0x4c, 0x32, 0x43, 0x2d, 0x33, 0x31, 0x30, 0x5f, 0x63, 0x6e, 0x74, 0x30,
302 0x22, 0x20, 0x65, 0x76, 0x65, 0x6e, 0x74, 0x3d, 0x22, 0x30, 0x78, 0x31,
303 0x22, 0x2f, 0x3e, 0x0a, 0x3c, 0x2f, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67,
304 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3e, 0x0a, 0x00
305};
306static const unsigned int defaults_xml_len = 3634;
diff --git a/daemon/escape b/daemon/escape
new file mode 100644
index 0000000..99f38e8
--- /dev/null
+++ b/daemon/escape
Binary files differ
diff --git a/daemon/escape.c b/daemon/escape.c
index 2b0863a..c54aa1c 100644
--- a/daemon/escape.c
+++ b/daemon/escape.c
@@ -6,7 +6,7 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9/* 9/*
10 * The Makefile in the daemon folder builds and executes 'escape' 10 * The Makefile in the daemon folder builds and executes 'escape'
11 * 'escape' creates configuration_xml.h from configuration.xml and events_xml.h from events-*.xml 11 * 'escape' creates configuration_xml.h from configuration.xml and events_xml.h from events-*.xml
12 * these genereated xml files are then #included and built as part of the gatord binary 12 * these genereated xml files are then #included and built as part of the gatord binary
diff --git a/daemon/events-CCI-400.xml b/daemon/events-CCI-400.xml
index 20002ef..4fa7711 100644
--- a/daemon/events-CCI-400.xml
+++ b/daemon/events-CCI-400.xml
@@ -1,6 +1,7 @@
1 <counter_set name="CCI_400_cnt" count="4"/> 1 <counter_set name="cci-400_cnt" count="4"/>
2 <category name="CCI-400" counter_set="CCI_400_cnt" per_cpu="no" supports_event_based_sampling="yes"> 2 <category name="CCI-400" counter_set="cci-400_cnt" per_cpu="no" supports_event_based_sampling="yes">
3 <event counter="CCI_400_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="cci-400_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
4
4 <option_set name="Slave"> 5 <option_set name="Slave">
5 <option event_delta="0x00" name="S0" description="Slave interface 0"/> 6 <option event_delta="0x00" name="S0" description="Slave interface 0"/>
6 <option event_delta="0x20" name="S1" description="Slave interface 1"/> 7 <option event_delta="0x20" name="S1" description="Slave interface 1"/>
@@ -8,6 +9,7 @@
8 <option event_delta="0x60" name="S3" description="Slave interface 3"/> 9 <option event_delta="0x60" name="S3" description="Slave interface 3"/>
9 <option event_delta="0x80" name="S4" description="Slave interface 4"/> 10 <option event_delta="0x80" name="S4" description="Slave interface 4"/>
10 </option_set> 11 </option_set>
12
11 <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/> 13 <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/>
12 <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/> 14 <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/>
13 <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/> 15 <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/>
@@ -28,11 +30,13 @@
28 <event event="0x11" option_set="Slave" title="CCI-400" name="Write: WriteLineUnique" description="Write request handshake: WriteLineUnique"/> 30 <event event="0x11" option_set="Slave" title="CCI-400" name="Write: WriteLineUnique" description="Write request handshake: WriteLineUnique"/>
29 <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/> 31 <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/>
30 <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/> 32 <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/>
33
31 <option_set name="Master"> 34 <option_set name="Master">
32 <option event_delta="0xa0" name="M0" description="Master interface 0"/> 35 <option event_delta="0xa0" name="M0" description="Master interface 0"/>
33 <option event_delta="0xc0" name="M1" description="Master interface 1"/> 36 <option event_delta="0xc0" name="M1" description="Master interface 1"/>
34 <option event_delta="0xe0" name="M2" description="Master interface 2"/> 37 <option event_delta="0xe0" name="M2" description="Master interface 2"/>
35 </option_set> 38 </option_set>
39
36 <event event="0x14" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/> 40 <event event="0x14" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/>
37 <event event="0x15" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Read request stall cycle because of an address hazard"/> 41 <event event="0x15" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Read request stall cycle because of an address hazard"/>
38 <event event="0x16" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of an ID hazard"/> 42 <event event="0x16" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of an ID hazard"/>
@@ -41,9 +45,11 @@
41 <event event="0x19" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/> 45 <event event="0x19" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/>
42 <event event="0x1a" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase MIx_W_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/> 46 <event event="0x1a" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase MIx_W_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/>
43 </category> 47 </category>
44 <counter_set name="CCI_400-r1_cnt" count="4"/> 48
45 <category name="CCI-400" counter_set="CCI_400-r1_cnt" per_cpu="no" supports_event_based_sampling="yes"> 49 <counter_set name="cci-400-r1_cnt" count="4"/>
46 <event counter="CCI_400-r1_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 50 <category name="CCI-400" counter_set="cci-400-r1_cnt" per_cpu="no" supports_event_based_sampling="yes">
51 <event counter="cci-400-r1_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
52
47 <option_set name="Slave"> 53 <option_set name="Slave">
48 <option event_delta="0x00" name="S0" description="Slave interface 0"/> 54 <option event_delta="0x00" name="S0" description="Slave interface 0"/>
49 <option event_delta="0x20" name="S1" description="Slave interface 1"/> 55 <option event_delta="0x20" name="S1" description="Slave interface 1"/>
@@ -51,6 +57,7 @@
51 <option event_delta="0x60" name="S3" description="Slave interface 3"/> 57 <option event_delta="0x60" name="S3" description="Slave interface 3"/>
52 <option event_delta="0x80" name="S4" description="Slave interface 4"/> 58 <option event_delta="0x80" name="S4" description="Slave interface 4"/>
53 </option_set> 59 </option_set>
60
54 <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/> 61 <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/>
55 <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/> 62 <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/>
56 <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/> 63 <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/>
@@ -72,11 +79,13 @@
72 <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/> 79 <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/>
73 <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/> 80 <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/>
74 <event event="0x14" option_set="Slave" title="CCI-400" name="Read stall: slave hazard" description="Read request stall cycle because of a slave interface ID hazard"/> 81 <event event="0x14" option_set="Slave" title="CCI-400" name="Read stall: slave hazard" description="Read request stall cycle because of a slave interface ID hazard"/>
82
75 <option_set name="Master"> 83 <option_set name="Master">
76 <option event_delta="0xa0" name="M0" description="Master interface 0"/> 84 <option event_delta="0xa0" name="M0" description="Master interface 0"/>
77 <option event_delta="0xc0" name="M1" description="Master interface 1"/> 85 <option event_delta="0xc0" name="M1" description="Master interface 1"/>
78 <option event_delta="0xe0" name="M2" description="Master interface 2"/> 86 <option event_delta="0xe0" name="M2" description="Master interface 2"/>
79 </option_set> 87 </option_set>
88
80 <event event="0x00" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/> 89 <event event="0x00" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/>
81 <event event="0x01" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Stall cycle because of an address hazard. A read or write invalidation is stalled because of an outstanding transaction to an overlapping address"/> 90 <event event="0x01" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Stall cycle because of an address hazard. A read or write invalidation is stalled because of an outstanding transaction to an overlapping address"/>
82 <event event="0x02" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of a master interface ID hazard"/> 91 <event event="0x02" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of a master interface ID hazard"/>
diff --git a/daemon/events-CCN-504.xml b/daemon/events-CCN-504.xml
index 6ef3e64..cfabf65 100644
--- a/daemon/events-CCN-504.xml
+++ b/daemon/events-CCN-504.xml
@@ -1,6 +1,7 @@
1 <counter_set name="CCN-504_cnt" count="4"/> 1 <counter_set name="CCN-504_cnt" count="4"/>
2 <category name="CCN-504" counter_set="CCN-504_cnt"> 2 <category name="CCN-504" counter_set="CCN-504_cnt">
3 <event counter="CCN-504_ccnt" title="CCN-504 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> 3 <event counter="CCN-504_ccnt" title="CCN-504 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
4
4 <option_set name="XP_Region"> 5 <option_set name="XP_Region">
5 <option event_delta="0x400000" name="XP 0" description="Crosspoint 0"/> 6 <option event_delta="0x400000" name="XP 0" description="Crosspoint 0"/>
6 <option event_delta="0x410000" name="XP 1" description="Crosspoint 1"/> 7 <option event_delta="0x410000" name="XP 1" description="Crosspoint 1"/>
@@ -14,6 +15,7 @@
14 <option event_delta="0x490000" name="XP 9" description="Crosspoint 9"/> 15 <option event_delta="0x490000" name="XP 9" description="Crosspoint 9"/>
15 <option event_delta="0x4A0000" name="XP 10" description="Crosspoint 10"/> 16 <option event_delta="0x4A0000" name="XP 10" description="Crosspoint 10"/>
16 </option_set> 17 </option_set>
18
17 <event event="0x0801" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: H-bit" description="Bus 0: REQ: Set H-bit, signaled when this XP sets the H-bit."/> 19 <event event="0x0801" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: H-bit" description="Bus 0: REQ: Set H-bit, signaled when this XP sets the H-bit."/>
18 <event event="0x0802" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: S-bit" description="Bus 0: REQ: Set S-bit, signaled when this XP sets the S-bit."/> 20 <event event="0x0802" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: S-bit" description="Bus 0: REQ: Set S-bit, signaled when this XP sets the S-bit."/>
19 <event event="0x0803" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: P-Cnt" description="Bus 0: REQ: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/> 21 <event event="0x0803" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: P-Cnt" description="Bus 0: REQ: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
@@ -54,6 +56,7 @@
54 <event event="0x087A" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: S-bit" description="Bus 1: DATB: Set S-bit, signaled when this XP sets the S-bit."/> 56 <event event="0x087A" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: S-bit" description="Bus 1: DATB: Set S-bit, signaled when this XP sets the S-bit."/>
55 <event event="0x087B" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: P-Cnt" description="Bus 1: DATB: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/> 57 <event event="0x087B" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: P-Cnt" description="Bus 1: DATB: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
56 <event event="0x087C" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: TknV" description="Bus 1: DATB: No TknV, signaled when this XP transmits a valid packet."/> 58 <event event="0x087C" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: TknV" description="Bus 1: DATB: No TknV, signaled when this XP transmits a valid packet."/>
59
57 <option_set name="HN-F_Region"> 60 <option_set name="HN-F_Region">
58 <option event_delta="0x200000" name="HN-F 3" description="Fully-coherent Home Node 3"/> 61 <option event_delta="0x200000" name="HN-F 3" description="Fully-coherent Home Node 3"/>
59 <option event_delta="0x210000" name="HN-F 5" description="Fully-coherent Home Node 5"/> 62 <option event_delta="0x210000" name="HN-F 5" description="Fully-coherent Home Node 5"/>
@@ -64,6 +67,7 @@
64 <option event_delta="0x260000" name="HN-F 17" description="Fully-coherent Home Node 17"/> 67 <option event_delta="0x260000" name="HN-F 17" description="Fully-coherent Home Node 17"/>
65 <option event_delta="0x270000" name="HN-F 18" description="Fully-coherent Home Node 18"/> 68 <option event_delta="0x270000" name="HN-F 18" description="Fully-coherent Home Node 18"/>
66 </option_set> 69 </option_set>
70
67 <event event="0x0401" option_set="HN-F_Region" title="CCN-504" name="Cache Miss" description="Counts the total cache misses. This is the first time lookup result, and is high priority."/> 71 <event event="0x0401" option_set="HN-F_Region" title="CCN-504" name="Cache Miss" description="Counts the total cache misses. This is the first time lookup result, and is high priority."/>
68 <event event="0x0402" option_set="HN-F_Region" title="CCN-504" name="L3 SF Cache Access" description="Counts the number of cache accesses. This is the first time access, and is high priority."/> 72 <event event="0x0402" option_set="HN-F_Region" title="CCN-504" name="L3 SF Cache Access" description="Counts the number of cache accesses. This is the first time access, and is high priority."/>
69 <event event="0x0403" option_set="HN-F_Region" title="CCN-504" name="Cache Fill" description="Counts the total allocations in the HN L3 cache, and all cache line allocations to the L3 cache."/> 73 <event event="0x0403" option_set="HN-F_Region" title="CCN-504" name="Cache Fill" description="Counts the total allocations in the HN L3 cache, and all cache line allocations to the L3 cache."/>
@@ -78,6 +82,7 @@
78 <event event="0x040C" option_set="HN-F_Region" title="CCN-504" name="MC Retries" description="Counts the number of transactions retried by the memory controller."/> 82 <event event="0x040C" option_set="HN-F_Region" title="CCN-504" name="MC Retries" description="Counts the number of transactions retried by the memory controller."/>
79 <event event="0x040D" option_set="HN-F_Region" title="CCN-504" name="MC Reqs" description="Counts the number of requests to the memory controller."/> 83 <event event="0x040D" option_set="HN-F_Region" title="CCN-504" name="MC Reqs" description="Counts the number of requests to the memory controller."/>
80 <event event="0x040E" option_set="HN-F_Region" title="CCN-504" name="QOS HH Retry" description="Counts the number of times a highest-priority QoS class was retried at the HN-F."/> 84 <event event="0x040E" option_set="HN-F_Region" title="CCN-504" name="QOS HH Retry" description="Counts the number of times a highest-priority QoS class was retried at the HN-F."/>
85
81 <option_set name="RN-I_Region"> 86 <option_set name="RN-I_Region">
82 <option event_delta="0x800000" name="RN-I 0" description="I/O-coherent Requesting Node 0"/> 87 <option event_delta="0x800000" name="RN-I 0" description="I/O-coherent Requesting Node 0"/>
83 <option event_delta="0x820000" name="RN-I 2" description="I/O-coherent Requesting Node 2"/> 88 <option event_delta="0x820000" name="RN-I 2" description="I/O-coherent Requesting Node 2"/>
@@ -86,6 +91,7 @@
86 <option event_delta="0x900000" name="RN-I 16" description="I/O-coherent Requesting Node 16"/> 91 <option event_delta="0x900000" name="RN-I 16" description="I/O-coherent Requesting Node 16"/>
87 <option event_delta="0x940000" name="RN-I 20" description="I/O-coherent Requesting Node 20"/> 92 <option event_delta="0x940000" name="RN-I 20" description="I/O-coherent Requesting Node 20"/>
88 </option_set> 93 </option_set>
94
89 <event event="0x1601" option_set="RN-I_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/> 95 <event event="0x1601" option_set="RN-I_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/>
90 <event event="0x1602" option_set="RN-I_Region" title="CCN-504" name="S1 RDataBeats" description="S1 RDataBeats."/> 96 <event event="0x1602" option_set="RN-I_Region" title="CCN-504" name="S1 RDataBeats" description="S1 RDataBeats."/>
91 <event event="0x1603" option_set="RN-I_Region" title="CCN-504" name="S2 RDataBeats" description="S2 RDataBeats."/> 97 <event event="0x1603" option_set="RN-I_Region" title="CCN-504" name="S2 RDataBeats" description="S2 RDataBeats."/>
@@ -96,12 +102,14 @@
96 <event event="0x1608" option_set="RN-I_Region" title="CCN-504" name="RRT full" description="RRT full."/> 102 <event event="0x1608" option_set="RN-I_Region" title="CCN-504" name="RRT full" description="RRT full."/>
97 <event event="0x1609" option_set="RN-I_Region" title="CCN-504" name="WRT full" description="WRT full."/> 103 <event event="0x1609" option_set="RN-I_Region" title="CCN-504" name="WRT full" description="WRT full."/>
98 <event event="0x160A" option_set="RN-I_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/> 104 <event event="0x160A" option_set="RN-I_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/>
105
99 <option_set name="SBAS_Region"> 106 <option_set name="SBAS_Region">
100 <option event_delta="0x810000" name="SBAS 1" description="ACE master to CHI protocol bridge 1"/> 107 <option event_delta="0x810000" name="SBAS 1" description="ACE master to CHI protocol bridge 1"/>
101 <option event_delta="0x890000" name="SBAS 9" description="ACE master to CHI protocol bridge 9"/> 108 <option event_delta="0x890000" name="SBAS 9" description="ACE master to CHI protocol bridge 9"/>
102 <option event_delta="0x8B0000" name="SBAS 11" description="ACE master to CHI protocol bridge 11"/> 109 <option event_delta="0x8B0000" name="SBAS 11" description="ACE master to CHI protocol bridge 11"/>
103 <option event_delta="0x930000" name="SBAS 19" description="ACE master to CHI protocol bridge 19"/> 110 <option event_delta="0x930000" name="SBAS 19" description="ACE master to CHI protocol bridge 19"/>
104 </option_set> 111 </option_set>
112
105 <event event="0x1001" option_set="SBAS_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/> 113 <event event="0x1001" option_set="SBAS_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/>
106 <event event="0x1004" option_set="SBAS_Region" title="CCN-504" name="RXDAT Flits received" description="RXDAT Flits received."/> 114 <event event="0x1004" option_set="SBAS_Region" title="CCN-504" name="RXDAT Flits received" description="RXDAT Flits received."/>
107 <event event="0x1005" option_set="SBAS_Region" title="CCN-504" name="TXDAT Flits sent" description="TXDAT Flits sent."/> 115 <event event="0x1005" option_set="SBAS_Region" title="CCN-504" name="TXDAT Flits sent" description="TXDAT Flits sent."/>
@@ -110,4 +118,5 @@
110 <event event="0x1008" option_set="SBAS_Region" title="CCN-504" name="RRT full" description="RRT full."/> 118 <event event="0x1008" option_set="SBAS_Region" title="CCN-504" name="RRT full" description="RRT full."/>
111 <event event="0x1009" option_set="SBAS_Region" title="CCN-504" name="WRT full" description="WRT full."/> 119 <event event="0x1009" option_set="SBAS_Region" title="CCN-504" name="WRT full" description="WRT full."/>
112 <event event="0x100A" option_set="SBAS_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/> 120 <event event="0x100A" option_set="SBAS_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/>
121
113 </category> 122 </category>
diff --git a/daemon/events-Cortex-A53.xml b/daemon/events-Cortex-A53.xml
index 5ba1790..577dcd9 100644
--- a/daemon/events-Cortex-A53.xml
+++ b/daemon/events-Cortex-A53.xml
@@ -1,87 +1,171 @@
1 <counter_set name="ARM_Cortex-A53_cnt" count="6"/> 1 <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
2 <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <!-- 0x11 CPU_CYCLES - Cycle -->
3 <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/> 4 <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
5 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
9 <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 10 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
11 <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
7 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
8 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 14 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
9 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
10 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/> 18 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
19 <!-- 0x09 EXC_TAKEN - Exception taken -->
11 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
12 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 22 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
23 <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
13 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 24 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
25 <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
14 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/> 26 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
15 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
29 <!-- 0x13 MEM_ACCESS - Data memory access -->
16 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/> 30 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
17 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/> 32 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
18 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/> 34 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
35 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
19 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/> 36 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
20 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/> 38 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
21 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/> 40 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
41 <!-- 0x19 BUS_ACCESS - Bus access -->
22 <event event="0x19" title="Bus" name="Access" description="Bus access"/> 42 <event event="0x19" title="Bus" name="Access" description="Bus access"/>
43 <!-- 0x1A MEMORY_ERROR - Local memory error -->
23 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/> 44 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
45 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
24 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/> 46 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
25 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/> 48 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
49 <!-- 0x1D BUS_CYCLES - Bus cycle -->
26 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/> 50 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
51 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
27 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/> 52 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
28 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/> 54 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
29 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/> 56 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
30 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/> 58 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
31 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/> 60 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
32 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/> 62 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
33 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/> 64 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
34 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/> 66 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
35 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/> 68 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
36 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/> 70 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
37 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/> 72 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
38 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/> 74 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
39 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/> 76 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
40 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/> 78 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
41 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/> 80 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
42 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/> 82 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
43 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/> 84 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
44 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/> 86 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
45 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/> 88 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
46 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/> 90 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
47 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/> 92 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
48 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/> 94 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
49 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/> 96 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
50 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/> 98 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
51 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/> 100 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
52 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/> 102 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
53 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/> 104 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
54 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/> 106 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
55 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/> 108 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
56 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/> 110 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
57 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/> 112 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
58 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/> 114 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
59 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/> 116 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
60 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/> 118 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
61 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/> 120 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
62 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/> 122 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
63 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/> 124 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
64 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/> 126 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
65 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/> 128 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
66 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/> 130 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
67 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/> 132 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
68 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/> 134 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
69 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/> 136 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
70 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/> 138 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
71 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/> 140 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
72 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/> 142 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
73 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/> 144 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
74 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/> 146 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
75 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/> 148 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
76 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/> 150 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
77 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/> 152 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
78 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/> 154 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
79 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/> 156 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
80 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/> 158 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
81 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/> 160 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
82 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/> 162 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
83 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/> 164 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
84 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/> 166 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
85 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/> 168 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
86 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/> 170 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
87 </category> 171 </category>
diff --git a/daemon/events-Cortex-A57.xml b/daemon/events-Cortex-A57.xml
index fbe96c2..b7178c0 100644
--- a/daemon/events-Cortex-A57.xml
+++ b/daemon/events-Cortex-A57.xml
@@ -1,87 +1,171 @@
1 <counter_set name="ARM_Cortex-A57_cnt" count="6"/> 1 <counter_set name="ARM_Cortex-A57_cnt" count="6"/>
2 <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes"> 2 <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <!-- 0x11 CPU_CYCLES - Cycle -->
3 <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/> 4 <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
5 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
4 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> 6 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
7 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> 8 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
9 <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> 10 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
11 <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
7 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/> 12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
13 <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
8 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/> 14 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
15 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
9 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/> 16 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
17 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
10 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/> 18 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
19 <!-- 0x09 EXC_TAKEN - Exception taken -->
11 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/> 20 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
21 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
12 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/> 22 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
23 <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
13 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/> 24 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
25 <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
14 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/> 26 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
27 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
15 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/> 28 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
29 <!-- 0x13 MEM_ACCESS - Data memory access -->
16 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/> 30 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
31 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
17 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/> 32 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
33 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
18 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/> 34 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
35 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
19 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/> 36 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
37 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
20 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/> 38 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
39 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
21 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/> 40 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
41 <!-- 0x19 BUS_ACCESS - Bus access -->
22 <event event="0x19" title="Bus" name="Access" description="Bus access"/> 42 <event event="0x19" title="Bus" name="Access" description="Bus access"/>
43 <!-- 0x1A MEMORY_ERROR - Local memory error -->
23 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/> 44 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
45 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
24 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/> 46 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
47 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
25 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/> 48 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
49 <!-- 0x1D BUS_CYCLES - Bus cycle -->
26 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/> 50 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
51 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
27 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/> 52 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
53 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
28 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/> 54 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
55 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
29 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/> 56 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
57 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
30 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/> 58 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
59 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
31 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/> 60 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
61 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
32 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/> 62 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
63 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
33 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/> 64 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
65 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
34 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/> 66 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
67 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
35 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/> 68 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
69 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
36 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/> 70 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
71 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
37 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/> 72 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
73 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
38 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/> 74 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
75 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
39 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/> 76 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
77 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
40 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/> 78 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
79 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
41 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/> 80 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
81 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
42 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/> 82 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
83 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
43 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/> 84 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
85 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
44 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/> 86 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
87 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
45 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/> 88 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
89 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
46 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/> 90 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
91 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
47 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/> 92 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
93 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
48 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/> 94 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
95 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
49 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/> 96 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
97 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
50 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/> 98 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
99 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
51 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/> 100 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
101 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
52 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/> 102 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
103 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
53 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/> 104 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
105 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
54 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/> 106 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
107 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
55 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/> 108 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
109 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
56 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/> 110 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
111 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
57 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/> 112 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
113 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
58 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/> 114 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
115 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
59 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/> 116 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
117 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
60 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/> 118 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
119 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
61 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/> 120 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
121 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
62 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/> 122 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
123 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
63 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/> 124 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
125 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
64 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/> 126 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
127 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
65 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/> 128 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
129 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
66 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/> 130 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
131 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
67 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/> 132 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
133 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
68 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/> 134 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
135 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
69 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/> 136 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
137 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
70 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/> 138 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
139 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
71 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/> 140 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
141 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
72 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/> 142 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
143 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
73 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/> 144 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
145 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
74 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/> 146 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
147 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
75 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/> 148 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
149 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
76 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/> 150 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
151 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
77 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/> 152 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
153 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
78 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/> 154 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
155 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
79 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/> 156 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
157 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
80 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/> 158 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
159 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
81 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/> 160 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
161 <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
82 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/> 162 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
163 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
83 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/> 164 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
165 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
84 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/> 166 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
167 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
85 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/> 168 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
169 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
86 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/> 170 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
87 </category> 171 </category>
diff --git a/daemon/events-L2C-310.xml b/daemon/events-L2C-310.xml
index 923fb90..4da4d1d 100644
--- a/daemon/events-L2C-310.xml
+++ b/daemon/events-L2C-310.xml
@@ -1,18 +1,18 @@
1 <counter_set name="L2C-310_cnt" count="2"/> 1 <counter_set name="L2C-310_cnt" count="2"/>
2 <category name="L2C-310" counter_set="L2C-310_cnt" per_cpu="no"> 2 <category name="L2C-310" counter_set="L2C-310_cnt" per_cpu="no">
3 <event event="0x1" title="L2 Cache" name="CastOUT" description="Eviction, CastOUT, of a line from the L2 cache"/> 3 <event event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
4 <event event="0x2" title="L2 Cache" name="Data Read Hit" description="Data read hit in the L2 cache"/> 4 <event event="0x2" title="L2 Cache" name="DRH" description="Data read hit"/>
5 <event event="0x3" title="L2 Cache" name="Data Read Request" description="Data read lookup to the L2 cache. Subsequently results in a hit or miss"/> 5 <event event="0x3" title="L2 Cache" name="DRREQ" description="Data read request"/>
6 <event event="0x4" title="L2 Cache" name="Data Write Hit" description="Data write hit in the L2 cache"/> 6 <event event="0x4" title="L2 Cache" name="DWHIT" description="Data write hit"/>
7 <event event="0x5" title="L2 Cache" name="Data Write Request" description="Data write lookup to the L2 cache. Subsequently results in a hit or miss"/> 7 <event event="0x5" title="L2 Cache" name="DWREQ" description="Data write request"/>
8 <event event="0x6" title="L2 Cache" name="Data Write-Through Request" description="Data write lookup to the L2 cache with Write-Through attribute. Subsequently results in a hit or miss"/> 8 <event event="0x6" title="L2 Cache" name="DWTREQ" description="Data write request with write-through attribute"/>
9 <event event="0x7" title="L2 Cache" name="Instruction Read Hit" description="Instruction read hit in the L2 cache"/> 9 <event event="0x7" title="L2 Cache" name="IRHIT" description="Instruction read hit"/>
10 <event event="0x8" title="L2 Cache" name="Instruction Read Request" description="Instruction read lookup to the L2 cache. Subsequently results in a hit or miss"/> 10 <event event="0x8" title="L2 Cache" name="IRREQ" description="Instruction read request"/>
11 <event event="0x9" title="L2 Cache" name="Write Allocate Miss" description="Allocation into the L2 cache caused by a write, with Write-Allocate attribute, miss"/> 11 <event event="0x9" title="L2 Cache" name="WA" description="Write allocate"/>
12 <event event="0xa" title="L2 Cache" name="Internal Prefetch Allocate" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/> 12 <event event="0xa" title="L2 Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
13 <event event="0xb" title="L2 Cache" name="Prefitch Hit" description="Prefetch hint hits in the L2 cache"/> 13 <event event="0xb" title="L2 Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>
14 <event event="0xc" title="L2 Cache" name="Prefitch Allocate" description="Prefetch hint allocated into the L2 cache"/> 14 <event event="0xc" title="L2 Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>
15 <event event="0xd" title="L2 Cache" name="Speculative Read Received" description="Speculative read received"/> 15 <event event="0xd" title="L2 Cache" name="SRRCVD" description="Speculative read received"/>
16 <event event="0xe" title="L2 Cache" name="Speculative Read Confirmed" description="Speculative read confirmed"/> 16 <event event="0xe" title="L2 Cache" name="SRCONF" description="Speculative read confirmed"/>
17 <event event="0xf" title="L2 Cache" name="Prefetch Hint Received" description="Prefetch hint received"/> 17 <event event="0xf" title="L2 Cache" name="EPFRCVD" description="Prefetch hint received"/>
18 </category> 18 </category>
diff --git a/daemon/events-Linux.xml b/daemon/events-Linux.xml
index c306dd6..4d677e1 100644
--- a/daemon/events-Linux.xml
+++ b/daemon/events-Linux.xml
@@ -11,6 +11,7 @@
11 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" class="absolute" units="B" description="Memory used by OS disk buffers"/> 11 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" class="absolute" units="B" description="Memory used by OS disk buffers"/>
12 <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" class="absolute" units="Hz" series_composition="overlay" average_cores="yes" description="Frequency setting of the CPU"/> 12 <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" class="absolute" units="Hz" series_composition="overlay" average_cores="yes" description="Frequency setting of the CPU"/>
13 <event counter="Linux_power_cpu_idle" title="Idle" name="State" per_cpu="yes" class="absolute" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/> 13 <event counter="Linux_power_cpu_idle" title="Idle" name="State" per_cpu="yes" class="absolute" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
14 <event counter="Linux_cpu_wait_contention" title="CPU Contention" name="Wait" per_cpu="no" class="activity" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" color="0x003c96fb" description="Thread waiting on contended resource"/> 14 <event counter="Linux_cpu_wait_contention" title="CPU Contention" name="Wait" per_cpu="no" class="activity" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on contended resource"/>
15 <event counter="Linux_cpu_wait_io" title="CPU I/O" name="Wait" per_cpu="no" class="activity" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" color="0x00b30000" description="Thread waiting on I/O resource"/> 15 <event counter="Linux_cpu_wait_io" title="CPU I/O" name="Wait" per_cpu="no" class="activity" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on I/O resource"/>
16 </category> 16 </category>
17
diff --git a/daemon/events-Mali-4xx.xml b/daemon/events-Mali-4xx.xml
index 0a95dfe..5a71386 100644
--- a/daemon/events-Mali-4xx.xml
+++ b/daemon/events-Mali-4xx.xml
@@ -1,33 +1,34 @@
1 <counter_set name="ARM_Mali-4xx_VP_0_cnt" count="2"/> 1 <counter_set name="ARM_Mali-4xx_VP_0_cnt" count="2"/>
2 <counter_set name="ARM_Mali-4xx_SW_cnt" count="0"/> 2 <counter_set name="ARM_Mali-4xx_SW_cnt" count="0"/>
3 <category name="Mali Vertex Processor" counter_set="ARM_Mali-4xx_VP_0_cnt" per_cpu="no"> 3 <counter_set name="ARM_Mali-4xx_Filmstrip_cnt" count="1"/>
4 <event event="0x01" title="Mali-4xx VP" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active."/> 4 <category name="Mali-4xx-VP" counter_set="ARM_Mali-4xx_VP_0_cnt" per_cpu="no">
5 <event event="0x02" title="Mali-4xx VP" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active."/> 5 <event event="0x01" title="Mali GPU Vertex Processor" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active."/>
6 <event event="0x03" title="Mali-4xx VP" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active."/> 6 <event event="0x02" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active."/>
7 <event event="0x04" title="Mali-4xx VP" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active."/> 7 <event event="0x03" title="Mali GPU Vertex Processor" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active."/>
8 <event event="0x05" title="Mali-4xx VP" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader."/> 8 <event event="0x04" title="Mali GPU Vertex Processor" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active."/>
9 <event event="0x06" title="Mali-4xx VP" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame."/> 9 <event event="0x05" title="Mali GPU Vertex Processor" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader."/>
10 <event event="0x07" title="Mali-4xx VP" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame."/> 10 <event event="0x06" title="Mali GPU Vertex Processor" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame."/>
11 <event event="0x08" title="Mali-4xx VP" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame."/> 11 <event event="0x07" title="Mali GPU Vertex Processor" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame."/>
12 <event event="0x09" title="Mali-4xx VP" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame."/> 12 <event event="0x08" title="Mali GPU Vertex Processor" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame."/>
13 <event event="0x0a" title="Mali-4xx VP" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame."/> 13 <event event="0x09" title="Mali GPU Vertex Processor" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame."/>
14 <event event="0x0b" title="Mali-4xx VP" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame."/> 14 <event event="0x0a" title="Mali GPU Vertex Processor" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame."/>
15 <event event="0x0c" title="Mali-4xx VP" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame."/> 15 <event event="0x0b" title="Mali GPU Vertex Processor" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame."/>
16 <event event="0x0e" title="Mali-4xx VP" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen."/> 16 <event event="0x0c" title="Mali GPU Vertex Processor" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame."/>
17 <event event="0x0f" title="Mali-4xx VP" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame."/> 17 <event event="0x0e" title="Mali GPU Vertex Processor" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen."/>
18 <event event="0x10" title="Mali-4xx VP" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame ."/> 18 <event event="0x0f" title="Mali GPU Vertex Processor" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame."/>
19 <event event="0x13" title="Mali-4xx VP" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame."/> 19 <event event="0x10" title="Mali GPU Vertex Processor" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame ."/>
20 <event event="0x16" title="Mali-4xx VP" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/> 20 <event event="0x13" title="Mali GPU Vertex Processor" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame."/>
21 <event event="0x17" title="Mali-4xx VP" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores."/> 21 <event event="0x16" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/>
22 <event event="0x18" title="Mali-4xx VP" name="Active Cycles, PLBU list writer" description="Number of cycles per frame the MaliGP2 PLBU output unit was active. This includes time spent waiting on the bus."/> 22 <event event="0x17" title="Mali GPU Vertex Processor" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores."/>
23 <event event="0x19" title="Mali-4xx VP" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus."/> 23 <event event="0x18" title="Mali GPU Vertex Processor" name="MaliGP2 PLBU cycles per frame" description="Number of cycles per frame the MaliGP2 PLBU output unit was active. This includes time spent waiting on the bus."/>
24 <event event="0x1b" title="Mali-4xx VP" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus."/> 24 <event event="0x19" title="Mali GPU Vertex Processor" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus."/>
25 <event event="0x1c" title="Mali-4xx VP" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus."/> 25 <event event="0x1b" title="Mali GPU Vertex Processor" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus."/>
26 <event event="0x1e" title="Mali-4xx VP" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus."/> 26 <event event="0x1c" title="Mali GPU Vertex Processor" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus."/>
27 <event event="0x20" title="Mali-4xx VP" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoring. This includes time spent waiting on the bus."/> 27 <event event="0x1e" title="Mali GPU Vertex Processor" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
28 <event event="0x21" title="Mali-4xx VP" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus."/> 28 <event event="0x20" title="Mali GPU Vertex Processor" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoring. This includes time spent waiting on the bus."/>
29 <event event="0x21" title="Mali GPU Vertex Processor" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
29 </category> 30 </category>
30 <category name="Mali Fragment Processor" per_cpu="no"> 31 <category name="Mali GPU Fragment Processor" per_cpu="no">
31 <counter_set name="ARM_Mali-4xx_FP_0_cnt" title="Mali-4xx FP0" description="Mali GPU Fragment Processor 0" count="2"/> 32 <counter_set name="ARM_Mali-4xx_FP_0_cnt" title="Mali-4xx FP0" description="Mali GPU Fragment Processor 0" count="2"/>
32 <counter_set name="ARM_Mali-4xx_FP_1_cnt" title="Mali-4xx FP1" description="Mali GPU Fragment Processor 1" count="2"/> 33 <counter_set name="ARM_Mali-4xx_FP_1_cnt" title="Mali-4xx FP1" description="Mali GPU Fragment Processor 1" count="2"/>
33 <counter_set name="ARM_Mali-4xx_FP_2_cnt" title="Mali-4xx FP2" description="Mali GPU Fragment Processor 2" count="2"/> 34 <counter_set name="ARM_Mali-4xx_FP_2_cnt" title="Mali-4xx FP2" description="Mali GPU Fragment Processor 2" count="2"/>
@@ -36,6 +37,7 @@
36 <counter_set name="ARM_Mali-4xx_FP_5_cnt" title="Mali-4xx FP5" description="Mali GPU Fragment Processor 5" count="2"/> 37 <counter_set name="ARM_Mali-4xx_FP_5_cnt" title="Mali-4xx FP5" description="Mali GPU Fragment Processor 5" count="2"/>
37 <counter_set name="ARM_Mali-4xx_FP_6_cnt" title="Mali-4xx FP6" description="Mali GPU Fragment Processor 6" count="2"/> 38 <counter_set name="ARM_Mali-4xx_FP_6_cnt" title="Mali-4xx FP6" description="Mali GPU Fragment Processor 6" count="2"/>
38 <counter_set name="ARM_Mali-4xx_FP_7_cnt" title="Mali-4xx FP7" description="Mali GPU Fragment Processor 7" count="2"/> 39 <counter_set name="ARM_Mali-4xx_FP_7_cnt" title="Mali-4xx FP7" description="Mali GPU Fragment Processor 7" count="2"/>
40
39 <event event="0x00" title="Mali-4xx FP" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/> 41 <event event="0x00" title="Mali-4xx FP" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
40 <event event="0x02" title="Mali-4xx FP" name="Total bus reads" description="Total number of 64-bit words read from the bus."/> 42 <event event="0x02" title="Mali-4xx FP" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
41 <event event="0x03" title="Mali-4xx FP" name="Total bus writes" description="Total number of 64-bit words written to the bus."/> 43 <event event="0x03" title="Mali-4xx FP" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
@@ -94,10 +96,11 @@
94 <event event="0x3c" title="Mali-4xx FP" name="Program cache hit count" description="Number of hits in the program cache."/> 96 <event event="0x3c" title="Mali-4xx FP" name="Program cache hit count" description="Number of hits in the program cache."/>
95 <event event="0x3d" title="Mali-4xx FP" name="Program cache miss count" description="Number of misses in the program cache."/> 97 <event event="0x3d" title="Mali-4xx FP" name="Program cache miss count" description="Number of misses in the program cache."/>
96 </category> 98 </category>
97 <counter_set name="ARM_Mali-4xx_L2_0_cnt" title="Mali-4xx L2" description="Mali GPU L2 Cache Core 0" count="2"/> 99 <counter_set name="ARM_Mali-4xx_L2_0_cnt" title="Mali-4xx L2 0" description="Mali GPU L2 Cache Core 0" count="2"/>
98 <category name="Mali-4xx L2" counter_set="ARM_Mali-4xx_L2_0_cnt" per_cpu="no"> 100 <category name="Mali-4xx-L2_0" counter_set="ARM_Mali-4xx_L2_0_cnt" per_cpu="no">
99 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/> 101 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
100 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/> 102 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
103
101 <option_set name="All"> 104 <option_set name="All">
102 <option event_delta="0x08" name="Master" description="Master"/> 105 <option event_delta="0x08" name="Master" description="Master"/>
103 <option event_delta="0x10" name="All slaves" description="All slaves"/> 106 <option event_delta="0x10" name="All slaves" description="All slaves"/>
@@ -107,6 +110,7 @@
107 <option event_delta="0x50" name="Slave 3" description="Slave 3"/> 110 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
108 <option event_delta="0x60" name="Slave 4" description="Slave 4"/> 111 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
109 </option_set> 112 </option_set>
113
110 <option_set name="Slaves"> 114 <option_set name="Slaves">
111 <option event_delta="0x10" name="All slaves" description="All slaves"/> 115 <option event_delta="0x10" name="All slaves" description="All slaves"/>
112 <option event_delta="0x20" name="Slave 0" description="Slave 0"/> 116 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
@@ -115,6 +119,7 @@
115 <option event_delta="0x50" name="Slave 3" description="Slave 3"/> 119 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
116 <option event_delta="0x60" name="Slave 4" description="Slave 4"/> 120 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
117 </option_set> 121 </option_set>
122
118 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/> 123 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
119 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/> 124 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
120 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/> 125 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
@@ -126,9 +131,10 @@
126 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/> 131 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
127 </category> 132 </category>
128 <counter_set name="ARM_Mali-4xx_L2_1_cnt" title="Mali-4xx L2 1" description="Mali GPU L2 Cache Core 1" count="2"/> 133 <counter_set name="ARM_Mali-4xx_L2_1_cnt" title="Mali-4xx L2 1" description="Mali GPU L2 Cache Core 1" count="2"/>
129 <category name="Mali-4xx L2_1" counter_set="ARM_Mali-4xx_L2_1_cnt" per_cpu="no"> 134 <category name="Mali-4xx-L2_1" counter_set="ARM_Mali-4xx_L2_1_cnt" per_cpu="no">
130 <event event="0x01" title="Mali L2 Cache 1" name="Total clock cycles" description="Total clock cycles"/> 135 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
131 <event event="0x02" title="Mali L2 Cache 1" name="Active clock cycles" description="Active clock cycles"/> 136 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
137
132 <option_set name="All"> 138 <option_set name="All">
133 <option event_delta="0x08" name="Master" description="Master"/> 139 <option event_delta="0x08" name="Master" description="Master"/>
134 <option event_delta="0x10" name="All slaves" description="All slaves"/> 140 <option event_delta="0x10" name="All slaves" description="All slaves"/>
@@ -138,6 +144,7 @@
138 <option event_delta="0x50" name="Slave 3" description="Slave 3"/> 144 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
139 <option event_delta="0x60" name="Slave 4" description="Slave 4"/> 145 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
140 </option_set> 146 </option_set>
147
141 <option_set name="Slaves"> 148 <option_set name="Slaves">
142 <option event_delta="0x10" name="All slaves" description="All slaves"/> 149 <option event_delta="0x10" name="All slaves" description="All slaves"/>
143 <option event_delta="0x20" name="Slave 0" description="Slave 0"/> 150 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
@@ -146,20 +153,22 @@
146 <option event_delta="0x50" name="Slave 3" description="Slave 3"/> 153 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
147 <option event_delta="0x60" name="Slave 4" description="Slave 4"/> 154 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
148 </option_set> 155 </option_set>
149 <event event="0x00" option_set="All" title="Mali L2 Cache 1" name="Read transactions" description="Read transactions"/> 156
150 <event event="0x01" option_set="All" title="Mali L2 Cache 1" name="Write transactions" description="Write transactions"/> 157 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
151 <event event="0x02" option_set="All" title="Mali L2 Cache 1" name="Words read" description="Words read"/> 158 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
152 <event event="0x03" option_set="All" title="Mali L2 Cache 1" name="Words written" description="Words written"/> 159 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
153 <event event="0x04" option_set="Slaves" title="Mali L2 Cache 1" name="Read hits" description="Read hits"/> 160 <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
154 <event event="0x05" option_set="Slaves" title="Mali L2 Cache 1" name="Read misses" description="Read misses"/> 161 <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
155 <event event="0x06" option_set="Slaves" title="Mali L2 Cache 1" name="Write invalidates" description="Write invalidates"/> 162 <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
156 <event event="0x07" option_set="Slaves" title="Mali L2 Cache 1" name="Read invalidates" description="Read invalidates"/> 163 <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
157 <event event="0x08" option_set="Slaves" title="Mali L2 Cache 1" name="Cacheable read transactions" description="Cacheable read transactions"/> 164 <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
165 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
158 </category> 166 </category>
159 <counter_set name="ARM_Mali-4xx_L2_2_cnt" title="Mali-4xx L2 2" description="Mali GPU L2 Cache Core 2" count="2"/> 167 <counter_set name="ARM_Mali-4xx_L2_2_cnt" title="Mali-4xx L2 2" description="Mali GPU L2 Cache Core 2" count="2"/>
160 <category name="Mali-4xx L2_2" counter_set="ARM_Mali-4xx_L2_2_cnt" per_cpu="no"> 168 <category name="Mali-4xx-L2_2" counter_set="ARM_Mali-4xx_L2_2_cnt" per_cpu="no">
161 <event event="0x01" title="Mali L2 Cache 2" name="Total clock cycles" description="Total clock cycles"/> 169 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
162 <event event="0x02" title="Mali L2 Cache 2" name="Active clock cycles" description="Active clock cycles"/> 170 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
171
163 <option_set name="All"> 172 <option_set name="All">
164 <option event_delta="0x08" name="Master" description="Master"/> 173 <option event_delta="0x08" name="Master" description="Master"/>
165 <option event_delta="0x10" name="All slaves" description="All slaves"/> 174 <option event_delta="0x10" name="All slaves" description="All slaves"/>
@@ -169,6 +178,7 @@
169 <option event_delta="0x50" name="Slave 3" description="Slave 3"/> 178 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
170 <option event_delta="0x60" name="Slave 4" description="Slave 4"/> 179 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
171 </option_set> 180 </option_set>
181
172 <option_set name="Slaves"> 182 <option_set name="Slaves">
173 <option event_delta="0x10" name="All slaves" description="All slaves"/> 183 <option event_delta="0x10" name="All slaves" description="All slaves"/>
174 <option event_delta="0x20" name="Slave 0" description="Slave 0"/> 184 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
@@ -177,18 +187,18 @@
177 <option event_delta="0x50" name="Slave 3" description="Slave 3"/> 187 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
178 <option event_delta="0x60" name="Slave 4" description="Slave 4"/> 188 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
179 </option_set> 189 </option_set>
180 <event event="0x00" option_set="All" title="Mali L2 Cache 2" name="Read transactions" description="Read transactions"/> 190
181 <event event="0x01" option_set="All" title="Mali L2 Cache 2" name="Write transactions" description="Write transactions"/> 191 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
182 <event event="0x02" option_set="All" title="Mali L2 Cache 2" name="Words read" description="Words read"/> 192 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
183 <event event="0x03" option_set="All" title="Mali L2 Cache 2" name="Words written" description="Words written"/> 193 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
184 <event event="0x04" option_set="Slaves" title="Mali L2 Cache 2" name="Read hits" description="Read hits"/> 194 <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
185 <event event="0x05" option_set="Slaves" title="Mali L2 Cache 2" name="Read misses" description="Read misses"/> 195 <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
186 <event event="0x06" option_set="Slaves" title="Mali L2 Cache 2" name="Write invalidates" description="Write invalidates"/> 196 <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
187 <event event="0x07" option_set="Slaves" title="Mali L2 Cache 2" name="Read invalidates" description="Read invalidates"/> 197 <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
188 <event event="0x08" option_set="Slaves" title="Mali L2 Cache 2" name="Cacheable read transactions" description="Cacheable read transactions"/> 198 <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
199 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
189 </category> 200 </category>
190 <counter_set name="ARM_Mali-4xx_Filmstrip_cnt" count="1"/> 201 <category name="ARM Mali-4xx Filmstrip" counter_set="ARM_Mali-4xx_Filmstrip_cnt" per_cpu="no">
191 <category name="Mali-4xx Filmstrip" counter_set="ARM_Mali-4xx_Filmstrip_cnt" per_cpu="no">
192 <option_set name="fs"> 202 <option_set name="fs">
193 <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/> 203 <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/>
194 <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/> 204 <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/>
@@ -202,11 +212,7 @@
202 <category name="ARM_Mali-4xx_Frequency" per_cpu="no"> 212 <category name="ARM_Mali-4xx_Frequency" per_cpu="no">
203 <event counter="ARM_Mali-4xx_Frequency" title="Mali GPU Frequency" name="Frequency" display="average" average_selection="yes" units="MHz" description="GPU core frequency."/> 213 <event counter="ARM_Mali-4xx_Frequency" title="Mali GPU Frequency" name="Frequency" display="average" average_selection="yes" units="MHz" description="GPU core frequency."/>
204 </category> 214 </category>
205 <category name="Mali-4xx Activity" counter_set="ARM_Mali-4xx_Activity_cnt"> 215 <category name="Mali-4xx-SW" counter_set="ARM_Mali-4xx_SW_cnt" per_cpu="no">
206 <event counter="ARM_Mali-4xx_fragment" title="GPU Fragment" name="Activity" class="activity" activity1="Activity" activity_color1="0x00006fcc" rendering_type="bar" average_selection="yes" average_cores="yes" percentage="yes" description="GPU Fragment Activity"/>
207 <event counter="ARM_Mali-4xx_vertex" title="GPU Vertex" name="Activity" class="activity" activity1="Activity" activity_color1="0x00eda000" rendering_type="bar" average_selection="yes" percentage="yes" description="GPU Vertex Activity"/>
208 </category>
209 <category name="Mali-4xx Software Counters" counter_set="ARM_Mali-4xx_SW_cnt" per_cpu="no">
210 <!-- EGL Counters --> 216 <!-- EGL Counters -->
211 <event counter="ARM_Mali-4xx_SW_0" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the framebuffer from video memory to framebuffer."/> 217 <event counter="ARM_Mali-4xx_SW_0" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the framebuffer from video memory to framebuffer."/>
212 <!-- glDrawElements Counters --> 218 <!-- glDrawElements Counters -->
diff --git a/daemon/events-Mali-T6xx.xml b/daemon/events-Mali-T6xx.xml
index 5e89797..ec9ca00 100644
--- a/daemon/events-Mali-T6xx.xml
+++ b/daemon/events-Mali-T6xx.xml
@@ -1,7 +1,9 @@
1 <category name="Mali-T6xx Software Counters" per_cpu="no"> 1
2 <category name="Mali-T6xx-SW-counters" per_cpu="no">
2 <event counter="ARM_Mali-T6xx_TOTAL_ALLOC_PAGES" title="Mali Total Alloc Pages" name="Total number of allocated pages" description="Mali total number of allocated pages."/> 3 <event counter="ARM_Mali-T6xx_TOTAL_ALLOC_PAGES" title="Mali Total Alloc Pages" name="Total number of allocated pages" description="Mali total number of allocated pages."/>
3 </category> 4 </category>
4 <category name="Mali-T6xx PM Shader" per_cpu="no"> 5
6 <category name="Mali-T6xx-PMShader" per_cpu="no">
5 <event counter="ARM_Mali-T6xx_PM_SHADER_0" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/> 7 <event counter="ARM_Mali-T6xx_PM_SHADER_0" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
6 <event counter="ARM_Mali-T6xx_PM_SHADER_1" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/> 8 <event counter="ARM_Mali-T6xx_PM_SHADER_1" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
7 <event counter="ARM_Mali-T6xx_PM_SHADER_2" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/> 9 <event counter="ARM_Mali-T6xx_PM_SHADER_2" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
@@ -11,27 +13,32 @@
11 <event counter="ARM_Mali-T6xx_PM_SHADER_6" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/> 13 <event counter="ARM_Mali-T6xx_PM_SHADER_6" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
12 <event counter="ARM_Mali-T6xx_PM_SHADER_7" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/> 14 <event counter="ARM_Mali-T6xx_PM_SHADER_7" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
13 </category> 15 </category>
14 <category name="Mali-T6xx PM Tiler" per_cpu="no"> 16
17 <category name="Mali-T6xx-PMTiler" per_cpu="no">
15 <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/> 18 <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
16 </category> 19 </category>
17 <category name="Mali-T6xx PM L2" per_cpu="no"> 20
21 <category name="Mali-T6xx-PML2" per_cpu="no">
18 <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/> 22 <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
19 <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/> 23 <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
20 </category> 24 </category>
21 <category name="Mali-T6xx MMU Address Space" per_cpu="no"> 25
26 <category name="Mali-T6xx-MMU_AS" per_cpu="no">
22 <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/> 27 <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
23 <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/> 28 <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
24 <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/> 29 <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
25 <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/> 30 <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
26 </category> 31 </category>
27 <category name="Mali-T6xx MMU Page Fault" per_cpu="no"> 32
33 <category name="Mali-T6xx-MMU_page_fault" per_cpu="no">
28 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_0" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 0" description="Reports the number of newly allocated pages after a MMU page fault in address space 0."/> 34 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_0" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 0" description="Reports the number of newly allocated pages after a MMU page fault in address space 0."/>
29 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_1" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 1" description="Reports the number of newly allocated pages after a MMU page fault in address space 1."/> 35 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_1" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 1" description="Reports the number of newly allocated pages after a MMU page fault in address space 1."/>
30 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_2" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 2" description="Reports the number of newly allocated pages after a MMU page fault in address space 2."/> 36 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_2" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 2" description="Reports the number of newly allocated pages after a MMU page fault in address space 2."/>
31 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_3" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 3" description="Reports the number of newly allocated pages after a MMU page fault in address space 3."/> 37 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_3" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 3" description="Reports the number of newly allocated pages after a MMU page fault in address space 3."/>
32 </category> 38 </category>
39
33 <counter_set name="ARM_Mali-T6xx_Filmstrip_cnt" count="1"/> 40 <counter_set name="ARM_Mali-T6xx_Filmstrip_cnt" count="1"/>
34 <category name="Mali-T6xx Filmstrip" counter_set="ARM_Mali-T6xx_Filmstrip_cnt" per_cpu="no"> 41 <category name="ARM Mali-T6xx Filmstrip" counter_set="ARM_Mali-T6xx_Filmstrip_cnt" per_cpu="no">
35 <option_set name="fs"> 42 <option_set name="fs">
36 <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/> 43 <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/>
37 <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/> 44 <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/>
@@ -39,8 +46,3 @@
39 </option_set> 46 </option_set>
40 <event event="0x0400" option_set="fs" title="ARM Mali-T6xx" name="Filmstrip" description="Scaled framebuffer"/> 47 <event event="0x0400" option_set="fs" title="ARM Mali-T6xx" name="Filmstrip" description="Scaled framebuffer"/>
41 </category> 48 </category>
42 <category name="Mali-T6xx Activity" per_cpu="no">
43 <event counter="ARM_Mali-T6xx_fragment" title="GPU Fragment" name="Activity" class="activity" activity1="Activity" activity_color1="0x00006fcc" rendering_type="bar" average_selection="yes" percentage="yes" cores="1" description="GPU Job Slot 0 Activity"/>
44 <event counter="ARM_Mali-T6xx_vertex" title="GPU Vertex-Tiling-Compute" name="Activity" class="activity" activity1="Activity" activity_color1="0x00eda000" rendering_type="bar" average_selection="yes" percentage="yes" cores="1" description="GPU Job Slot 1 Activity"/>
45 <event counter="ARM_Mali-T6xx_opencl" title="GPU Vertex-Compute" name="Activity" class="activity" activity1="Activity" activity_color1="0x00ef022f" rendering_type="bar" average_selection="yes" percentage="yes" cores="1" description="GPU Job Slot 2 Activity"/>
46 </category>
diff --git a/daemon/events-Mali-T6xx_hw.xml b/daemon/events-Mali-T6xx_hw.xml
index df27962..03566cb 100644
--- a/daemon/events-Mali-T6xx_hw.xml
+++ b/daemon/events-Mali-T6xx_hw.xml
@@ -1,27 +1,35 @@
1 <category name="Mali-T6xx Job Manager" per_cpu="no"> 1
2 <category name="Mali-T6xx-JobManager" per_cpu="no">
3
2 <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali Job Manager Cycles" name="GPU cycles" description="Number of cycles the GPU was active"/> 4 <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali Job Manager Cycles" name="GPU cycles" description="Number of cycles the GPU was active"/>
3 <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali Job Manager Cycles" name="IRQ cycles" description="Number of cycles the GPU had a pending interrupt"/> 5 <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali Job Manager Cycles" name="IRQ cycles" description="Number of cycles the GPU had a pending interrupt"/>
4 <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali Job Manager Cycles" name="JS0 cycles" description="Number of cycles JS0 (fragment) was active"/> 6 <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali Job Manager Cycles" name="JS0 cycles" description="Number of cycles JS0 (fragment) was active"/>
5 <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali Job Manager Cycles" name="JS1 cycles" description="Number of cycles JS1 (vertex/tiler/compute) was active"/> 7 <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali Job Manager Cycles" name="JS1 cycles" description="Number of cycles JS1 (vertex/tiler/compute) was active"/>
6 <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali Job Manager Cycles" name="JS2 cycles" description="Number of cycles JS2 (vertex/compute) was active"/> 8 <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali Job Manager Cycles" name="JS2 cycles" description="Number of cycles JS2 (vertex/compute) was active"/>
9
7 <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali Job Manager Work" name="JS0 jobs" description="Number of Jobs (fragment) completed in JS0"/> 10 <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali Job Manager Work" name="JS0 jobs" description="Number of Jobs (fragment) completed in JS0"/>
8 <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali Job Manager Work" name="JS0 tasks" description="Number of Tasks completed in JS0"/> 11 <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali Job Manager Work" name="JS0 tasks" description="Number of Tasks completed in JS0"/>
9 <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali Job Manager Work" name="JS1 jobs" description="Number of Jobs (vertex/tiler/compute) completed in JS1"/> 12 <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali Job Manager Work" name="JS1 jobs" description="Number of Jobs (vertex/tiler/compute) completed in JS1"/>
10 <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali Job Manager Work" name="JS1 tasks" description="Number of Tasks completed in JS1"/> 13 <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali Job Manager Work" name="JS1 tasks" description="Number of Tasks completed in JS1"/>
11 <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali Job Manager Work" name="JS2 tasks" description="Number of Tasks completed in JS2"/> 14 <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali Job Manager Work" name="JS2 tasks" description="Number of Tasks completed in JS2"/>
12 <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali Job Manager Work" name="JS2 jobs" description="Number of Jobs (vertex/compute) completed in JS2"/> 15 <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali Job Manager Work" name="JS2 jobs" description="Number of Jobs (vertex/compute) completed in JS2"/>
16
13 </category> 17 </category>
14 <category name="Mali-T6xx Tiler" per_cpu="no"> 18
19 <category name="Mali-T6xx-Tiler" per_cpu="no">
20
15 <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali Tiler Primitives" name="Polygons" description="Number of polygons processed"/> 21 <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali Tiler Primitives" name="Polygons" description="Number of polygons processed"/>
16 <event counter="ARM_Mali-T6xx_QUADS" title="Mali Tiler Primitives" name="Quads" description="Number of quads processed"/> 22 <event counter="ARM_Mali-T6xx_QUADS" title="Mali Tiler Primitives" name="Quads" description="Number of quads processed"/>
17 <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali Tiler Primitives" name="Triangles" description="Number of triangles processed"/> 23 <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali Tiler Primitives" name="Triangles" description="Number of triangles processed"/>
18 <event counter="ARM_Mali-T6xx_LINES" title="Mali Tiler Primitives" name="Lines" description="Number of lines processed"/> 24 <event counter="ARM_Mali-T6xx_LINES" title="Mali Tiler Primitives" name="Lines" description="Number of lines processed"/>
19 <event counter="ARM_Mali-T6xx_POINTS" title="Mali Tiler Primitives" name="Points" description="Number of points processed"/> 25 <event counter="ARM_Mali-T6xx_POINTS" title="Mali Tiler Primitives" name="Points" description="Number of points processed"/>
26
20 <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali Tiler Culling" name="Front facing prims" description="Number of front facing primitives"/> 27 <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali Tiler Culling" name="Front facing prims" description="Number of front facing primitives"/>
21 <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali Tiler Culling" name="Back facing prims" description="Number of back facing primitives"/> 28 <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali Tiler Culling" name="Back facing prims" description="Number of back facing primitives"/>
22 <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali Tiler Culling" name="Visible prims" description="Number of visible primitives"/> 29 <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali Tiler Culling" name="Visible prims" description="Number of visible primitives"/>
23 <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali Tiler Culling" name="Culled prims" description="Number of culled primitives"/> 30 <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali Tiler Culling" name="Culled prims" description="Number of culled primitives"/>
24 <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali Tiler Culling" name="Clipped prims" description="Number of clipped primitives"/> 31 <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali Tiler Culling" name="Clipped prims" description="Number of clipped primitives"/>
32
25 <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali Tiler Hierarchy" name="L0 prims" description="Number of primitives in hierarchy level 0"/> 33 <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali Tiler Hierarchy" name="L0 prims" description="Number of primitives in hierarchy level 0"/>
26 <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali Tiler Hierarchy" name="L1 prims" description="Number of primitives in hierarchy level 1"/> 34 <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali Tiler Hierarchy" name="L1 prims" description="Number of primitives in hierarchy level 1"/>
27 <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali Tiler Hierarchy" name="L2 prims" description="Number of primitives in hierarchy level 2"/> 35 <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali Tiler Hierarchy" name="L2 prims" description="Number of primitives in hierarchy level 2"/>
@@ -30,6 +38,7 @@
30 <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali Tiler Hierarchy" name="L5 prims" description="Number of primitives in hierarchy level 5"/> 38 <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali Tiler Hierarchy" name="L5 prims" description="Number of primitives in hierarchy level 5"/>
31 <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali Tiler Hierarchy" name="L6 prims" description="Number of primitives in hierarchy level 6"/> 39 <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali Tiler Hierarchy" name="L6 prims" description="Number of primitives in hierarchy level 6"/>
32 <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali Tiler Hierarchy" name="L7 prims" description="Number of primitives in hierarchy level 7"/> 40 <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali Tiler Hierarchy" name="L7 prims" description="Number of primitives in hierarchy level 7"/>
41
33 <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali Tiler Commands" name="Prims in 1 command" description="Number of primitives producing 1 command"/> 42 <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali Tiler Commands" name="Prims in 1 command" description="Number of primitives producing 1 command"/>
34 <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali Tiler Commands" name="Prims in 2 command" description="Number of primitives producing 2 commands"/> 43 <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali Tiler Commands" name="Prims in 2 command" description="Number of primitives producing 2 commands"/>
35 <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali Tiler Commands" name="Prims in 3 command" description="Number of primitives producing 3 commands"/> 44 <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali Tiler Commands" name="Prims in 3 command" description="Number of primitives producing 3 commands"/>
@@ -39,36 +48,48 @@
39 <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali Tiler Commands" name="Prims in 8-15 commands" description="Number of primitives producing 8-15 commands"/> 48 <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali Tiler Commands" name="Prims in 8-15 commands" description="Number of primitives producing 8-15 commands"/>
40 <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali Tiler Commands" name="Prims in 16-63 commands" description="Number of primitives producing 16-63 commands"/> 49 <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali Tiler Commands" name="Prims in 16-63 commands" description="Number of primitives producing 16-63 commands"/>
41 <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali Tiler Commands" name="Prims in &gt;= 64 commands" description="Number of primitives producing &gt;= 64 commands"/> 50 <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali Tiler Commands" name="Prims in &gt;= 64 commands" description="Number of primitives producing &gt;= 64 commands"/>
51
42 </category> 52 </category>
43 <category name="Mali-T6xx Shader Core" per_cpu="no"> 53
54 <category name="Mali-T6xx-ShaderCore" per_cpu="no">
55
44 <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Mali Core Cycles" name="Tripipe cycles" description="Number of cycles the Tripipe was active"/> 56 <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Mali Core Cycles" name="Tripipe cycles" description="Number of cycles the Tripipe was active"/>
45 <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Mali Core Cycles" name="Fragment cycles" description="Number of cycles fragment processing was active"/> 57 <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Mali Core Cycles" name="Fragment cycles" description="Number of cycles fragment processing was active"/>
46 <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Mali Core Cycles" name="Compute cycles" description="Number of cycles vertex\compute processing was active"/> 58 <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Mali Core Cycles" name="Compute cycles" description="Number of cycles vertex\compute processing was active"/>
47 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Mali Core Cycles" name="Fragment cycles waiting for tile" description="Number of cycles spent waiting for a physical tile buffer"/> 59 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Mali Core Cycles" name="Fragment cycles waiting for tile" description="Number of cycles spent waiting for a physical tile buffer"/>
60
48 <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Mali Core Threads" name="Fragment threads" description="Number of fragment threads started"/> 61 <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Mali Core Threads" name="Fragment threads" description="Number of fragment threads started"/>
49 <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Mali Core Threads" name="Dummy fragment threads" description="Number of dummy fragment threads started"/> 62 <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Mali Core Threads" name="Dummy fragment threads" description="Number of dummy fragment threads started"/>
50 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/> 63 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
51 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/> 64 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
52 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/> 65 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
53 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/> 66 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
67
54 <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Mali Compute Threads" name="Compute tasks" description="Number of compute tasks"/> 68 <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Mali Compute Threads" name="Compute tasks" description="Number of compute tasks"/>
55 <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Mali Compute Threads" name="Compute threads started" description="Number of compute threads started"/> 69 <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Mali Compute Threads" name="Compute threads started" description="Number of compute threads started"/>
56 <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Mali Compute Threads" name="Compute cycles awaiting descriptors" description="Number of compute cycles spent waiting for descriptors"/> 70 <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Mali Compute Threads" name="Compute cycles awaiting descriptors" description="Number of compute cycles spent waiting for descriptors"/>
71
57 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/> 72 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
58 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/> 73 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
59 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/> 74 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
60 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/> 75 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
76
61 <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Mali Fragment Quads" name="Quads rasterized" description="Number of quads rasterized"/> 77 <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Mali Fragment Quads" name="Quads rasterized" description="Number of quads rasterized"/>
62 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Mali Fragment Quads" name="Quads doing early ZS" description="Number of quads doing early ZS test"/> 78 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Mali Fragment Quads" name="Quads doing early ZS" description="Number of quads doing early ZS test"/>
63 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Mali Fragment Quads" name="Quads killed early Z" description="Number of quads killed by early ZS test"/> 79 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Mali Fragment Quads" name="Quads killed early Z" description="Number of quads killed by early ZS test"/>
80
64 <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Mali Fragment Tasks" name="Tiles rendered" description="Number of tiles rendered"/> 81 <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Mali Fragment Tasks" name="Tiles rendered" description="Number of tiles rendered"/>
65 <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Mali Fragment Tasks" name="Tile writes killed by TE" description="Number of tile writes skipped by transaction elimination"/> 82 <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Mali Fragment Tasks" name="Tile writes killed by TE" description="Number of tile writes skipped by transaction elimination"/>
83
66 <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Mali Arithmetic Pipe" name="A instructions" description="Number of instructions completed by the the A-pipe (normalized per pipeline)"/> 84 <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Mali Arithmetic Pipe" name="A instructions" description="Number of instructions completed by the the A-pipe (normalized per pipeline)"/>
85
67 <event counter="ARM_Mali-T6xx_LS_WORDS" title="Mali Load/Store Pipe" name="LS instructions" description="Number of instructions completed by the LS-pipe"/> 86 <event counter="ARM_Mali-T6xx_LS_WORDS" title="Mali Load/Store Pipe" name="LS instructions" description="Number of instructions completed by the LS-pipe"/>
68 <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Mali Load/Store Pipe" name="LS instruction issues" description="Number of instructions issued to the LS-pipe, including restarts"/> 87 <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Mali Load/Store Pipe" name="LS instruction issues" description="Number of instructions issued to the LS-pipe, including restarts"/>
88
69 <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Mali Texture Pipe" name="T instructions" description="Number of instructions completed by the T-pipe"/> 89 <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Mali Texture Pipe" name="T instructions" description="Number of instructions completed by the T-pipe"/>
70 <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Mali Texture Pipe" name="T instruction issues" description="Number of instructions issused to the T-pipe, including restarts"/> 90 <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Mali Texture Pipe" name="T instruction issues" description="Number of instructions issused to the T-pipe, including restarts"/>
71 <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Mali Texture Pipe" name="Cache misses" description="Number of instructions in the T-pipe, recirculated due to cache miss"/> 91 <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Mali Texture Pipe" name="Cache misses" description="Number of instructions in the T-pipe, recirculated due to cache miss"/>
92
72 <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Mali Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store cache"/> 93 <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Mali Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store cache"/>
73 <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Mali Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store cache"/> 94 <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Mali Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store cache"/>
74 <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Mali Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store cache"/> 95 <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Mali Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store cache"/>
@@ -78,8 +99,11 @@
78 <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Mali Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store cache"/> 99 <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Mali Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store cache"/>
79 <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Mali Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store cache"/> 100 <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Mali Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store cache"/>
80 <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Mali Load/Store Cache" name="Snoops in to LSC" description="Number of coherent memory snoops in to the Load/Store cache"/> 101 <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Mali Load/Store Cache" name="Snoops in to LSC" description="Number of coherent memory snoops in to the Load/Store cache"/>
102
81 </category> 103 </category>
82 <category name="Mali-T6xx L2 and MMU" per_cpu="no"> 104
105 <category name="Mali-T6xx-L2AndMMU" per_cpu="no">
106
83 <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="Mali L2 Cache" name="External write beats" description="Number of external bus write beats"/> 107 <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="Mali L2 Cache" name="External write beats" description="Number of external bus write beats"/>
84 <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="Mali L2 Cache" name="External read beats" description="Number of external bus read beats"/> 108 <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="Mali L2 Cache" name="External read beats" description="Number of external bus read beats"/>
85 <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="Mali L2 Cache" name="Read snoops" description="Number of read transaction snoops"/> 109 <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="Mali L2 Cache" name="Read snoops" description="Number of read transaction snoops"/>
@@ -88,4 +112,5 @@
88 <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="Mali L2 Cache" name="L2 write hits" description="Number of writes hitting in the L2 cache"/> 112 <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="Mali L2 Cache" name="L2 write hits" description="Number of writes hitting in the L2 cache"/>
89 <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="Mali L2 Cache" name="External bus stalls (AR)" description="Number of cycles a valid read address (AR) is stalled by the external interconnect"/> 113 <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="Mali L2 Cache" name="External bus stalls (AR)" description="Number of cycles a valid read address (AR) is stalled by the external interconnect"/>
90 <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="Mali L2 Cache" name="External bus stalls (W)" description="Number of cycles a valid write data (W channel) is stalled by the external interconnect"/> 114 <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="Mali L2 Cache" name="External bus stalls (W)" description="Number of cycles a valid write data (W channel) is stalled by the external interconnect"/>
115
91 </category> 116 </category>
diff --git a/daemon/events.xml b/daemon/events.xml
new file mode 100644
index 0000000..35f454a
--- /dev/null
+++ b/daemon/events.xml
@@ -0,0 +1,1670 @@
1<?xml version="1.0" encoding="UTF-8"?>
2<events>
3 <counter_set name="ARM_ARM11MPCore_cnt" count="3"/>
4 <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cnt" per_cpu="yes">
5 <event counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
6 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
7 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
8 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
9 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
10 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
11 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instructions executed, branch might or might not have changed program flow"/>
12 <event event="0x06" title="Branch" name="Not predicted" description="Branch not predicted"/>
13 <event event="0x07" title="Branch" name="Mispredicted" description="Branch mispredicted"/>
14 <event event="0x08" title="Core" name="Instructions" description="Instructions executed"/>
15 <event event="0x09" title="Core" name="Folded Instructions" description="Folded instructions executed"/>
16 <event event="0x0a" title="Cache" name="Data read access" description="Data cache read access, not including cache operations"/>
17 <event event="0x0b" title="Cache" name="Data read miss" description="Data cache miss, not including Cache Operations"/>
18 <event event="0x0c" title="Cache" name="Data write access" description="Data cache write access"/>
19 <event event="0x0d" title="Cache" name="Data write miss" description="Data cache write miss"/>
20 <event event="0x0e" title="Cache" name="Data line eviction" description="Data cache line eviction, not including cache operations"/>
21 <event event="0x0f" title="Branch" name="PC change w/o mode change" description="Software changed the PC and there is not a mode change"/>
22 <event event="0x10" title="Cache " name="TLB miss" description="Main TLB miss"/>
23 <event event="0x11" title="External" name="External Memory request" description="External memory request (cache refill, noncachable, write-back)"/>
24 <event event="0x12" title="Cache" name="Stall" description="Stall because of Load Store Unit request queue being full"/>
25 <event event="0x13" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of LSU ordering constraints or CP15 operations (Data Synchronization Barrier command) or Strongly Ordered operation"/>
26 <event event="0x14" title="Write Buffer" name="Write Merges" description="Buffered write merged in a store buffer slot"/>
27 <event event="0xFF" title="Core" name="Cycle counter" description="An increment each cycle"/>
28 </category>
29 <counter_set name="ARM_ARM11_cnt" count="3"/>
30 <category name="ARM11" counter_set="ARM_ARM11_cnt" per_cpu="yes">
31 <event counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
32 <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
33 <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
34 <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
35 <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
36 <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
37 <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/>
38 <event event="0x06" title="Branch" name="Mispredicted" description="Branch mis-predicted"/>
39 <event event="0x07" title="Instruction" name="Executed" description="Instructions executed"/>
40 <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/>
41 <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/>
42 <event event="0x0b" title="Cache" name="Data miss" description="Data cache miss, not including Cache Operations"/>
43 <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/>
44 <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/>
45 <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/>
46 <event event="0x10" title="External" name="Access" description="Explicit external data or peripheral access"/>
47 <event event="0x11" title="Cache" name="Data miss" description="Stall because of Load Store Unit request queue being full"/>
48 <event event="0x12" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation"/>
49 <event event="0x13" title="Disable Interrupts" name="FIQ" description="The number of cycles which FIQ interrupts are disabled (ARM1156 only)"/>
50 <event event="0x14" title="Disable Interrupts" name="IRQ" description="The number of cycles which IRQ interrupts are disabled (ARM1156 only)"/>
51 <event event="0x20" title="ETM" name="ETMEXTOUT[0]" description="ETMEXTOUT[0] signal was asserted for a cycle"/>
52 <event event="0x21" title="ETM" name="ETMEXTOUT[1]" description="ETMEXTOUT[1] signal was asserted for a cycle"/>
53 <event event="0x22" title="ETM" name="ETMEXTOUT[0,1]" description="ETMEXTOUT[0] or ETMEXTOUT[1] was asserted"/>
54 <event event="0x23" title="Procedure" name="Calls" description="Procedure call instruction executed"/>
55 <event event="0x24" title="Procedure" name="Returns" description="Procedure return instruction executed"/>
56 <event event="0x25" title="Procedure" name="Return and predicted" description="Procedure return instruction executed and return address predicted"/>
57 <event event="0x26" title="Procedure" name="Return and mispredicted" description="Procedure return instruction executed and return address predicted incorrectly"/>
58 <event event="0x30" title="Cache" name="Inst tag or parity error" description="Instruction cache Tag or Valid RAM parity error (ARM1156 only)"/>
59 <event event="0x31" title="Cache" name="Inst parity error" description="Instruction cache RAM parity error (ARM1156 only)"/>
60 <event event="0x32" title="Cache" name="Data tag or parity error" description="Data cache Tag or Valid RAM parity error (ARM1156 only)"/>
61 <event event="0x33" title="Cache" name="Data parity error" description="Data cache RAM parity error (ARM1156 only)"/>
62 <event event="0x34" title="ITCM" name="Error" description="ITCM error (ARM1156 only)"/>
63 <event event="0x35" title="DTCM" name="Error" description="DTCM error (ARM1156 only)"/>
64 <event event="0x36" title="Procedure" name="Return address pop" description="Procedure return address popped off the return stack (ARM1156 only)"/>
65 <event event="0x37" title="Procedure" name="Return address misprediction" description="Procedure return address popped off the return stack has been incorrectly predicted by the PFU (ARM1156 only)"/>
66 <event event="0x38" title="Cache" name="Data dirty parity error" description="Data cache Dirty RAM parity error (ARM1156 only)"/>
67 </category>
68 <counter_set name="cci-400_cnt" count="4"/>
69 <category name="CCI-400" counter_set="cci-400_cnt" per_cpu="no" supports_event_based_sampling="yes">
70 <event counter="cci-400_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
71
72 <option_set name="Slave">
73 <option event_delta="0x00" name="S0" description="Slave interface 0"/>
74 <option event_delta="0x20" name="S1" description="Slave interface 1"/>
75 <option event_delta="0x40" name="S2" description="Slave interface 2"/>
76 <option event_delta="0x60" name="S3" description="Slave interface 3"/>
77 <option event_delta="0x80" name="S4" description="Slave interface 4"/>
78 </option_set>
79
80 <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/>
81 <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/>
82 <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/>
83 <event event="0x03" option_set="Slave" title="CCI-400" name="Read: shareable" description="Read request handshake: inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation"/>
84 <event event="0x04" option_set="Slave" title="CCI-400" name="Read: cache" description="Read request handshake: cache maintenance operation, CleanInvalid, CleanShared, MakeInvalid"/>
85 <event event="0x05" option_set="Slave" title="CCI-400" name="Read: memory barrier" description="Read request handshake: memory barrier"/>
86 <event event="0x06" option_set="Slave" title="CCI-400" name="Read: sync barrier" description="Read request handshake: synchronization barrier"/>
87 <event event="0x07" option_set="Slave" title="CCI-400" name="Read: DVM message, no sync" description="Read request handshake: DVM message, not synchronization"/>
88 <event event="0x08" option_set="Slave" title="CCI-400" name="Read: DVM message, sync" description="Read request handshake: DVM message, synchronization"/>
89 <event event="0x09" option_set="Slave" title="CCI-400" name="Read: stall" description="Read request stall cycle because the transaction tracker is full. Increase SIx_R_MAX to avoid this stall"/>
90 <event event="0x0a" option_set="Slave" title="CCI-400" name="Read data last handshake" description="Read data last handshake: data returned from the snoop instead of from downstream"/>
91 <event event="0x0b" option_set="Slave" title="CCI-400" name="Read data stall cycle" description="Read data stall cycle: RVALIDS is HIGH, RREADYS is LOW"/>
92 <event event="0x0c" option_set="Slave" title="CCI-400" name="Write: any" description="Write request handshake: any"/>
93 <event event="0x0d" option_set="Slave" title="CCI-400" name="Write: transaction" description="Write request handshake: device transaction"/>
94 <event event="0x0e" option_set="Slave" title="CCI-400" name="Write: normal" description="Write request handshake: normal, non-shareable, or system-shareable, but not barrier"/>
95 <event event="0x0f" option_set="Slave" title="CCI-400" name="Write: shareable" description="Write request handshake: inner- or outer-shareable, WriteBack or WriteClean"/>
96 <event event="0x10" option_set="Slave" title="CCI-400" name="Write: WriteUnique" description="Write request handshake: WriteUnique"/>
97 <event event="0x11" option_set="Slave" title="CCI-400" name="Write: WriteLineUnique" description="Write request handshake: WriteLineUnique"/>
98 <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/>
99 <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/>
100
101 <option_set name="Master">
102 <option event_delta="0xa0" name="M0" description="Master interface 0"/>
103 <option event_delta="0xc0" name="M1" description="Master interface 1"/>
104 <option event_delta="0xe0" name="M2" description="Master interface 2"/>
105 </option_set>
106
107 <event event="0x14" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/>
108 <event event="0x15" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Read request stall cycle because of an address hazard"/>
109 <event event="0x16" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of an ID hazard"/>
110 <event event="0x17" option_set="Master" title="CCI-400" name="Read stall: tracker full" description="Read request stall cycle because the transaction tracker is full. Increase MIx_R_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/>
111 <event event="0x18" option_set="Master" title="CCI-400" name="Read stall: barrier hazard" description="Read request stall cycle because of a barrier hazard"/>
112 <event event="0x19" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/>
113 <event event="0x1a" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase MIx_W_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/>
114 </category>
115
116 <counter_set name="cci-400-r1_cnt" count="4"/>
117 <category name="CCI-400" counter_set="cci-400-r1_cnt" per_cpu="no" supports_event_based_sampling="yes">
118 <event counter="cci-400-r1_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
119
120 <option_set name="Slave">
121 <option event_delta="0x00" name="S0" description="Slave interface 0"/>
122 <option event_delta="0x20" name="S1" description="Slave interface 1"/>
123 <option event_delta="0x40" name="S2" description="Slave interface 2"/>
124 <option event_delta="0x60" name="S3" description="Slave interface 3"/>
125 <option event_delta="0x80" name="S4" description="Slave interface 4"/>
126 </option_set>
127
128 <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/>
129 <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/>
130 <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/>
131 <event event="0x03" option_set="Slave" title="CCI-400" name="Read: shareable" description="Read request handshake: inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation"/>
132 <event event="0x04" option_set="Slave" title="CCI-400" name="Read: cache" description="Read request handshake: cache maintenance operation"/>
133 <event event="0x05" option_set="Slave" title="CCI-400" name="Read: memory barrier" description="Read request handshake: memory barrier"/>
134 <event event="0x06" option_set="Slave" title="CCI-400" name="Read: sync barrier" description="Read request handshake: synchronization barrier"/>
135 <event event="0x07" option_set="Slave" title="CCI-400" name="Read: DVM message, no sync" description="Read request handshake: DVM message, not synchronization"/>
136 <event event="0x08" option_set="Slave" title="CCI-400" name="Read: DVM message, sync" description="Read request handshake: DVM message, synchronization"/>
137 <event event="0x09" option_set="Slave" title="CCI-400" name="Read: stall" description="Read request stall cycle because the transaction tracker is full. Increase SIx_R_MAX to avoid this stall"/>
138 <event event="0x0a" option_set="Slave" title="CCI-400" name="Read data last handshake" description="Read data last handshake: data returned from the snoop instead of from downstream"/>
139 <event event="0x0b" option_set="Slave" title="CCI-400" name="Read data stall cycle" description="Read data stall cycle: RVALIDS is HIGH, RREADYS is LOW"/>
140 <event event="0x0c" option_set="Slave" title="CCI-400" name="Write: any" description="Write request handshake: any"/>
141 <event event="0x0d" option_set="Slave" title="CCI-400" name="Write: transaction" description="Write request handshake: device transaction"/>
142 <event event="0x0e" option_set="Slave" title="CCI-400" name="Write: normal" description="Write request handshake: normal, non-shareable, or system-shareable, but not barrier"/>
143 <event event="0x0f" option_set="Slave" title="CCI-400" name="Write: shareable" description="Write request handshake: inner- or outer-shareable, WriteBack or WriteClean"/>
144 <event event="0x10" option_set="Slave" title="CCI-400" name="Write: WriteUnique" description="Write request handshake: WriteUnique"/>
145 <event event="0x11" option_set="Slave" title="CCI-400" name="Write: WriteLineUnique" description="Write request handshake: WriteLineUnique"/>
146 <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/>
147 <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/>
148 <event event="0x14" option_set="Slave" title="CCI-400" name="Read stall: slave hazard" description="Read request stall cycle because of a slave interface ID hazard"/>
149
150 <option_set name="Master">
151 <option event_delta="0xa0" name="M0" description="Master interface 0"/>
152 <option event_delta="0xc0" name="M1" description="Master interface 1"/>
153 <option event_delta="0xe0" name="M2" description="Master interface 2"/>
154 </option_set>
155
156 <event event="0x00" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/>
157 <event event="0x01" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Stall cycle because of an address hazard. A read or write invalidation is stalled because of an outstanding transaction to an overlapping address"/>
158 <event event="0x02" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of a master interface ID hazard"/>
159 <event event="0x03" option_set="Master" title="CCI-400" name="Read stall: tracker full" description="A read request with a QoS value in the high priority group is stalled for a cycle because the read transaction queue is full. Increase MIx_R_MAX to avoid this stall"/>
160 <event event="0x04" option_set="Master" title="CCI-400" name="Read stall: barrier hazard" description="Read request stall cycle because of a barrier hazard"/>
161 <event event="0x05" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/>
162 <event event="0x06" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="A write request is stalled for a cycle because the write transaction tracker is full. Increase MIx_W_MAX to avoid this stall"/>
163 <event event="0x07" option_set="Master" title="CCI-400" name="Read Stall: Low Priority" description="A read request with a QoS value in the low priority group is stalled for a cycle because there are no slots available in the read queue for the low priority group"/>
164 <event event="0x08" option_set="Master" title="CCI-400" name="Read Stall: Medium Priority" description="A read request with a QoS value in the medium priority group is stalled for a cycle because there are no slots available in the read queue for the medium priority group"/>
165 <event event="0x09" option_set="Master" title="CCI-400" name="Read Stall: VN0" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN0"/>
166 <event event="0x0a" option_set="Master" title="CCI-400" name="Read Stall: VN1" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN1"/>
167 <event event="0x0b" option_set="Master" title="CCI-400" name="Read Stall: VN2" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN2"/>
168 <event event="0x0c" option_set="Master" title="CCI-400" name="Read Stall: VN3" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN3"/>
169 <event event="0x0d" option_set="Master" title="CCI-400" name="Write Stall: VN0" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN0"/>
170 <event event="0x0e" option_set="Master" title="CCI-400" name="Write Stall: VN1" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN1"/>
171 <event event="0x0f" option_set="Master" title="CCI-400" name="Write Stall: VN2" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN2"/>
172 <event event="0x10" option_set="Master" title="CCI-400" name="Write Stall: VN" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN"/>
173 <event event="0x11" option_set="Master" title="CCI-400" name="WriteUnique or WriteLineUnique Stall" description="A WriteUnique or WriteLineUnique request is stalled for a cycle because of an address hazard"/>
174 </category>
175 <counter_set name="CCN-504_cnt" count="4"/>
176 <category name="CCN-504" counter_set="CCN-504_cnt">
177 <event counter="CCN-504_ccnt" title="CCN-504 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
178
179 <option_set name="XP_Region">
180 <option event_delta="0x400000" name="XP 0" description="Crosspoint 0"/>
181 <option event_delta="0x410000" name="XP 1" description="Crosspoint 1"/>
182 <option event_delta="0x420000" name="XP 2" description="Crosspoint 2"/>
183 <option event_delta="0x430000" name="XP 3" description="Crosspoint 3"/>
184 <option event_delta="0x440000" name="XP 4" description="Crosspoint 4"/>
185 <option event_delta="0x450000" name="XP 5" description="Crosspoint 5"/>
186 <option event_delta="0x460000" name="XP 6" description="Crosspoint 6"/>
187 <option event_delta="0x470000" name="XP 7" description="Crosspoint 7"/>
188 <option event_delta="0x480000" name="XP 8" description="Crosspoint 8"/>
189 <option event_delta="0x490000" name="XP 9" description="Crosspoint 9"/>
190 <option event_delta="0x4A0000" name="XP 10" description="Crosspoint 10"/>
191 </option_set>
192
193 <event event="0x0801" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: H-bit" description="Bus 0: REQ: Set H-bit, signaled when this XP sets the H-bit."/>
194 <event event="0x0802" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: S-bit" description="Bus 0: REQ: Set S-bit, signaled when this XP sets the S-bit."/>
195 <event event="0x0803" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: P-Cnt" description="Bus 0: REQ: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
196 <event event="0x0804" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: TknV" description="Bus 0: REQ: No TknV, signaled when this XP transmits a valid packet."/>
197 <event event="0x0809" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: H-bit" description="Bus 1: REQ: Set H-bit, signaled when this XP sets the H-bit."/>
198 <event event="0x080A" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: S-bit" description="Bus 1: REQ: Set S-bit, signaled when this XP sets the S-bit."/>
199 <event event="0x080B" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: P-Cnt" description="Bus 1: REQ: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
200 <event event="0x080C" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: TknV" description="Bus 1: REQ: No TknV, signaled when this XP transmits a valid packet."/>
201 <event event="0x0811" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: H-bit" description="Bus 0: RSP: Set H-bit, signaled when this XP sets the H-bit."/>
202 <event event="0x0812" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: S-bit" description="Bus 0: RSP: Set S-bit, signaled when this XP sets the S-bit."/>
203 <event event="0x0813" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: P-Cnt" description="Bus 0: RSP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
204 <event event="0x0814" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: TknV" description="Bus 0: RSP: No TknV, signaled when this XP transmits a valid packet."/>
205 <event event="0x0819" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: H-bit" description="Bus 1: RSP: Set H-bit, signaled when this XP sets the H-bit."/>
206 <event event="0x081A" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: S-bit" description="Bus 1: RSP: Set S-bit, signaled when this XP sets the S-bit."/>
207 <event event="0x081B" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: P-Cnt" description="Bus 1: RSP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
208 <event event="0x081C" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: TknV" description="Bus 1: RSP: No TknV, signaled when this XP transmits a valid packet."/>
209 <event event="0x0821" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: H-bit" description="Bus 0: SNP: Set H-bit, signaled when this XP sets the H-bit."/>
210 <event event="0x0822" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: S-bit" description="Bus 0: SNP: Set S-bit, signaled when this XP sets the S-bit."/>
211 <event event="0x0823" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: P-Cnt" description="Bus 0: SNP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
212 <event event="0x0824" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: TknV" description="Bus 0: SNP: No TknV, signaled when this XP transmits a valid packet."/>
213 <event event="0x0829" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: H-bit" description="Bus 1: SNP: Set H-bit, signaled when this XP sets the H-bit."/>
214 <event event="0x082A" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: S-bit" description="Bus 1: SNP: Set S-bit, signaled when this XP sets the S-bit."/>
215 <event event="0x082B" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: P-Cnt" description="Bus 1: SNP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
216 <event event="0x082C" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: TknV" description="Bus 1: SNP: No TknV, signaled when this XP transmits a valid packet."/>
217 <event event="0x0831" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: H-bit" description="Bus 0: DAT: Set H-bit, signaled when this XP sets the H-bit."/>
218 <event event="0x0832" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: S-bit" description="Bus 0: DAT: Set S-bit, signaled when this XP sets the S-bit."/>
219 <event event="0x0833" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: P-Cnt" description="Bus 0: DAT: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
220 <event event="0x0834" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: TknV" description="Bus 0: DAT: No TknV, signaled when this XP transmits a valid packet."/>
221 <event event="0x0839" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: H-bit" description="Bus 1: DAT: Set H-bit, signaled when this XP sets the H-bit."/>
222 <event event="0x083A" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: S-bit" description="Bus 1: DAT: Set S-bit, signaled when this XP sets the S-bit."/>
223 <event event="0x083B" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: P-Cnt" description="Bus 1: DAT: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
224 <event event="0x083C" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: TknV" description="Bus 1: DAT: No TknV, signaled when this XP transmits a valid packet."/>
225 <event event="0x0871" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: H-bit" description="Bus 0: DATB: Set H-bit, signaled when this XP sets the H-bit."/>
226 <event event="0x0872" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: S-bit" description="Bus 0: DATB: Set S-bit, signaled when this XP sets the S-bit."/>
227 <event event="0x0873" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: P-Cnt" description="Bus 0: DATB: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
228 <event event="0x0874" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: TknV" description="Bus 0: DATB: No TknV, signaled when this XP transmits a valid packet."/>
229 <event event="0x0879" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: H-bit" description="Bus 1: DATB: Set H-bit, signaled when this XP sets the H-bit."/>
230 <event event="0x087A" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: S-bit" description="Bus 1: DATB: Set S-bit, signaled when this XP sets the S-bit."/>
231 <event event="0x087B" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: P-Cnt" description="Bus 1: DATB: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
232 <event event="0x087C" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: TknV" description="Bus 1: DATB: No TknV, signaled when this XP transmits a valid packet."/>
233
234 <option_set name="HN-F_Region">
235 <option event_delta="0x200000" name="HN-F 3" description="Fully-coherent Home Node 3"/>
236 <option event_delta="0x210000" name="HN-F 5" description="Fully-coherent Home Node 5"/>
237 <option event_delta="0x220000" name="HN-F 7" description="Fully-coherent Home Node 7"/>
238 <option event_delta="0x230000" name="HN-F 8" description="Fully-coherent Home Node 8"/>
239 <option event_delta="0x240000" name="HN-F 13" description="Fully-coherent Home Node 13"/>
240 <option event_delta="0x250000" name="HN-F 15" description="Fully-coherent Home Node 15"/>
241 <option event_delta="0x260000" name="HN-F 17" description="Fully-coherent Home Node 17"/>
242 <option event_delta="0x270000" name="HN-F 18" description="Fully-coherent Home Node 18"/>
243 </option_set>
244
245 <event event="0x0401" option_set="HN-F_Region" title="CCN-504" name="Cache Miss" description="Counts the total cache misses. This is the first time lookup result, and is high priority."/>
246 <event event="0x0402" option_set="HN-F_Region" title="CCN-504" name="L3 SF Cache Access" description="Counts the number of cache accesses. This is the first time access, and is high priority."/>
247 <event event="0x0403" option_set="HN-F_Region" title="CCN-504" name="Cache Fill" description="Counts the total allocations in the HN L3 cache, and all cache line allocations to the L3 cache."/>
248 <event event="0x0404" option_set="HN-F_Region" title="CCN-504" name="POCQ Retry" description="Counts the number of requests that have been retried."/>
249 <event event="0x0405" option_set="HN-F_Region" title="CCN-504" name="POCQ Reqs Recvd" description="Counts the number of requests received by HN."/>
250 <event event="0x0406" option_set="HN-F_Region" title="CCN-504" name="SF Hit" description="Counts the number of snoop filter hits."/>
251 <event event="0x0407" option_set="HN-F_Region" title="CCN-504" name="SF Evictions" description="Counts the number of snoop filter evictions. Cache invalidations are initiated."/>
252 <event event="0x0408" option_set="HN-F_Region" title="CCN-504" name="Snoops Sent" description="Counts the number of snoops sent. Does not differentiate between broadcast or directed snoops."/>
253 <event event="0x0409" option_set="HN-F_Region" title="CCN-504" name="Snoops Broadcast" description="Counts the number of snoop broadcasts sent."/>
254 <event event="0x040A" option_set="HN-F_Region" title="CCN-504" name="L3 Eviction" description="Counts the number of L3 evictions."/>
255 <event event="0x040B" option_set="HN-F_Region" title="CCN-504" name="L3 Fill Invalid Way" description="Counts the number of L3 fills to an invalid way."/>
256 <event event="0x040C" option_set="HN-F_Region" title="CCN-504" name="MC Retries" description="Counts the number of transactions retried by the memory controller."/>
257 <event event="0x040D" option_set="HN-F_Region" title="CCN-504" name="MC Reqs" description="Counts the number of requests to the memory controller."/>
258 <event event="0x040E" option_set="HN-F_Region" title="CCN-504" name="QOS HH Retry" description="Counts the number of times a highest-priority QoS class was retried at the HN-F."/>
259
260 <option_set name="RN-I_Region">
261 <option event_delta="0x800000" name="RN-I 0" description="I/O-coherent Requesting Node 0"/>
262 <option event_delta="0x820000" name="RN-I 2" description="I/O-coherent Requesting Node 2"/>
263 <option event_delta="0x860000" name="RN-I 6" description="I/O-coherent Requesting Node 6"/>
264 <option event_delta="0x8C0000" name="RN-I 12" description="I/O-coherent Requesting Node 12"/>
265 <option event_delta="0x900000" name="RN-I 16" description="I/O-coherent Requesting Node 16"/>
266 <option event_delta="0x940000" name="RN-I 20" description="I/O-coherent Requesting Node 20"/>
267 </option_set>
268
269 <event event="0x1601" option_set="RN-I_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/>
270 <event event="0x1602" option_set="RN-I_Region" title="CCN-504" name="S1 RDataBeats" description="S1 RDataBeats."/>
271 <event event="0x1603" option_set="RN-I_Region" title="CCN-504" name="S2 RDataBeats" description="S2 RDataBeats."/>
272 <event event="0x1604" option_set="RN-I_Region" title="CCN-504" name="RXDAT Flits received" description="RXDAT Flits received."/>
273 <event event="0x1605" option_set="RN-I_Region" title="CCN-504" name="TXDAT Flits sent" description="TXDAT Flits sent."/>
274 <event event="0x1606" option_set="RN-I_Region" title="CCN-504" name="Total TXREQ Flits sent" description="Total TXREQ Flits sent."/>
275 <event event="0x1607" option_set="RN-I_Region" title="CCN-504" name="Retried TXREQ Flits sent" description="Retried TXREQ Flits sent."/>
276 <event event="0x1608" option_set="RN-I_Region" title="CCN-504" name="RRT full" description="RRT full."/>
277 <event event="0x1609" option_set="RN-I_Region" title="CCN-504" name="WRT full" description="WRT full."/>
278 <event event="0x160A" option_set="RN-I_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/>
279
280 <option_set name="SBAS_Region">
281 <option event_delta="0x810000" name="SBAS 1" description="ACE master to CHI protocol bridge 1"/>
282 <option event_delta="0x890000" name="SBAS 9" description="ACE master to CHI protocol bridge 9"/>
283 <option event_delta="0x8B0000" name="SBAS 11" description="ACE master to CHI protocol bridge 11"/>
284 <option event_delta="0x930000" name="SBAS 19" description="ACE master to CHI protocol bridge 19"/>
285 </option_set>
286
287 <event event="0x1001" option_set="SBAS_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/>
288 <event event="0x1004" option_set="SBAS_Region" title="CCN-504" name="RXDAT Flits received" description="RXDAT Flits received."/>
289 <event event="0x1005" option_set="SBAS_Region" title="CCN-504" name="TXDAT Flits sent" description="TXDAT Flits sent."/>
290 <event event="0x1006" option_set="SBAS_Region" title="CCN-504" name="Total TXREQ Flits sent" description="Total TXREQ Flits sent."/>
291 <event event="0x1007" option_set="SBAS_Region" title="CCN-504" name="Retried TXREQ Flits sent" description="Retried TXREQ Flits sent."/>
292 <event event="0x1008" option_set="SBAS_Region" title="CCN-504" name="RRT full" description="RRT full."/>
293 <event event="0x1009" option_set="SBAS_Region" title="CCN-504" name="WRT full" description="WRT full."/>
294 <event event="0x100A" option_set="SBAS_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/>
295
296 </category>
297 <counter_set name="ARMv7_Cortex_A12_cnt" count="6"/>
298 <category name="Cortex-A12" counter_set="ARMv7_Cortex_A12_cnt" per_cpu="yes" supports_event_based_sampling="yes">
299 <event counter="ARMv7_Cortex_A12_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
300 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
301 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
302 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
303 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
304 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
305 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
306 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
307 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
308 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
309 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
310 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
311 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
312 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
313 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
314 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
315 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
316 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
317 <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
318 <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
319 <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
320 <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
321 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
322 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
323 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
324 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
325 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
326 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
327 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
328 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
329 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
330 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
331 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
332 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
333 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
334 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
335 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
336 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
337 <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
338 <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
339 <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
340 <event event="0x6f" title="Intrinsic" name="STREX" description="Exclusive instruction speculatively executed - STREX"/>
341 <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/>
342 <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/>
343 <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
344 <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
345 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
346 <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
347 <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
348 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
349 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
350 <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
351 <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
352 <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
353 <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
354 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
355 <event event="0x8a" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
356 <event event="0xc0" title="Instruction" name="Stalled Linefill" description="Instruction side stalled due to a Linefill"/>
357 <event event="0xc1" title="Instruction" name="Stalled Page Table Walk" description="Instruction Side stalled due to a Page Table Walk"/>
358 <event event="0xc2" title="Cache" name="4 Ways Read" description="Number of set of 4 ways read in the instruction cache - Tag RAM"/>
359 <event event="0xc3" title="Cache" name="Ways Read" description="Number of ways read in the instruction cache - Data RAM"/>
360 <event event="0xc4" title="Cache" name="BATC Read" description="Number of ways read in the instruction BTAC RAM"/>
361 <event event="0xca" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local Cortex-A12 cluster, rather than accessing the L2 cache or issuing an external read. It increments on each transaction, rather than on each beat of data"/>
362 <event event="0xd3" title="Slots" name="Load-Store Unit" description="Duration during which all slots in the Load-Store Unit are busy"/>
363 <event event="0xd8" title="Slots" name="Load-Store Issue Queue" description="Duration during which all slots in the Load-Store Issue queue are busy"/>
364 <event event="0xd9" title="Slots" name="Data Processing Issue Queue" description="Duration during which all slots in the Data Processing issue queue are busy"/>
365 <event event="0xda" title="Slots" name="Data Engine Issue Queue" description="Duration during which all slots in the Data Engine issue queue are busy"/>
366 <event event="0xdb" title="NEON" name="Flush" description="Number of NEON instruction which fail their condition code and lead to a flush of the DE pipe"/>
367 <event event="0xdc" title="Hypervisor" name="Traps" description="Number of Trap to hypervisor"/>
368 <event event="0xde" title="PTM" name="EXTOUT 0" description="PTM EXTOUT 0"/>
369 <event event="0xdf" title="PTM" name="EXTOUT 1" description="PTM EXTOUT 1"/>
370 <event event="0xe0" title="MMU" name="Table Walk" description="Duration during which the MMU handle a Page table walk"/>
371 <event event="0xe1" title="MMU" name="Stage1 Table Walk" description="Duration during which the MMU handle a Stage1 Page table walk"/>
372 <event event="0xe2" title="MMU" name="Stage2 Table Walk" description="Duration during which the MMU handle a Stage2 Page table walk"/>
373 <event event="0xe3" title="MMU" name="LSU Table Walk" description="Duration during which the MMU handle a Page table walk requested by the Load Store Unit"/>
374 <event event="0xe4" title="MMU" name="Instruction Table Walk" description="Duration during which the MMU handle a Page table walk requested by the Instruction side"/>
375 <event event="0xe5" title="MMU" name="Preload Table Walk" description="Duration during which the MMU handle a Page table walk requested by a Preload instruction or Prefetch request"/>
376 <event event="0xe6" title="MMU" name="cp15 Table Walk" description="Duration during which the MMU handle a Page table walk requested by a cp15 operation (maintenance by MVA and VA-to-PA operation)"/>
377 <event event="0xe7" title="Cache" name="L1 PLD TLB refill" description="Level 1 PLD TLB refill"/>
378 <event event="0xe8" title="Cache" name="L1 CP15 TLB refill" description="Level 1 CP15 TLB refill"/>
379 <event event="0xe9" title="Cache" name="L1 TLB flush" description="Level 1 TLB flush"/>
380 <event event="0xea" title="Cache" name="L2 TLB access" description="Level 2 TLB access"/>
381 <event event="0xeb" title="Cache" name="L2 TLB miss" description="Level 2 TLB miss"/>
382 </category>
383 <counter_set name="ARMv7_Cortex_A15_cnt" count="6"/>
384 <category name="Cortex-A15" counter_set="ARMv7_Cortex_A15_cnt" per_cpu="yes" supports_event_based_sampling="yes">
385 <event counter="ARMv7_Cortex_A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
386 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
387 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
388 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
389 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
390 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
391 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
392 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
393 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
394 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
395 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
396 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
397 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
398 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
399 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
400 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
401 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
402 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
403 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
404 <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
405 <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
406 <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
407 <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
408 <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
409 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
410 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
411 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
412 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
413 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>
414 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>
415 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
416 <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
417 <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
418 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
419 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
420 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
421 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
422 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
423 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
424 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
425 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
426 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
427 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
428 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
429 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
430 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
431 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
432 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
433 <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
434 <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
435 <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
436 <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
437 <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/>
438 <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/>
439 <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
440 <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
441 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
442 <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
443 <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
444 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
445 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
446 <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
447 <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
448 <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
449 <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
450 </category>
451 <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
452 <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
453 <!-- 0x11 CPU_CYCLES - Cycle -->
454 <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
455 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
456 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
457 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
458 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
459 <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
460 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
461 <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
462 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
463 <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
464 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
465 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
466 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
467 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
468 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
469 <!-- 0x09 EXC_TAKEN - Exception taken -->
470 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
471 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
472 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
473 <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
474 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
475 <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
476 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
477 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
478 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
479 <!-- 0x13 MEM_ACCESS - Data memory access -->
480 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
481 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
482 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
483 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
484 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
485 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
486 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
487 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
488 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
489 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
490 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
491 <!-- 0x19 BUS_ACCESS - Bus access -->
492 <event event="0x19" title="Bus" name="Access" description="Bus access"/>
493 <!-- 0x1A MEMORY_ERROR - Local memory error -->
494 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
495 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
496 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
497 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
498 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
499 <!-- 0x1D BUS_CYCLES - Bus cycle -->
500 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
501 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
502 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
503 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
504 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
505 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
506 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
507 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
508 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
509 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
510 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
511 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
512 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
513 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
514 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
515 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
516 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
517 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
518 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
519 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
520 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
521 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
522 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
523 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
524 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
525 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
526 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
527 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
528 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
529 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
530 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
531 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
532 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
533 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
534 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
535 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
536 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
537 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
538 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
539 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
540 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
541 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
542 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
543 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
544 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
545 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
546 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
547 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
548 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
549 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
550 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
551 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
552 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
553 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
554 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
555 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
556 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
557 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
558 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
559 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
560 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
561 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
562 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
563 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
564 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
565 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
566 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
567 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
568 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
569 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
570 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
571 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
572 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
573 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
574 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
575 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
576 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
577 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
578 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
579 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
580 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
581 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
582 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
583 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
584 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
585 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
586 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
587 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
588 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
589 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
590 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
591 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
592 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
593 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
594 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
595 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
596 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
597 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
598 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
599 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
600 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
601 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
602 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
603 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
604 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
605 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
606 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
607 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
608 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
609 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
610 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
611 <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
612 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
613 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
614 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
615 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
616 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
617 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
618 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
619 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
620 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
621 </category>
622 <counter_set name="ARM_Cortex-A57_cnt" count="6"/>
623 <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes">
624 <!-- 0x11 CPU_CYCLES - Cycle -->
625 <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
626 <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
627 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
628 <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
629 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
630 <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
631 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
632 <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
633 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
634 <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
635 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
636 <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
637 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
638 <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
639 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
640 <!-- 0x09 EXC_TAKEN - Exception taken -->
641 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
642 <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
643 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
644 <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
645 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
646 <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
647 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
648 <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
649 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
650 <!-- 0x13 MEM_ACCESS - Data memory access -->
651 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
652 <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
653 <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
654 <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
655 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
656 <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
657 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
658 <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
659 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
660 <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
661 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
662 <!-- 0x19 BUS_ACCESS - Bus access -->
663 <event event="0x19" title="Bus" name="Access" description="Bus access"/>
664 <!-- 0x1A MEMORY_ERROR - Local memory error -->
665 <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
666 <!-- 0x1B INST_SPEC - Operation speculatively executed -->
667 <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
668 <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
669 <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
670 <!-- 0x1D BUS_CYCLES - Bus cycle -->
671 <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
672 <!-- 0x1E CHAIN - Odd performance counter chain mode -->
673 <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
674 <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
675 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
676 <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
677 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
678 <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
679 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
680 <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
681 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
682 <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
683 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
684 <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
685 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
686 <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
687 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
688 <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
689 <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
690 <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
691 <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
692 <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
693 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
694 <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
695 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
696 <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
697 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
698 <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
699 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
700 <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
701 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
702 <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
703 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
704 <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
705 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
706 <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
707 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
708 <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
709 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
710 <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
711 <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
712 <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
713 <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
714 <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
715 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
716 <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
717 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
718 <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
719 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
720 <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
721 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
722 <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
723 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
724 <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
725 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
726 <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
727 <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
728 <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
729 <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
730 <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
731 <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
732 <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
733 <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
734 <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
735 <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
736 <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
737 <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
738 <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
739 <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
740 <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
741 <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
742 <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
743 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
744 <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
745 <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
746 <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
747 <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
748 <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
749 <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
750 <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
751 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
752 <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
753 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
754 <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
755 <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
756 <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
757 <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
758 <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
759 <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
760 <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
761 <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
762 <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
763 <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
764 <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
765 <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
766 <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
767 <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
768 <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
769 <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
770 <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
771 <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
772 <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
773 <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
774 <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
775 <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
776 <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
777 <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
778 <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
779 <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
780 <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
781 <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
782 <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
783 <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
784 <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
785 <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
786 <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
787 <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
788 <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
789 <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
790 <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
791 <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
792 </category>
793 <counter_set name="ARMv7_Cortex_A5_cnt" count="2"/>
794 <category name="Cortex-A5" counter_set="ARMv7_Cortex_A5_cnt" per_cpu="yes" supports_event_based_sampling="yes">
795 <event counter="ARMv7_Cortex_A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
796 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
797 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
798 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
799 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
800 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
801 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
802 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
803 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
804 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
805 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
806 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
807 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
808 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
809 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
810 <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
811 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
812 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
813 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
814 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
815 <event event="0x14" title="Cache" name="Instruction access" description="Instruction cache access"/>
816 <event event="0x15" title="Cache" name="Data eviction" description="Data cache eviction"/>
817 <event event="0x86" title="Interrupts" name="IRQ" description="IRQ exception taken"/>
818 <event event="0x87" title="Interrupts" name="FIQ" description="FIQ exception taken"/>
819 <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
820 <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
821 <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
822 <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
823 <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
824 <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
825 <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description="ETM - ETM Ext Out[0]"/>
826 <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description="ETM - ETM Ext Out[1]"/>
827 <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
828 </category>
829 <counter_set name="ARMv7_Cortex_A7_cnt" count="4"/>
830 <category name="Cortex-A7" counter_set="ARMv7_Cortex_A7_cnt" per_cpu="yes" supports_event_based_sampling="yes">
831 <event counter="ARMv7_Cortex_A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
832 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
833 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
834 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
835 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
836 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
837 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
838 <event event="0x06" title="Memory" name="Data Read" description="Data read architecturally executed"/>
839 <event event="0x07" title="Memory" name="Data Write" description="Data write architecturally executed"/>
840 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
841 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
842 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
843 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
844 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
845 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
846 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
847 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
848 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
849 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
850 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
851 <event event="0x15" title="Cache" name="L1 data eviction" description="Level 1 data cache eviction"/>
852 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
853 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
854 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
855 <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
856 <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
857 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
858 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
859 <event event="0x86" title="Exception" name="IRQ" description="IRQ exception taken"/>
860 <event event="0x87" title="Exception" name="FIQ" description="FIQ exception taken"/>
861 <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
862 <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
863 <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
864 <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
865 <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
866 <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
867 <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description="ETM - ETM Ext Out[0]"/>
868 <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description="ETM - ETM Ext Out[1]"/>
869 <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
870 <event event="0xCA" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local cluster, rather than accessing the L2 cache or issuing an external read."/>
871 </category>
872 <counter_set name="ARMv7_Cortex_A8_cnt" count="4"/>
873 <category name="Cortex-A8" counter_set="ARMv7_Cortex_A8_cnt" per_cpu="yes" supports_event_based_sampling="yes">
874 <event counter="ARMv7_Cortex_A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
875 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
876 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
877 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
878 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
879 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
880 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
881 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
882 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
883 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
884 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
885 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
886 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
887 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
888 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
889 <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
890 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
891 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
892 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
893 <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>
894 <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>
895 <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>
896 <event event="0x43" title="Cache" name="L2 access" description="Any accesses to the L2 cache"/>
897 <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>
898 <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>
899 <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>
900 <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/>
901 <event event="0x48" title="Memory" name="Unaligned access replay" description="Any unaligned memory access that results in a replay"/>
902 <event event="0x49" title="Cache" name="L1 data hash miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/>
903 <event event="0x4a" title="Cache" name="L1 inst hash miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/>
904 <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/>
905 <event event="0x4c" title="NEON" name="L1 cache hit" description="Any NEON access that hits in the L1 data cache"/>
906 <event event="0x4d" title="NEON" name="L1 cache access" description="Any NEON cacheable data accesses for L1 data cache"/>
907 <event event="0x4e" title="NEON" name="L2 cache access" description="Any L2 cache accesses as a result of a NEON memory access"/>
908 <event event="0x4f" title="NEON" name="L2 cache hit" description="Any NEON hit in the L2 cache"/>
909 <event event="0x50" title="Cache" name="L1 inst access" description="Any L1 instruction cache access, excluding CP15 cache accesses"/>
910 <event event="0x51" title="Branch" name="Return stack misprediction" description="Any return stack misprediction because of incorrect target address for a taken return stack pop"/>
911 <event event="0x52" title="Branch" name="Direction misprediction" description="Branch direction misprediction"/>
912 <event event="0x53" title="Branch" name="Taken prediction" description="Any predictable branch that is predicted to be taken"/>
913 <event event="0x54" title="Branch" name="Executed and taken prediction" description="Any predictable branch that is executed and taken"/>
914 <event event="0x55" title="Core" name="Operations issued" description="Number of operations issued, where an operation is either: an instruction or one operation in a sequence of operations that make up a multi-cycle instruction"/>
915 <event event="0x56" title="Core" name="No issue cycles" description="Increment for every cycle that no instructions are available for issue"/>
916 <event event="0x57" title="Core" name="Issue cycles" description="For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once"/>
917 <event event="0x58" title="NEON" name="MRC data wait" description="Number of cycles the processor stalls waiting on MRC data from NEON"/>
918 <event event="0x59" title="NEON" name="Full queue" description="Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue"/>
919 <event event="0x5a" title="NEON" name="Idle" description="Number of cycles that NEON and integer processors are both not idle"/>
920 <event event="0x70" title="External" name="PMUEXTIN[0]" description="Counts any event from external input source PMUEXTIN[0]"/>
921 <event event="0x71" title="External" name="PMUEXTIN[1]" description="Counts any event from external input source PMUEXTIN[1]"/>
922 <event event="0x72" title="External" name="PMUEXTIN[0,1]" description="Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"/>
923 </category>
924 <counter_set name="ARMv7_Cortex_A9_cnt" count="6"/>
925 <category name="Cortex-A9" counter_set="ARMv7_Cortex_A9_cnt" per_cpu="yes" supports_event_based_sampling="yes">
926 <event counter="ARMv7_Cortex_A9_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
927 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
928 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
929 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
930 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
931 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
932 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
933 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
934 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
935 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
936 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
937 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
938 <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
939 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
940 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
941 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
942 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
943 <event event="0x40" title="Java" name="Bytecode execute" description="Counts the number of Java bytecodes being decoded, including speculative ones"/>
944 <event event="0x41" title="Java" name="SW bytecode execute" description="Counts the number of software java bytecodes being decoded, including speculative ones"/>
945 <event event="0x42" title="Jazelle" name="Backward branch execute" description="Counts the number of Jazelle taken branches being executed"/>
946 <event event="0x50" title="Cache" name="Coherency miss" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which also miss in all the other Cortex-A9 processors, meaning that the request is sent to the external memory"/>
947 <event event="0x51" title="Cache" name="Coherency hit" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which hit in another Cortex-A9 processor, meaning that the linefill data is fetched directly from the relevant Cortex-A9 cache"/>
948 <event event="0x60" title="Cache" name="Inst dependent stall" description="Counts the number of cycles where the processor is ready to accept new instructions, but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill"/>
949 <event event="0x61" title="Cache" name="Data dependent stall" description="Counts the number of cycles where the core has some instructions that it cannot issue to any pipeline, and the Load Store unit has at least one pending linefill request, and no pending TLB requests"/>
950 <event event="0x62" title="Cache" name="TLB stall" description="Counts the number of cycles where the processor is stalled waiting for the completion of translation table walks from the main TLB"/>
951 <event event="0x63" title="Intrinsic" name="STREX pass" description="Counts the number of STREX instructions architecturally executed and passed"/>
952 <event event="0x64" title="Intrinsic" name="STREX fail" description="Counts the number of STREX instructions architecturally executed and failed"/>
953 <event event="0x65" title="Cache" name="Data eviction" description="Counts the number of eviction requests because of a linefill in the data cache"/>
954 <event event="0x66" title="Pipeline" name="Issue stage no dispatch" description="Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions"/>
955 <event event="0x67" title="Pipeline" name="Issue stage empty" description="Counts the number of cycles where the issue stage is empty"/>
956 <event event="0x68" title="Instruction" name="Executed" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>
957 <event event="0x69" title="Cache" name="Data linefills" description="Counts the number of linefills performed on the external AXI bus"/>
958 <event event="0x6A" title="Cache" name="Prefetch linefills" description="Counts the number of data linefills caused by prefetcher requests"/>
959 <event event="0x6B" title="Cache" name="Prefetch hits" description="Counts the number of cache hits in a line that belongs to a stream followed by the prefetcher"/>
960 <event event="0x6E" title="Core" name="Functions" description="Counts the number of procedure returns whose condition codes do not fail, excluding all returns from exception"/>
961 <event event="0x70" title="Instruction" name="Main execution unit" description="Counts the number of instructions being executed in the main execution pipeline of the processor, the multiply pipeline and arithmetic logic unit pipeline"/>
962 <event event="0x71" title="Instruction" name="Second execution unit" description="Counts the number of instructions being executed in the processor second execution pipeline (ALU)"/>
963 <event event="0x72" title="Instruction" name="Load/Store" description="Counts the number of instructions being executed in the Load/Store unit"/>
964 <event event="0x73" title="Instruction" name="Floating point" description="Counts the number of Floating-point instructions going through the Register Rename stage"/>
965 <event event="0x74" title="Instruction" name="NEON" description="Counts the number of NEON instructions going through the Register Rename stage"/>
966 <event event="0x80" title="Stalls" name="PLD" description="Counts the number of cycles where the processor is stalled because PLD slots are all full"/>
967 <event event="0x81" title="Stalls" name="Memory write" description="Counts the number of cycles when the processor is stalled and the data side is stalled too because it is full and executing writes to the external memory"/>
968 <event event="0x82" title="Stalls" name="Inst main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side"/>
969 <event event="0x83" title="Stalls" name="Data main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the data side"/>
970 <event event="0x84" title="Stalls" name="Inst micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the instruction side"/>
971 <event event="0x85" title="Stalls" name="Data micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the data side"/>
972 <event event="0x86" title="Stalls" name="DMB" description="Counts the number of stall cycles because of the execution of a DMB memory barrier"/>
973 <event event="0x8A" title="Clock" name="Integer core" description="Counts the number of cycles during which the integer core clock is enabled"/>
974 <event event="0x8B" title="Clock" name="Data engine" description="Counts the number of cycles during which the Data Engine clock is enabled"/>
975 <event event="0x8C" title="Clock" name="NEON" description="Counts the number of cycles when the NEON SIMD clock is enabled"/>
976 <event event="0x8D" title="Memory" name="TLB inst allocations" description="Counts the number of TLB allocations because of Instruction requests"/>
977 <event event="0x8E" title="Memory" name="TLB data allocations" description="Counts the number of TLB allocations because of Data requests"/>
978 <event event="0x90" title="Instruction" name="ISB" description="Counts the number of ISB instructions architecturally executed"/>
979 <event event="0x91" title="Instruction" name="DSB" description="Counts the number of DSB instructions architecturally executed"/>
980 <event event="0x92" title="Instruction" name="DMB" description="Counts the number of DMB instructions speculatively executed"/>
981 <event event="0x93" title="External" name="Interrupts" description="Counts the number of external interrupts executed by the processor"/>
982 <event event="0xA0" title="PLE" name="Cache line rq completed" description="Counts the number of PLE cache line requests completed"/>
983 <event event="0xA1" title="PLE" name="Cache line rq skipped" description="Counts the number of PLE cache line requests skipped"/>
984 <event event="0xA2" title="PLE" name="FIFO flush" description="Counts the number of PLE FIFO flush requests"/>
985 <event event="0xA3" title="PLE" name="Request completed" description="Counts the number of PLE FIFO flush completed"/>
986 <event event="0xA4" title="PLE" name="FIFO overflow" description="Counts the number of PLE FIFO flush overflowed"/>
987 <event event="0xA5" title="PLE" name="Request programmed" description="Counts the number of PLE FIFO flush program requests"/>
988 </category>
989 <counter_set name="Krait_cnt" count="4"/>
990 <category name="Krait" counter_set="Krait_cnt" per_cpu="yes" supports_event_based_sampling="yes">
991 <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
992 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
993 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
994 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
995 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
996 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
997 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
998 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
999 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
1000 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
1001 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
1002 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
1003 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
1004 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
1005 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
1006 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
1007 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
1008 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
1009 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
1010 </category>
1011 <counter_set name="L2C-310_cnt" count="2"/>
1012 <category name="L2C-310" counter_set="L2C-310_cnt" per_cpu="no">
1013 <event event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
1014 <event event="0x2" title="L2 Cache" name="DRH" description="Data read hit"/>
1015 <event event="0x3" title="L2 Cache" name="DRREQ" description="Data read request"/>
1016 <event event="0x4" title="L2 Cache" name="DWHIT" description="Data write hit"/>
1017 <event event="0x5" title="L2 Cache" name="DWREQ" description="Data write request"/>
1018 <event event="0x6" title="L2 Cache" name="DWTREQ" description="Data write request with write-through attribute"/>
1019 <event event="0x7" title="L2 Cache" name="IRHIT" description="Instruction read hit"/>
1020 <event event="0x8" title="L2 Cache" name="IRREQ" description="Instruction read request"/>
1021 <event event="0x9" title="L2 Cache" name="WA" description="Write allocate"/>
1022 <event event="0xa" title="L2 Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
1023 <event event="0xb" title="L2 Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>
1024 <event event="0xc" title="L2 Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>
1025 <event event="0xd" title="L2 Cache" name="SRRCVD" description="Speculative read received"/>
1026 <event event="0xe" title="L2 Cache" name="SRCONF" description="Speculative read confirmed"/>
1027 <event event="0xf" title="L2 Cache" name="EPFRCVD" description="Prefetch hint received"/>
1028 </category>
1029 <category name="Linux">
1030 <event counter="Linux_irq_softirq" title="Interrupts" name="SoftIRQ" per_cpu="yes" description="Linux SoftIRQ taken"/>
1031 <event counter="Linux_irq_irq" title="Interrupts" name="IRQ" per_cpu="yes" description="Linux IRQ taken"/>
1032 <event counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/>
1033 <event counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/>
1034 <event counter="Linux_net_rx" title="Network" name="Receive" units="B" description="Receive network traffic, including effect from Streamline"/>
1035 <event counter="Linux_net_tx" title="Network" name="Transmit" units="B" description="Transmit network traffic, including effect from Streamline"/>
1036 <event counter="Linux_sched_switch" title="Scheduler" name="Switch" per_cpu="yes" description="Context switch events"/>
1037 <event counter="Linux_meminfo_memused" title="Memory" name="Used" class="absolute" units="B" proc="yes" description="Total used memory size. Note: a process' used memory includes shared memory that may be counted more than once (equivalent to RES from top). Kernel threads are not filterable."/>
1038 <event counter="Linux_meminfo_memfree" title="Memory" name="Free" class="absolute" display="minimum" units="B" description="Available memory size"/>
1039 <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" class="absolute" units="B" description="Memory used by OS disk buffers"/>
1040 <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" class="absolute" units="Hz" series_composition="overlay" average_cores="yes" description="Frequency setting of the CPU"/>
1041 <event counter="Linux_power_cpu_idle" title="Idle" name="State" per_cpu="yes" class="absolute" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
1042 <event counter="Linux_cpu_wait_contention" title="CPU Contention" name="Wait" per_cpu="no" class="activity" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on contended resource"/>
1043 <event counter="Linux_cpu_wait_io" title="CPU I/O" name="Wait" per_cpu="no" class="activity" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on I/O resource"/>
1044 </category>
1045
1046 <counter_set name="ARM_Mali-4xx_VP_0_cnt" count="2"/>
1047 <counter_set name="ARM_Mali-4xx_SW_cnt" count="0"/>
1048 <counter_set name="ARM_Mali-4xx_Filmstrip_cnt" count="1"/>
1049 <category name="Mali-4xx-VP" counter_set="ARM_Mali-4xx_VP_0_cnt" per_cpu="no">
1050 <event event="0x01" title="Mali GPU Vertex Processor" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active."/>
1051 <event event="0x02" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active."/>
1052 <event event="0x03" title="Mali GPU Vertex Processor" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active."/>
1053 <event event="0x04" title="Mali GPU Vertex Processor" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active."/>
1054 <event event="0x05" title="Mali GPU Vertex Processor" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader."/>
1055 <event event="0x06" title="Mali GPU Vertex Processor" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame."/>
1056 <event event="0x07" title="Mali GPU Vertex Processor" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame."/>
1057 <event event="0x08" title="Mali GPU Vertex Processor" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame."/>
1058 <event event="0x09" title="Mali GPU Vertex Processor" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame."/>
1059 <event event="0x0a" title="Mali GPU Vertex Processor" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame."/>
1060 <event event="0x0b" title="Mali GPU Vertex Processor" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame."/>
1061 <event event="0x0c" title="Mali GPU Vertex Processor" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame."/>
1062 <event event="0x0e" title="Mali GPU Vertex Processor" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen."/>
1063 <event event="0x0f" title="Mali GPU Vertex Processor" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame."/>
1064 <event event="0x10" title="Mali GPU Vertex Processor" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame ."/>
1065 <event event="0x13" title="Mali GPU Vertex Processor" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame."/>
1066 <event event="0x16" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/>
1067 <event event="0x17" title="Mali GPU Vertex Processor" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores."/>
1068 <event event="0x18" title="Mali GPU Vertex Processor" name="MaliGP2 PLBU cycles per frame" description="Number of cycles per frame the MaliGP2 PLBU output unit was active. This includes time spent waiting on the bus."/>
1069 <event event="0x19" title="Mali GPU Vertex Processor" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus."/>
1070 <event event="0x1b" title="Mali GPU Vertex Processor" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus."/>
1071 <event event="0x1c" title="Mali GPU Vertex Processor" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus."/>
1072 <event event="0x1e" title="Mali GPU Vertex Processor" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
1073 <event event="0x20" title="Mali GPU Vertex Processor" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoring. This includes time spent waiting on the bus."/>
1074 <event event="0x21" title="Mali GPU Vertex Processor" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
1075 </category>
1076 <category name="Mali GPU Fragment Processor" per_cpu="no">
1077 <counter_set name="ARM_Mali-4xx_FP_0_cnt" title="Mali-4xx FP0" description="Mali GPU Fragment Processor 0" count="2"/>
1078 <counter_set name="ARM_Mali-4xx_FP_1_cnt" title="Mali-4xx FP1" description="Mali GPU Fragment Processor 1" count="2"/>
1079 <counter_set name="ARM_Mali-4xx_FP_2_cnt" title="Mali-4xx FP2" description="Mali GPU Fragment Processor 2" count="2"/>
1080 <counter_set name="ARM_Mali-4xx_FP_3_cnt" title="Mali-4xx FP3" description="Mali GPU Fragment Processor 3" count="2"/>
1081 <counter_set name="ARM_Mali-4xx_FP_4_cnt" title="Mali-4xx FP4" description="Mali GPU Fragment Processor 4" count="2"/>
1082 <counter_set name="ARM_Mali-4xx_FP_5_cnt" title="Mali-4xx FP5" description="Mali GPU Fragment Processor 5" count="2"/>
1083 <counter_set name="ARM_Mali-4xx_FP_6_cnt" title="Mali-4xx FP6" description="Mali GPU Fragment Processor 6" count="2"/>
1084 <counter_set name="ARM_Mali-4xx_FP_7_cnt" title="Mali-4xx FP7" description="Mali GPU Fragment Processor 7" count="2"/>
1085
1086 <event event="0x00" title="Mali-4xx FP" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
1087 <event event="0x02" title="Mali-4xx FP" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
1088 <event event="0x03" title="Mali-4xx FP" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
1089 <event event="0x04" title="Mali-4xx FP" name="Bus read request cycles" description="Number of cycles during which the bus read request signal was HIGH."/>
1090 <event event="0x05" title="Mali-4xx FP" name="Bus write request cycles" description="Number of cycles during which the bus write request signal was HIGH."/>
1091 <event event="0x06" title="Mali-4xx FP" name="Bus read transactions count" description="Number of read requests accepted by the bus."/>
1092 <event event="0x07" title="Mali-4xx FP" name="Bus write transactions" description="Number of write requests accepted by the bus."/>
1093 <event event="0x09" title="Mali-4xx FP" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit."/>
1094 <event event="0x0a" title="Mali-4xx FP" name="Store unit writes" description="64-bit words written to the bus by the store unit."/>
1095 <event event="0x0d" title="Mali-4xx FP" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache."/>
1096 <event event="0x0e" title="Mali-4xx FP" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader."/>
1097 <event event="0x0f" title="Mali-4xx FP" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register."/>
1098 <event event="0x10" title="Mali-4xx FP" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache."/>
1099 <event event="0x11" title="Mali-4xx FP" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table."/>
1100 <event event="0x12" title="Mali-4xx FP" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache."/>
1101 <event event="0x13" title="Mali-4xx FP" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus."/>
1102 <event event="0x14" title="Mali-4xx FP" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus."/>
1103 <event event="0x15" title="Mali-4xx FP" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table."/>
1104 <event event="0x17" title="Mali-4xx FP" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction."/>
1105 <event event="0x18" title="Mali-4xx FP" name="Polygon count" description="Number of triangles read from the polygon list."/>
1106 <event event="0x19" title="Mali-4xx FP" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list."/>
1107 <event event="0x1a" title="Mali-4xx FP" name="Lines count" description="Number of lines read from the polygon list."/>
1108 <event event="0x1b" title="Mali-4xx FP" name="Points count" description="Number of points read from the polygon list."/>
1109 <event event="0x1c" title="Mali-4xx FP" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected."/>
1110 <event event="0x1d" title="Mali-4xx FP" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input."/>
1111 <event event="0x1e" title="Mali-4xx FP" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer."/>
1112 <event event="0x1f" title="Mali-4xx FP" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad."/>
1113 <event event="0x20" title="Mali-4xx FP" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed."/>
1114 <event event="0x21" title="Mali-4xx FP" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill."/>
1115 <event event="0x22" title="Mali-4xx FP" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test."/>
1116 <event event="0x23" title="Mali-4xx FP" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels."/>
1117 <event event="0x24" title="Mali-4xx FP" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection."/>
1118 <event event="0x25" title="Mali-4xx FP" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs."/>
1119 <event event="0x26" title="Mali-4xx FP" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous."/>
1120 <event event="0x27" title="Mali-4xx FP" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation."/>
1121 <event event="0x28" title="Mali-4xx FP" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation."/>
1122 <event event="0x29" title="Mali-4xx FP" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation."/>
1123 <event event="0x2a" title="Mali-4xx FP" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer."/>
1124 <event event="0x2b" title="Mali-4xx FP" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation."/>
1125 <event event="0x2c" title="Mali-4xx FP" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported."/>
1126 <event event="0x2d" title="Mali-4xx FP" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active."/>
1127 <event event="0x2e" title="Mali-4xx FP" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed."/>
1128 <event event="0x2f" title="Mali-4xx FP" name="Texture mapper cycle count" description="Number of texture operation cycles."/>
1129 <event event="0x30" title="Mali-4xx FP" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)."/>
1130 <event event="0x31" title="Mali-4xx FP" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)."/>
1131 <event event="0x32" title="Mali-4xx FP" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)."/>
1132 <event event="0x33" title="Mali-4xx FP" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)."/>
1133 <event event="0x34" title="Mali-4xx FP" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
1134 <event event="0x35" title="Mali-4xx FP" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)."/>
1135 <event event="0x36" title="Mali-4xx FP" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)."/>
1136 <event event="0x37" title="Mali-4xx FP" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
1137 <event event="0x38" title="Mali-4xx FP" name="Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>
1138 <event event="0x39" title="Mali-4xx FP" name="Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>
1139 <event event="0x3a" title="Mali-4xx FP" name="Load/Store cache hit count" description="Number of hits in the load/store cache."/>
1140 <event event="0x3b" title="Mali-4xx FP" name="Load/Store cache miss count" description="Number of misses in the load/store cache."/>
1141 <event event="0x3c" title="Mali-4xx FP" name="Program cache hit count" description="Number of hits in the program cache."/>
1142 <event event="0x3d" title="Mali-4xx FP" name="Program cache miss count" description="Number of misses in the program cache."/>
1143 </category>
1144 <counter_set name="ARM_Mali-4xx_L2_0_cnt" title="Mali-4xx L2 0" description="Mali GPU L2 Cache Core 0" count="2"/>
1145 <category name="Mali-4xx-L2_0" counter_set="ARM_Mali-4xx_L2_0_cnt" per_cpu="no">
1146 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
1147 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
1148
1149 <option_set name="All">
1150 <option event_delta="0x08" name="Master" description="Master"/>
1151 <option event_delta="0x10" name="All slaves" description="All slaves"/>
1152 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
1153 <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
1154 <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
1155 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
1156 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
1157 </option_set>
1158
1159 <option_set name="Slaves">
1160 <option event_delta="0x10" name="All slaves" description="All slaves"/>
1161 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
1162 <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
1163 <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
1164 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
1165 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
1166 </option_set>
1167
1168 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
1169 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
1170 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
1171 <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
1172 <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
1173 <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
1174 <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
1175 <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
1176 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
1177 </category>
1178 <counter_set name="ARM_Mali-4xx_L2_1_cnt" title="Mali-4xx L2 1" description="Mali GPU L2 Cache Core 1" count="2"/>
1179 <category name="Mali-4xx-L2_1" counter_set="ARM_Mali-4xx_L2_1_cnt" per_cpu="no">
1180 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
1181 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
1182
1183 <option_set name="All">
1184 <option event_delta="0x08" name="Master" description="Master"/>
1185 <option event_delta="0x10" name="All slaves" description="All slaves"/>
1186 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
1187 <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
1188 <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
1189 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
1190 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
1191 </option_set>
1192
1193 <option_set name="Slaves">
1194 <option event_delta="0x10" name="All slaves" description="All slaves"/>
1195 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
1196 <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
1197 <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
1198 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
1199 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
1200 </option_set>
1201
1202 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
1203 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
1204 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
1205 <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
1206 <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
1207 <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
1208 <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
1209 <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
1210 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
1211 </category>
1212 <counter_set name="ARM_Mali-4xx_L2_2_cnt" title="Mali-4xx L2 2" description="Mali GPU L2 Cache Core 2" count="2"/>
1213 <category name="Mali-4xx-L2_2" counter_set="ARM_Mali-4xx_L2_2_cnt" per_cpu="no">
1214 <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
1215 <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
1216
1217 <option_set name="All">
1218 <option event_delta="0x08" name="Master" description="Master"/>
1219 <option event_delta="0x10" name="All slaves" description="All slaves"/>
1220 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
1221 <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
1222 <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
1223 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
1224 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
1225 </option_set>
1226
1227 <option_set name="Slaves">
1228 <option event_delta="0x10" name="All slaves" description="All slaves"/>
1229 <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
1230 <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
1231 <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
1232 <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
1233 <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
1234 </option_set>
1235
1236 <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
1237 <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
1238 <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
1239 <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
1240 <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
1241 <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
1242 <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
1243 <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
1244 <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
1245 </category>
1246 <category name="ARM Mali-4xx Filmstrip" counter_set="ARM_Mali-4xx_Filmstrip_cnt" per_cpu="no">
1247 <option_set name="fs">
1248 <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/>
1249 <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/>
1250 <option event_delta="0xa" name="1:10" description="captures every 10th frame"/>
1251 </option_set>
1252 <event event="0x0400" option_set="fs" title="ARM Mali-4xx" name="Filmstrip" description="Scaled framebuffer"/>
1253 </category>
1254 <category name="ARM_Mali-4xx_Voltage" per_cpu="no">
1255 <event counter="ARM_Mali-4xx_Voltage" title="Mali GPU Voltage" name="Voltage" class="absolute" display="average" average_selection="yes" units="mV" description="GPU core voltage."/>
1256 </category>
1257 <category name="ARM_Mali-4xx_Frequency" per_cpu="no">
1258 <event counter="ARM_Mali-4xx_Frequency" title="Mali GPU Frequency" name="Frequency" display="average" average_selection="yes" units="MHz" description="GPU core frequency."/>
1259 </category>
1260 <category name="Mali-4xx-SW" counter_set="ARM_Mali-4xx_SW_cnt" per_cpu="no">
1261 <!-- EGL Counters -->
1262 <event counter="ARM_Mali-4xx_SW_0" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the framebuffer from video memory to framebuffer."/>
1263 <!-- glDrawElements Counters -->
1264 <event counter="ARM_Mali-4xx_SW_1" title="glDrawElements Statistics" name="Calls to glDrawElements" description="Number of calls to glDrawElements."/>
1265 <event counter="ARM_Mali-4xx_SW_2" title="glDrawElements Statistics" name="Indices to glDrawElements" description="Number of indices to glDrawElements."/>
1266 <event counter="ARM_Mali-4xx_SW_3" title="glDrawElements Statistics" name="Transformed by glDrawElements" description="Number of vertices transformed by glDrawElements."/>
1267 <!-- glDrawArrays Counters -->
1268 <event counter="ARM_Mali-4xx_SW_4" title="glDrawArrays Statistics" name="Calls to glDrawArrays" description="Number of calls to glDrawArrays."/>
1269 <event counter="ARM_Mali-4xx_SW_5" title="glDrawArrays Statistics" name="Transformed by glDrawArrays" description="Number of vertices transformed by glDrawArrays."/>
1270 <!-- Draw Call Counters -->
1271 <event counter="ARM_Mali-4xx_SW_6" title="Drawcall Statistics" name="Points" description="Number of calls to glDraw* with parameter GL_POINTS."/>
1272 <event counter="ARM_Mali-4xx_SW_7" title="Drawcall Statistics" name="Lines" description="Number of calls to glDraw* with parameter GL_LINES."/>
1273 <event counter="ARM_Mali-4xx_SW_8" title="Drawcall Statistics" name="Lineloop" description="Number of calls to glDraw* with parameter GL_LINE_LOOP."/>
1274 <event counter="ARM_Mali-4xx_SW_9" title="Drawcall Statistics" name="Linestrip" description="Number of calls to glDraw* with parameter GL_LINE_STRIP."/>
1275 <event counter="ARM_Mali-4xx_SW_10" title="Drawcall Statistics" name="Triangles" description="Number of calls to glDraw* with parameter GL_TRIANGLES."/>
1276 <event counter="ARM_Mali-4xx_SW_11" title="Drawcall Statistics" name="Trianglestrip" description="Number of calls to glDraw* with parameter GL_TRIANGLE_STRIP."/>
1277 <event counter="ARM_Mali-4xx_SW_12" title="Drawcall Statistics" name="Trianglefan" description="Number of calls to glDraw* with parameter GL_TRIANGLE_FAN."/>
1278 <event counter="ARM_Mali-4xx_SW_13" title="Drawcall Statistics" name="Vertex Upload Time (us)" description="Time spent uploading vertex attributes and faceindex data not present in a VBO."/>
1279 <event counter="ARM_Mali-4xx_SW_14" title="Drawcall Statistics" name="Uniform Bytes Copied (bytes)" description="Number of bytes copied to Mali memory as a result of uniforms update."/>
1280 <!-- Buffer Profiling Counters -->
1281 <event counter="ARM_Mali-4xx_SW_15" title="Buffer Profiling" name="Texture Upload Time (ms)" description="Time spent uploading textures."/>
1282 <event counter="ARM_Mali-4xx_SW_16" title="Buffer Profiling" name="VBO Upload Time (ms)" description="Time spent uploading vertex buffer objects."/>
1283 <event counter="ARM_Mali-4xx_SW_17" title="Buffer Profiling" name="FBO Flushes" description="Number of flushed on framebuffer attachment."/>
1284 <!-- OpenGL ES 1.1 Emulation -->
1285 <event counter="ARM_Mali-4xx_SW_18" title="Fixed-function Emulation" name="# Vertex Shaders Generated" description="Number of vertex shaders generated."/>
1286 <event counter="ARM_Mali-4xx_SW_19" title="Fixed-function Emulation" name="# Fragment Shaders Generated" description="Number of fragment shaders generated."/>
1287 <!-- Geometry Statistics -->
1288 <event counter="ARM_Mali-4xx_SW_33" title="Geometry Statistics" name="Triangles" description="The total number of triangles passed to GLES per-frame."/>
1289 <event counter="ARM_Mali-4xx_SW_34" title="Geometry Statistics" name="Independent Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLES."/>
1290 <event counter="ARM_Mali-4xx_SW_35" title="Geometry Statistics" name="Strip Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_STRIP."/>
1291 <event counter="ARM_Mali-4xx_SW_36" title="Geometry Statistics" name="Fan Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_FAN."/>
1292 <event counter="ARM_Mali-4xx_SW_37" title="Geometry Statistics" name="Lines" description="Number of lines passed to GLES per-frame."/>
1293 <event counter="ARM_Mali-4xx_SW_38" title="Geometry Statistics" name="Independent Lines" description="Number of lines passed to GLES using the mode GL_LINES."/>
1294 <event counter="ARM_Mali-4xx_SW_39" title="Geometry Statistics" name="Strip Lines" description="Number of lines passed to GLES using the mode GL_LINE_STRIP."/>
1295 <event counter="ARM_Mali-4xx_SW_40" title="Geometry Statistics" name="Loop Lines" description="Number of lines passed to GLES using the mode GL_LINE_LOOP."/>
1296 </category>
1297
1298 <category name="Mali-T6xx-JobManager" per_cpu="no">
1299
1300 <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali Job Manager Cycles" name="GPU cycles" description="Number of cycles the GPU was active"/>
1301 <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali Job Manager Cycles" name="IRQ cycles" description="Number of cycles the GPU had a pending interrupt"/>
1302 <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali Job Manager Cycles" name="JS0 cycles" description="Number of cycles JS0 (fragment) was active"/>
1303 <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali Job Manager Cycles" name="JS1 cycles" description="Number of cycles JS1 (vertex/tiler/compute) was active"/>
1304 <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali Job Manager Cycles" name="JS2 cycles" description="Number of cycles JS2 (vertex/compute) was active"/>
1305
1306 <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali Job Manager Work" name="JS0 jobs" description="Number of Jobs (fragment) completed in JS0"/>
1307 <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali Job Manager Work" name="JS0 tasks" description="Number of Tasks completed in JS0"/>
1308 <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali Job Manager Work" name="JS1 jobs" description="Number of Jobs (vertex/tiler/compute) completed in JS1"/>
1309 <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali Job Manager Work" name="JS1 tasks" description="Number of Tasks completed in JS1"/>
1310 <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali Job Manager Work" name="JS2 tasks" description="Number of Tasks completed in JS2"/>
1311 <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali Job Manager Work" name="JS2 jobs" description="Number of Jobs (vertex/compute) completed in JS2"/>
1312
1313 </category>
1314
1315 <category name="Mali-T6xx-Tiler" per_cpu="no">
1316
1317 <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali Tiler Primitives" name="Polygons" description="Number of polygons processed"/>
1318 <event counter="ARM_Mali-T6xx_QUADS" title="Mali Tiler Primitives" name="Quads" description="Number of quads processed"/>
1319 <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali Tiler Primitives" name="Triangles" description="Number of triangles processed"/>
1320 <event counter="ARM_Mali-T6xx_LINES" title="Mali Tiler Primitives" name="Lines" description="Number of lines processed"/>
1321 <event counter="ARM_Mali-T6xx_POINTS" title="Mali Tiler Primitives" name="Points" description="Number of points processed"/>
1322
1323 <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali Tiler Culling" name="Front facing prims" description="Number of front facing primitives"/>
1324 <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali Tiler Culling" name="Back facing prims" description="Number of back facing primitives"/>
1325 <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali Tiler Culling" name="Visible prims" description="Number of visible primitives"/>
1326 <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali Tiler Culling" name="Culled prims" description="Number of culled primitives"/>
1327 <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali Tiler Culling" name="Clipped prims" description="Number of clipped primitives"/>
1328
1329 <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali Tiler Hierarchy" name="L0 prims" description="Number of primitives in hierarchy level 0"/>
1330 <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali Tiler Hierarchy" name="L1 prims" description="Number of primitives in hierarchy level 1"/>
1331 <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali Tiler Hierarchy" name="L2 prims" description="Number of primitives in hierarchy level 2"/>
1332 <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali Tiler Hierarchy" name="L3 prims" description="Number of primitives in hierarchy level 3"/>
1333 <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali Tiler Hierarchy" name="L4 prims" description="Number of primitives in hierarchy level 4"/>
1334 <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali Tiler Hierarchy" name="L5 prims" description="Number of primitives in hierarchy level 5"/>
1335 <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali Tiler Hierarchy" name="L6 prims" description="Number of primitives in hierarchy level 6"/>
1336 <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali Tiler Hierarchy" name="L7 prims" description="Number of primitives in hierarchy level 7"/>
1337
1338 <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali Tiler Commands" name="Prims in 1 command" description="Number of primitives producing 1 command"/>
1339 <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali Tiler Commands" name="Prims in 2 command" description="Number of primitives producing 2 commands"/>
1340 <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali Tiler Commands" name="Prims in 3 command" description="Number of primitives producing 3 commands"/>
1341 <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali Tiler Commands" name="Prims in 4 command" description="Number of primitives producing 4 commands"/>
1342 <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali Tiler Commands" name="Prims in 4-7 commands" description="Number of primitives producing 4-7 commands"/>
1343 <event counter="ARM_Mali-T6xx_COMMAND_5_7" title="Mali Tiler Commands" name="Prims in 5-7 commands" description="Number of primitives producing 5-7 commands"/>
1344 <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali Tiler Commands" name="Prims in 8-15 commands" description="Number of primitives producing 8-15 commands"/>
1345 <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali Tiler Commands" name="Prims in 16-63 commands" description="Number of primitives producing 16-63 commands"/>
1346 <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali Tiler Commands" name="Prims in &gt;= 64 commands" description="Number of primitives producing &gt;= 64 commands"/>
1347
1348 </category>
1349
1350 <category name="Mali-T6xx-ShaderCore" per_cpu="no">
1351
1352 <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Mali Core Cycles" name="Tripipe cycles" description="Number of cycles the Tripipe was active"/>
1353 <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Mali Core Cycles" name="Fragment cycles" description="Number of cycles fragment processing was active"/>
1354 <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Mali Core Cycles" name="Compute cycles" description="Number of cycles vertex\compute processing was active"/>
1355 <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Mali Core Cycles" name="Fragment cycles waiting for tile" description="Number of cycles spent waiting for a physical tile buffer"/>
1356
1357 <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Mali Core Threads" name="Fragment threads" description="Number of fragment threads started"/>
1358 <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Mali Core Threads" name="Dummy fragment threads" description="Number of dummy fragment threads started"/>
1359 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
1360 <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
1361 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
1362 <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
1363
1364 <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Mali Compute Threads" name="Compute tasks" description="Number of compute tasks"/>
1365 <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Mali Compute Threads" name="Compute threads started" description="Number of compute threads started"/>
1366 <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Mali Compute Threads" name="Compute cycles awaiting descriptors" description="Number of compute cycles spent waiting for descriptors"/>
1367
1368 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
1369 <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
1370 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
1371 <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
1372
1373 <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Mali Fragment Quads" name="Quads rasterized" description="Number of quads rasterized"/>
1374 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Mali Fragment Quads" name="Quads doing early ZS" description="Number of quads doing early ZS test"/>
1375 <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Mali Fragment Quads" name="Quads killed early Z" description="Number of quads killed by early ZS test"/>
1376
1377 <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Mali Fragment Tasks" name="Tiles rendered" description="Number of tiles rendered"/>
1378 <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Mali Fragment Tasks" name="Tile writes killed by TE" description="Number of tile writes skipped by transaction elimination"/>
1379
1380 <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Mali Arithmetic Pipe" name="A instructions" description="Number of instructions completed by the the A-pipe (normalized per pipeline)"/>
1381
1382 <event counter="ARM_Mali-T6xx_LS_WORDS" title="Mali Load/Store Pipe" name="LS instructions" description="Number of instructions completed by the LS-pipe"/>
1383 <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Mali Load/Store Pipe" name="LS instruction issues" description="Number of instructions issued to the LS-pipe, including restarts"/>
1384
1385 <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Mali Texture Pipe" name="T instructions" description="Number of instructions completed by the T-pipe"/>
1386 <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Mali Texture Pipe" name="T instruction issues" description="Number of instructions issused to the T-pipe, including restarts"/>
1387 <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Mali Texture Pipe" name="Cache misses" description="Number of instructions in the T-pipe, recirculated due to cache miss"/>
1388
1389 <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Mali Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store cache"/>
1390 <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Mali Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store cache"/>
1391 <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Mali Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store cache"/>
1392 <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Mali Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store cache"/>
1393 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Mali Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store cache"/>
1394 <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Mali Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store cache"/>
1395 <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Mali Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store cache"/>
1396 <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Mali Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store cache"/>
1397 <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Mali Load/Store Cache" name="Snoops in to LSC" description="Number of coherent memory snoops in to the Load/Store cache"/>
1398
1399 </category>
1400
1401 <category name="Mali-T6xx-L2AndMMU" per_cpu="no">
1402
1403 <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="Mali L2 Cache" name="External write beats" description="Number of external bus write beats"/>
1404 <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="Mali L2 Cache" name="External read beats" description="Number of external bus read beats"/>
1405 <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="Mali L2 Cache" name="Read snoops" description="Number of read transaction snoops"/>
1406 <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="Mali L2 Cache" name="L2 read hits" description="Number of reads hitting in the L2 cache"/>
1407 <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="Mali L2 Cache" name="Write snoops" description="Number of write transaction snoops"/>
1408 <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="Mali L2 Cache" name="L2 write hits" description="Number of writes hitting in the L2 cache"/>
1409 <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="Mali L2 Cache" name="External bus stalls (AR)" description="Number of cycles a valid read address (AR) is stalled by the external interconnect"/>
1410 <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="Mali L2 Cache" name="External bus stalls (W)" description="Number of cycles a valid write data (W channel) is stalled by the external interconnect"/>
1411
1412 </category>
1413
1414 <category name="Mali-T6xx-SW-counters" per_cpu="no">
1415 <event counter="ARM_Mali-T6xx_TOTAL_ALLOC_PAGES" title="Mali Total Alloc Pages" name="Total number of allocated pages" description="Mali total number of allocated pages."/>
1416 </category>
1417
1418 <category name="Mali-T6xx-PMShader" per_cpu="no">
1419 <event counter="ARM_Mali-T6xx_PM_SHADER_0" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
1420 <event counter="ARM_Mali-T6xx_PM_SHADER_1" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
1421 <event counter="ARM_Mali-T6xx_PM_SHADER_2" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
1422 <event counter="ARM_Mali-T6xx_PM_SHADER_3" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/>
1423 <event counter="ARM_Mali-T6xx_PM_SHADER_4" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/>
1424 <event counter="ARM_Mali-T6xx_PM_SHADER_5" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/>
1425 <event counter="ARM_Mali-T6xx_PM_SHADER_6" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
1426 <event counter="ARM_Mali-T6xx_PM_SHADER_7" class="absolute" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
1427 </category>
1428
1429 <category name="Mali-T6xx-PMTiler" per_cpu="no">
1430 <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
1431 </category>
1432
1433 <category name="Mali-T6xx-PML2" per_cpu="no">
1434 <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
1435 <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
1436 </category>
1437
1438 <category name="Mali-T6xx-MMU_AS" per_cpu="no">
1439 <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
1440 <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
1441 <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
1442 <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
1443 </category>
1444
1445 <category name="Mali-T6xx-MMU_page_fault" per_cpu="no">
1446 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_0" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 0" description="Reports the number of newly allocated pages after a MMU page fault in address space 0."/>
1447 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_1" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 1" description="Reports the number of newly allocated pages after a MMU page fault in address space 1."/>
1448 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_2" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 2" description="Reports the number of newly allocated pages after a MMU page fault in address space 2."/>
1449 <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_3" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 3" description="Reports the number of newly allocated pages after a MMU page fault in address space 3."/>
1450 </category>
1451
1452 <counter_set name="ARM_Mali-T6xx_Filmstrip_cnt" count="1"/>
1453 <category name="ARM Mali-T6xx Filmstrip" counter_set="ARM_Mali-T6xx_Filmstrip_cnt" per_cpu="no">
1454 <option_set name="fs">
1455 <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/>
1456 <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/>
1457 <option event_delta="0xa" name="1:10" description="captures every 10th frame"/>
1458 </option_set>
1459 <event event="0x0400" option_set="fs" title="ARM Mali-T6xx" name="Filmstrip" description="Scaled framebuffer"/>
1460 </category>
1461 <counter_set name="Perf_Hardware_cnt" count="6"/>
1462 <category name="Perf Hardware" counter_set="Perf_Hardware_cnt" per_cpu="yes" supports_event_based_sampling="yes">
1463 <event counter="Perf_Hardware_ccnt" event="0" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
1464 <event event="1" title="Instruction" name="Executed" description="Instruction executed"/>
1465 <event event="2" title="Cache" name="References" description="Cache References"/>
1466 <event event="3" title="Cache" name="Misses" description="Cache Misses"/>
1467 <event event="4" title="Branch" name="Instructions" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
1468 <event event="5" title="Branch" name="Misses" description="Branch mispredicted or not predicted"/>
1469 <event event="6" title="Bus" name="Cycles" description="Bus Cycles"/>
1470 <event event="7" title="Instruction" name="Stalled Frontend" description="Stalled Frontend Cycles"/>
1471 <event event="8" title="Instruction" name="Stalled Backend" description="Stalled Backend Cycles"/>
1472 </category>
1473 <counter_set name="ScorpionMP_cnt" count="4"/>
1474 <category name="ScorpionMP" counter_set="ScorpionMP_cnt" per_cpu="yes" supports_event_based_sampling="yes">
1475 <event counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
1476 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
1477 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
1478 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
1479 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
1480 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
1481 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
1482 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
1483 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
1484 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
1485 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
1486 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
1487 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
1488 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
1489 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
1490 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
1491 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
1492 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
1493 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
1494 <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>
1495 <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>
1496 <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>
1497 <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>
1498 <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>
1499 <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>
1500 <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>
1501 <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>
1502 <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>
1503 <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>
1504 <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>
1505 <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>
1506 <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>
1507 <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>
1508 <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>
1509 <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>
1510 <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>
1511 <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>
1512 <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>
1513 <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>
1514 <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>
1515 <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>
1516 <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>
1517 <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>
1518 <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>
1519 <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>
1520 <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>
1521 <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>
1522 <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>
1523 <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>
1524 <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>
1525 <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>
1526 <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>
1527 <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>
1528 <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>
1529 <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>
1530 <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>
1531 <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>
1532 <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>
1533 <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>
1534 <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>
1535 <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>
1536 <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>
1537 <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>
1538 <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>
1539 <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>
1540 <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>
1541 <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>
1542 <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>
1543 <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>
1544 <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>
1545 <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>
1546 <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>
1547 <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>
1548 <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>
1549 <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>
1550 <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>
1551 <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>
1552 <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>
1553 <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>
1554 <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>
1555 <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>
1556 <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>
1557 <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>
1558 <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>
1559 <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>
1560 <event event="0x8e" title="ScorpionMP" name="NUM_BARRIERS" description="Barriers"/>
1561 <event event="0x8f" title="ScorpionMP" name="BARRIER_CYCLES" description="Barrier cycles"/>
1562 </category>
1563 <counter_set name="Scorpion_cnt" count="4"/>
1564 <category name="Scorpion" counter_set="Scorpion_cnt" per_cpu="yes" supports_event_based_sampling="yes">
1565 <event counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
1566 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
1567 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
1568 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
1569 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
1570 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
1571 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
1572 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
1573 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
1574 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
1575 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
1576 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
1577 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
1578 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
1579 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
1580 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
1581 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
1582 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
1583 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
1584 <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>
1585 <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>
1586 <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>
1587 <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>
1588 <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>
1589 <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>
1590 <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>
1591 <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>
1592 <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>
1593 <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>
1594 <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>
1595 <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>
1596 <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>
1597 <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>
1598 <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>
1599 <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>
1600 <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>
1601 <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>
1602 <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>
1603 <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>
1604 <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>
1605 <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>
1606 <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>
1607 <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>
1608 <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>
1609 <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>
1610 <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>
1611 <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>
1612 <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>
1613 <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>
1614 <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>
1615 <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>
1616 <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>
1617 <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>
1618 <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>
1619 <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>
1620 <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>
1621 <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>
1622 <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>
1623 <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>
1624 <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>
1625 <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>
1626 <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>
1627 <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>
1628 <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>
1629 <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>
1630 <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>
1631 <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>
1632 <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>
1633 <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>
1634 <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>
1635 <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>
1636 <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>
1637 <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>
1638 <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>
1639 <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>
1640 <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>
1641 <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>
1642 <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>
1643 <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>
1644 <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>
1645 <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>
1646 <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>
1647 <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>
1648 <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>
1649 <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>
1650 <event event="0x8e" title="Scorpion" name="BANK_AB_HIT" description="L2 hit rates bank A/B hits"/>
1651 <event event="0x8f" title="Scorpion" name="BANK_AB_ACCESS" description="L2 hit rates bank A/B accesses"/>
1652 <event event="0x90" title="Scorpion" name="BANK_CD_HIT" description="L2 hit rates bank C/D hits"/>
1653 <event event="0x91" title="Scorpion" name="BANK_CD_ACCESS" description="L2 hit rates bank C/D accesses"/>
1654 <event event="0x92" title="Scorpion" name="BANK_AB_DSIDE_HIT" description="L2 hit rates bank A/B d-side hits"/>
1655 <event event="0x93" title="Scorpion" name="BANK_AB_DSIDE_ACCESS" description="L2 hit rates bank A/B d-side accesses"/>
1656 <event event="0x94" title="Scorpion" name="BANK_CD_DSIDE_HIT" description="L2 hit rates bank C/D d-side hits"/>
1657 <event event="0x95" title="Scorpion" name="BANK_CD_DSIDE_ACCESS" description="L2 hit rates bank C/D d-side accesses"/>
1658 <event event="0x96" title="Scorpion" name="BANK_AB_ISIDE_HIT" description="L2 hit rates bank A/B i-side hits"/>
1659 <event event="0x97" title="Scorpion" name="BANK_AB_ISIDE_ACCESS" description="L2 hit rates bank A/B i-side accesses"/>
1660 <event event="0x98" title="Scorpion" name="BANK_CD_ISIDE_HIT" description="L2 hit rates bank C/D i-side hits"/>
1661 <event event="0x99" title="Scorpion" name="BANK_CD_ISIDE_ACCESS" description="L2 hit rates bank C/D i-side accesses"/>
1662 <event event="0x9a" title="Scorpion" name="ISIDE_RD_WAIT" description="fills and castouts cycles that i-side RD requests wait on data from bus"/>
1663 <event event="0x9b" title="Scorpion" name="DSIDE_RD_WAIT" description="fills and castouts cycles that d-side RD requests wait on data from bus"/>
1664 <event event="0x9c" title="Scorpion" name="BANK_BYPASS_WRITE" description="fills and castouts bank bypass writes"/>
1665 <event event="0x9d" title="Scorpion" name="BANK_AB_NON_CASTOUT" description="fills and castouts bank A/B non-castout writes to bus"/>
1666 <event event="0x9e" title="Scorpion" name="BANK_AB_L2_CASTOUT" description="fills and castouts bank A/B L2 castouts (granules)"/>
1667 <event event="0x9f" title="Scorpion" name="BANK_CD_NON_CASTOUT" description="fills and castouts bank C/D non-castout writes to bus"/>
1668 <event event="0xa0" title="Scorpion" name="BANK_CD_L2_CASTOUT" description="fills and castouts bank C/D L2 castouts (granules)"/>
1669 </category>
1670</events>
diff --git a/daemon/events_xml.h b/daemon/events_xml.h
new file mode 100644
index 0000000..bf97458
--- /dev/null
+++ b/daemon/events_xml.h
@@ -0,0 +1,16317 @@
1static const unsigned char events_xml[] = {
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16310 0x6f, 0x75, 0x74, 0x73, 0x20, 0x62, 0x61, 0x6e, 0x6b, 0x20, 0x43, 0x2f,
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16315 0x74, 0x73, 0x3e, 0x0a, 0x00
16316};
16317static const unsigned int events_xml_len = 195760;
diff --git a/daemon/k/perf_event.h b/daemon/k/perf_event.h
index e5dff8c..e886c48 120000..100644
--- a/daemon/k/perf_event.h
+++ b/daemon/k/perf_event.h
@@ -1 +1,792 @@
1perf_event.3.12.h \ No newline at end of file 1/*
2 * Performance events:
3 *
4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
7 *
8 * Data type definitions, declarations, prototypes.
9 *
10 * Started by: Thomas Gleixner and Ingo Molnar
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14#ifndef _LINUX_PERF_EVENT_H
15#define _LINUX_PERF_EVENT_H
16
17#include <linux/types.h>
18#include <linux/ioctl.h>
19#include <asm/byteorder.h>
20
21/*
22 * User-space ABI bits:
23 */
24
25/*
26 * attr.type
27 */
28enum perf_type_id {
29 PERF_TYPE_HARDWARE = 0,
30 PERF_TYPE_SOFTWARE = 1,
31 PERF_TYPE_TRACEPOINT = 2,
32 PERF_TYPE_HW_CACHE = 3,
33 PERF_TYPE_RAW = 4,
34 PERF_TYPE_BREAKPOINT = 5,
35
36 PERF_TYPE_MAX, /* non-ABI */
37};
38
39/*
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
42 * syscall:
43 */
44enum perf_hw_id {
45 /*
46 * Common hardware events, generalized by the kernel:
47 */
48 PERF_COUNT_HW_CPU_CYCLES = 0,
49 PERF_COUNT_HW_INSTRUCTIONS = 1,
50 PERF_COUNT_HW_CACHE_REFERENCES = 2,
51 PERF_COUNT_HW_CACHE_MISSES = 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
53 PERF_COUNT_HW_BRANCH_MISSES = 5,
54 PERF_COUNT_HW_BUS_CYCLES = 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
58
59 PERF_COUNT_HW_MAX, /* non-ABI */
60};
61
62/*
63 * Generalized hardware cache events:
64 *
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
68 */
69enum perf_hw_cache_id {
70 PERF_COUNT_HW_CACHE_L1D = 0,
71 PERF_COUNT_HW_CACHE_L1I = 1,
72 PERF_COUNT_HW_CACHE_LL = 2,
73 PERF_COUNT_HW_CACHE_DTLB = 3,
74 PERF_COUNT_HW_CACHE_ITLB = 4,
75 PERF_COUNT_HW_CACHE_BPU = 5,
76 PERF_COUNT_HW_CACHE_NODE = 6,
77
78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
79};
80
81enum perf_hw_cache_op_id {
82 PERF_COUNT_HW_CACHE_OP_READ = 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
85
86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
87};
88
89enum perf_hw_cache_op_result_id {
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
92
93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
94};
95
96/*
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
100 * well):
101 */
102enum perf_sw_ids {
103 PERF_COUNT_SW_CPU_CLOCK = 0,
104 PERF_COUNT_SW_TASK_CLOCK = 1,
105 PERF_COUNT_SW_PAGE_FAULTS = 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
111 PERF_COUNT_SW_EMULATION_FAULTS = 8,
112 PERF_COUNT_SW_DUMMY = 9,
113
114 PERF_COUNT_SW_MAX, /* non-ABI */
115};
116
117/*
118 * Bits that can be set in attr.sample_type to request information
119 * in the overflow packets.
120 */
121enum perf_event_sample_format {
122 PERF_SAMPLE_IP = 1U << 0,
123 PERF_SAMPLE_TID = 1U << 1,
124 PERF_SAMPLE_TIME = 1U << 2,
125 PERF_SAMPLE_ADDR = 1U << 3,
126 PERF_SAMPLE_READ = 1U << 4,
127 PERF_SAMPLE_CALLCHAIN = 1U << 5,
128 PERF_SAMPLE_ID = 1U << 6,
129 PERF_SAMPLE_CPU = 1U << 7,
130 PERF_SAMPLE_PERIOD = 1U << 8,
131 PERF_SAMPLE_STREAM_ID = 1U << 9,
132 PERF_SAMPLE_RAW = 1U << 10,
133 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
134 PERF_SAMPLE_REGS_USER = 1U << 12,
135 PERF_SAMPLE_STACK_USER = 1U << 13,
136 PERF_SAMPLE_WEIGHT = 1U << 14,
137 PERF_SAMPLE_DATA_SRC = 1U << 15,
138 PERF_SAMPLE_IDENTIFIER = 1U << 16,
139
140 PERF_SAMPLE_MAX = 1U << 17, /* non-ABI */
141};
142
143/*
144 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
145 *
146 * If the user does not pass priv level information via branch_sample_type,
147 * the kernel uses the event's priv level. Branch and event priv levels do
148 * not have to match. Branch priv level is checked for permissions.
149 *
150 * The branch types can be combined, however BRANCH_ANY covers all types
151 * of branches and therefore it supersedes all the other types.
152 */
153enum perf_branch_sample_type {
154 PERF_SAMPLE_BRANCH_USER = 1U << 0, /* user branches */
155 PERF_SAMPLE_BRANCH_KERNEL = 1U << 1, /* kernel branches */
156 PERF_SAMPLE_BRANCH_HV = 1U << 2, /* hypervisor branches */
157
158 PERF_SAMPLE_BRANCH_ANY = 1U << 3, /* any branch types */
159 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << 4, /* any call branch */
160 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << 5, /* any return branch */
161 PERF_SAMPLE_BRANCH_IND_CALL = 1U << 6, /* indirect calls */
162 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */
163 PERF_SAMPLE_BRANCH_IN_TX = 1U << 8, /* in transaction */
164 PERF_SAMPLE_BRANCH_NO_TX = 1U << 9, /* not in transaction */
165
166 PERF_SAMPLE_BRANCH_MAX = 1U << 10, /* non-ABI */
167};
168
169#define PERF_SAMPLE_BRANCH_PLM_ALL \
170 (PERF_SAMPLE_BRANCH_USER|\
171 PERF_SAMPLE_BRANCH_KERNEL|\
172 PERF_SAMPLE_BRANCH_HV)
173
174/*
175 * Values to determine ABI of the registers dump.
176 */
177enum perf_sample_regs_abi {
178 PERF_SAMPLE_REGS_ABI_NONE = 0,
179 PERF_SAMPLE_REGS_ABI_32 = 1,
180 PERF_SAMPLE_REGS_ABI_64 = 2,
181};
182
183/*
184 * The format of the data returned by read() on a perf event fd,
185 * as specified by attr.read_format:
186 *
187 * struct read_format {
188 * { u64 value;
189 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
190 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
191 * { u64 id; } && PERF_FORMAT_ID
192 * } && !PERF_FORMAT_GROUP
193 *
194 * { u64 nr;
195 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
196 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
197 * { u64 value;
198 * { u64 id; } && PERF_FORMAT_ID
199 * } cntr[nr];
200 * } && PERF_FORMAT_GROUP
201 * };
202 */
203enum perf_event_read_format {
204 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
205 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
206 PERF_FORMAT_ID = 1U << 2,
207 PERF_FORMAT_GROUP = 1U << 3,
208
209 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
210};
211
212#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
213#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
214#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
215#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
216 /* add: sample_stack_user */
217
218/*
219 * Hardware event_id to monitor via a performance monitoring event:
220 */
221struct perf_event_attr {
222
223 /*
224 * Major type: hardware/software/tracepoint/etc.
225 */
226 __u32 type;
227
228 /*
229 * Size of the attr structure, for fwd/bwd compat.
230 */
231 __u32 size;
232
233 /*
234 * Type specific configuration information.
235 */
236 __u64 config;
237
238 union {
239 __u64 sample_period;
240 __u64 sample_freq;
241 };
242
243 __u64 sample_type;
244 __u64 read_format;
245
246 __u64 disabled : 1, /* off by default */
247 inherit : 1, /* children inherit it */
248 pinned : 1, /* must always be on PMU */
249 exclusive : 1, /* only group on PMU */
250 exclude_user : 1, /* don't count user */
251 exclude_kernel : 1, /* ditto kernel */
252 exclude_hv : 1, /* ditto hypervisor */
253 exclude_idle : 1, /* don't count when idle */
254 mmap : 1, /* include mmap data */
255 comm : 1, /* include comm data */
256 freq : 1, /* use freq, not period */
257 inherit_stat : 1, /* per task counts */
258 enable_on_exec : 1, /* next exec enables */
259 task : 1, /* trace fork/exit */
260 watermark : 1, /* wakeup_watermark */
261 /*
262 * precise_ip:
263 *
264 * 0 - SAMPLE_IP can have arbitrary skid
265 * 1 - SAMPLE_IP must have constant skid
266 * 2 - SAMPLE_IP requested to have 0 skid
267 * 3 - SAMPLE_IP must have 0 skid
268 *
269 * See also PERF_RECORD_MISC_EXACT_IP
270 */
271 precise_ip : 2, /* skid constraint */
272 mmap_data : 1, /* non-exec mmap data */
273 sample_id_all : 1, /* sample_type all events */
274
275 exclude_host : 1, /* don't count in host */
276 exclude_guest : 1, /* don't count in guest */
277
278 exclude_callchain_kernel : 1, /* exclude kernel callchains */
279 exclude_callchain_user : 1, /* exclude user callchains */
280 mmap2 : 1, /* include mmap with inode data */
281
282 __reserved_1 : 40;
283
284 union {
285 __u32 wakeup_events; /* wakeup every n events */
286 __u32 wakeup_watermark; /* bytes before wakeup */
287 };
288
289 __u32 bp_type;
290 union {
291 __u64 bp_addr;
292 __u64 config1; /* extension of config */
293 };
294 union {
295 __u64 bp_len;
296 __u64 config2; /* extension of config1 */
297 };
298 __u64 branch_sample_type; /* enum perf_branch_sample_type */
299
300 /*
301 * Defines set of user regs to dump on samples.
302 * See asm/perf_regs.h for details.
303 */
304 __u64 sample_regs_user;
305
306 /*
307 * Defines size of the user stack to dump on samples.
308 */
309 __u32 sample_stack_user;
310
311 /* Align to u64. */
312 __u32 __reserved_2;
313};
314
315#define perf_flags(attr) (*(&(attr)->read_format + 1))
316
317/*
318 * Ioctls that can be done on a perf event fd:
319 */
320#define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
321#define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
322#define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
323#define PERF_EVENT_IOC_RESET _IO ('$', 3)
324#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
325#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
326#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
327#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
328
329enum perf_event_ioc_flags {
330 PERF_IOC_FLAG_GROUP = 1U << 0,
331};
332
333/*
334 * Structure of the page that can be mapped via mmap
335 */
336struct perf_event_mmap_page {
337 __u32 version; /* version number of this structure */
338 __u32 compat_version; /* lowest version this is compat with */
339
340 /*
341 * Bits needed to read the hw events in user-space.
342 *
343 * u32 seq, time_mult, time_shift, idx, width;
344 * u64 count, enabled, running;
345 * u64 cyc, time_offset;
346 * s64 pmc = 0;
347 *
348 * do {
349 * seq = pc->lock;
350 * barrier()
351 *
352 * enabled = pc->time_enabled;
353 * running = pc->time_running;
354 *
355 * if (pc->cap_usr_time && enabled != running) {
356 * cyc = rdtsc();
357 * time_offset = pc->time_offset;
358 * time_mult = pc->time_mult;
359 * time_shift = pc->time_shift;
360 * }
361 *
362 * idx = pc->index;
363 * count = pc->offset;
364 * if (pc->cap_usr_rdpmc && idx) {
365 * width = pc->pmc_width;
366 * pmc = rdpmc(idx - 1);
367 * }
368 *
369 * barrier();
370 * } while (pc->lock != seq);
371 *
372 * NOTE: for obvious reason this only works on self-monitoring
373 * processes.
374 */
375 __u32 lock; /* seqlock for synchronization */
376 __u32 index; /* hardware event identifier */
377 __s64 offset; /* add to hardware event value */
378 __u64 time_enabled; /* time event active */
379 __u64 time_running; /* time event on cpu */
380 union {
381 __u64 capabilities;
382 struct {
383 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
384 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
385
386 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
387 cap_user_time : 1, /* The time_* fields are used */
388 cap_user_time_zero : 1, /* The time_zero field is used */
389 cap_____res : 59;
390 };
391 };
392
393 /*
394 * If cap_usr_rdpmc this field provides the bit-width of the value
395 * read using the rdpmc() or equivalent instruction. This can be used
396 * to sign extend the result like:
397 *
398 * pmc <<= 64 - width;
399 * pmc >>= 64 - width; // signed shift right
400 * count += pmc;
401 */
402 __u16 pmc_width;
403
404 /*
405 * If cap_usr_time the below fields can be used to compute the time
406 * delta since time_enabled (in ns) using rdtsc or similar.
407 *
408 * u64 quot, rem;
409 * u64 delta;
410 *
411 * quot = (cyc >> time_shift);
412 * rem = cyc & ((1 << time_shift) - 1);
413 * delta = time_offset + quot * time_mult +
414 * ((rem * time_mult) >> time_shift);
415 *
416 * Where time_offset,time_mult,time_shift and cyc are read in the
417 * seqcount loop described above. This delta can then be added to
418 * enabled and possible running (if idx), improving the scaling:
419 *
420 * enabled += delta;
421 * if (idx)
422 * running += delta;
423 *
424 * quot = count / running;
425 * rem = count % running;
426 * count = quot * enabled + (rem * enabled) / running;
427 */
428 __u16 time_shift;
429 __u32 time_mult;
430 __u64 time_offset;
431 /*
432 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
433 * from sample timestamps.
434 *
435 * time = timestamp - time_zero;
436 * quot = time / time_mult;
437 * rem = time % time_mult;
438 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
439 *
440 * And vice versa:
441 *
442 * quot = cyc >> time_shift;
443 * rem = cyc & ((1 << time_shift) - 1);
444 * timestamp = time_zero + quot * time_mult +
445 * ((rem * time_mult) >> time_shift);
446 */
447 __u64 time_zero;
448 __u32 size; /* Header size up to __reserved[] fields. */
449
450 /*
451 * Hole for extension of the self monitor capabilities
452 */
453
454 __u8 __reserved[118*8+4]; /* align to 1k. */
455
456 /*
457 * Control data for the mmap() data buffer.
458 *
459 * User-space reading the @data_head value should issue an smp_rmb(),
460 * after reading this value.
461 *
462 * When the mapping is PROT_WRITE the @data_tail value should be
463 * written by userspace to reflect the last read data, after issueing
464 * an smp_mb() to separate the data read from the ->data_tail store.
465 * In this case the kernel will not over-write unread data.
466 *
467 * See perf_output_put_handle() for the data ordering.
468 */
469 __u64 data_head; /* head in the data section */
470 __u64 data_tail; /* user-space written tail */
471};
472
473#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
474#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
475#define PERF_RECORD_MISC_KERNEL (1 << 0)
476#define PERF_RECORD_MISC_USER (2 << 0)
477#define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
478#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
479#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
480
481#define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
482/*
483 * Indicates that the content of PERF_SAMPLE_IP points to
484 * the actual instruction that triggered the event. See also
485 * perf_event_attr::precise_ip.
486 */
487#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
488/*
489 * Reserve the last bit to indicate some extended misc field
490 */
491#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
492
493struct perf_event_header {
494 __u32 type;
495 __u16 misc;
496 __u16 size;
497};
498
499enum perf_event_type {
500
501 /*
502 * If perf_event_attr.sample_id_all is set then all event types will
503 * have the sample_type selected fields related to where/when
504 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
505 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
506 * just after the perf_event_header and the fields already present for
507 * the existing fields, i.e. at the end of the payload. That way a newer
508 * perf.data file will be supported by older perf tools, with these new
509 * optional fields being ignored.
510 *
511 * struct sample_id {
512 * { u32 pid, tid; } && PERF_SAMPLE_TID
513 * { u64 time; } && PERF_SAMPLE_TIME
514 * { u64 id; } && PERF_SAMPLE_ID
515 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
516 * { u32 cpu, res; } && PERF_SAMPLE_CPU
517 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
518 * } && perf_event_attr::sample_id_all
519 *
520 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
521 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
522 * relative to header.size.
523 */
524
525 /*
526 * The MMAP events record the PROT_EXEC mappings so that we can
527 * correlate userspace IPs to code. They have the following structure:
528 *
529 * struct {
530 * struct perf_event_header header;
531 *
532 * u32 pid, tid;
533 * u64 addr;
534 * u64 len;
535 * u64 pgoff;
536 * char filename[];
537 * struct sample_id sample_id;
538 * };
539 */
540 PERF_RECORD_MMAP = 1,
541
542 /*
543 * struct {
544 * struct perf_event_header header;
545 * u64 id;
546 * u64 lost;
547 * struct sample_id sample_id;
548 * };
549 */
550 PERF_RECORD_LOST = 2,
551
552 /*
553 * struct {
554 * struct perf_event_header header;
555 *
556 * u32 pid, tid;
557 * char comm[];
558 * struct sample_id sample_id;
559 * };
560 */
561 PERF_RECORD_COMM = 3,
562
563 /*
564 * struct {
565 * struct perf_event_header header;
566 * u32 pid, ppid;
567 * u32 tid, ptid;
568 * u64 time;
569 * struct sample_id sample_id;
570 * };
571 */
572 PERF_RECORD_EXIT = 4,
573
574 /*
575 * struct {
576 * struct perf_event_header header;
577 * u64 time;
578 * u64 id;
579 * u64 stream_id;
580 * struct sample_id sample_id;
581 * };
582 */
583 PERF_RECORD_THROTTLE = 5,
584 PERF_RECORD_UNTHROTTLE = 6,
585
586 /*
587 * struct {
588 * struct perf_event_header header;
589 * u32 pid, ppid;
590 * u32 tid, ptid;
591 * u64 time;
592 * struct sample_id sample_id;
593 * };
594 */
595 PERF_RECORD_FORK = 7,
596
597 /*
598 * struct {
599 * struct perf_event_header header;
600 * u32 pid, tid;
601 *
602 * struct read_format values;
603 * struct sample_id sample_id;
604 * };
605 */
606 PERF_RECORD_READ = 8,
607
608 /*
609 * struct {
610 * struct perf_event_header header;
611 *
612 * #
613 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
614 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
615 * # is fixed relative to header.
616 * #
617 *
618 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
619 * { u64 ip; } && PERF_SAMPLE_IP
620 * { u32 pid, tid; } && PERF_SAMPLE_TID
621 * { u64 time; } && PERF_SAMPLE_TIME
622 * { u64 addr; } && PERF_SAMPLE_ADDR
623 * { u64 id; } && PERF_SAMPLE_ID
624 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
625 * { u32 cpu, res; } && PERF_SAMPLE_CPU
626 * { u64 period; } && PERF_SAMPLE_PERIOD
627 *
628 * { struct read_format values; } && PERF_SAMPLE_READ
629 *
630 * { u64 nr,
631 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
632 *
633 * #
634 * # The RAW record below is opaque data wrt the ABI
635 * #
636 * # That is, the ABI doesn't make any promises wrt to
637 * # the stability of its content, it may vary depending
638 * # on event, hardware, kernel version and phase of
639 * # the moon.
640 * #
641 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
642 * #
643 *
644 * { u32 size;
645 * char data[size];}&& PERF_SAMPLE_RAW
646 *
647 * { u64 nr;
648 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
649 *
650 * { u64 abi; # enum perf_sample_regs_abi
651 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
652 *
653 * { u64 size;
654 * char data[size];
655 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
656 *
657 * { u64 weight; } && PERF_SAMPLE_WEIGHT
658 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
659 * };
660 */
661 PERF_RECORD_SAMPLE = 9,
662
663 /*
664 * The MMAP2 records are an augmented version of MMAP, they add
665 * maj, min, ino numbers to be used to uniquely identify each mapping
666 *
667 * struct {
668 * struct perf_event_header header;
669 *
670 * u32 pid, tid;
671 * u64 addr;
672 * u64 len;
673 * u64 pgoff;
674 * u32 maj;
675 * u32 min;
676 * u64 ino;
677 * u64 ino_generation;
678 * char filename[];
679 * struct sample_id sample_id;
680 * };
681 */
682 PERF_RECORD_MMAP2 = 10,
683
684 PERF_RECORD_MAX, /* non-ABI */
685};
686
687#define PERF_MAX_STACK_DEPTH 127
688
689enum perf_callchain_context {
690 PERF_CONTEXT_HV = (__u64)-32,
691 PERF_CONTEXT_KERNEL = (__u64)-128,
692 PERF_CONTEXT_USER = (__u64)-512,
693
694 PERF_CONTEXT_GUEST = (__u64)-2048,
695 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
696 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
697
698 PERF_CONTEXT_MAX = (__u64)-4095,
699};
700
701#define PERF_FLAG_FD_NO_GROUP (1U << 0)
702#define PERF_FLAG_FD_OUTPUT (1U << 1)
703#define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */
704
705union perf_mem_data_src {
706 __u64 val;
707 struct {
708 __u64 mem_op:5, /* type of opcode */
709 mem_lvl:14, /* memory hierarchy level */
710 mem_snoop:5, /* snoop mode */
711 mem_lock:2, /* lock instr */
712 mem_dtlb:7, /* tlb access */
713 mem_rsvd:31;
714 };
715};
716
717/* type of opcode (load/store/prefetch,code) */
718#define PERF_MEM_OP_NA 0x01 /* not available */
719#define PERF_MEM_OP_LOAD 0x02 /* load instruction */
720#define PERF_MEM_OP_STORE 0x04 /* store instruction */
721#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
722#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
723#define PERF_MEM_OP_SHIFT 0
724
725/* memory hierarchy (memory level, hit or miss) */
726#define PERF_MEM_LVL_NA 0x01 /* not available */
727#define PERF_MEM_LVL_HIT 0x02 /* hit level */
728#define PERF_MEM_LVL_MISS 0x04 /* miss level */
729#define PERF_MEM_LVL_L1 0x08 /* L1 */
730#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
731#define PERF_MEM_LVL_L2 0x20 /* L2 */
732#define PERF_MEM_LVL_L3 0x40 /* L3 */
733#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
734#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
735#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
736#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
737#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
738#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
739#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
740#define PERF_MEM_LVL_SHIFT 5
741
742/* snoop mode */
743#define PERF_MEM_SNOOP_NA 0x01 /* not available */
744#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
745#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
746#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
747#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
748#define PERF_MEM_SNOOP_SHIFT 19
749
750/* locked instruction */
751#define PERF_MEM_LOCK_NA 0x01 /* not available */
752#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
753#define PERF_MEM_LOCK_SHIFT 24
754
755/* TLB access */
756#define PERF_MEM_TLB_NA 0x01 /* not available */
757#define PERF_MEM_TLB_HIT 0x02 /* hit level */
758#define PERF_MEM_TLB_MISS 0x04 /* miss level */
759#define PERF_MEM_TLB_L1 0x08 /* L1 */
760#define PERF_MEM_TLB_L2 0x10 /* L2 */
761#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
762#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
763#define PERF_MEM_TLB_SHIFT 26
764
765#define PERF_MEM_S(a, s) \
766 (((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
767
768/*
769 * single taken branch record layout:
770 *
771 * from: source instruction (may not always be a branch insn)
772 * to: branch target
773 * mispred: branch target was mispredicted
774 * predicted: branch target was predicted
775 *
776 * support for mispred, predicted is optional. In case it
777 * is not supported mispred = predicted = 0.
778 *
779 * in_tx: running in a hardware transaction
780 * abort: aborting a hardware transaction
781 */
782struct perf_branch_entry {
783 __u64 from;
784 __u64 to;
785 __u64 mispred:1, /* target mispredicted */
786 predicted:1,/* target predicted */
787 in_tx:1, /* in transaction */
788 abort:1, /* transaction abort */
789 reserved:60;
790};
791
792#endif /* _LINUX_PERF_EVENT_H */
diff --git a/daemon/main.cpp b/daemon/main.cpp
index 2998c70..1275aef 100644
--- a/daemon/main.cpp
+++ b/daemon/main.cpp
@@ -20,10 +20,8 @@
20#include <unistd.h> 20#include <unistd.h>
21 21
22#include "Child.h" 22#include "Child.h"
23#include "EventsXML.h"
24#include "KMod.h" 23#include "KMod.h"
25#include "Logging.h" 24#include "Logging.h"
26#include "Monitor.h"
27#include "OlySocket.h" 25#include "OlySocket.h"
28#include "OlyUtility.h" 26#include "OlyUtility.h"
29#include "SessionData.h" 27#include "SessionData.h"
@@ -33,9 +31,8 @@
33extern Child* child; 31extern Child* child;
34static int shutdownFilesystem(); 32static int shutdownFilesystem();
35static pthread_mutex_t numSessions_mutex; 33static pthread_mutex_t numSessions_mutex;
36static OlyServerSocket* sock = NULL;
37static Monitor monitor;
38static int numSessions = 0; 34static int numSessions = 0;
35static OlyServerSocket* sock = NULL;
39static bool driverRunningAtStart = false; 36static bool driverRunningAtStart = false;
40static bool driverMountedAtStart = false; 37static bool driverMountedAtStart = false;
41 38
@@ -105,8 +102,42 @@ static void child_exit(int) {
105 } 102 }
106} 103}
107 104
108static const int UDP_ANS_PORT = 30000; 105static int udpPort(int port) {
109static const int UDP_REQ_PORT = 30001; 106 int s;
107 struct sockaddr_in6 sockaddr;
108 int on;
109 int family = AF_INET6;
110
111 s = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP);
112 if (s == -1) {
113 family = AF_INET;
114 s = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
115 if (s == -1) {
116 logg->logError(__FILE__, __LINE__, "socket failed");
117 handleException();
118 }
119 }
120
121 on = 1;
122 if (setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (const char*)&on, sizeof(on)) != 0) {
123 logg->logError(__FILE__, __LINE__, "setsockopt failed");
124 handleException();
125 }
126
127 memset((void*)&sockaddr, 0, sizeof(sockaddr));
128 sockaddr.sin6_family = family;
129 sockaddr.sin6_port = htons(port);
130 sockaddr.sin6_addr = in6addr_any;
131 if (bind(s, (struct sockaddr *)&sockaddr, sizeof(sockaddr)) < 0) {
132 logg->logError(__FILE__, __LINE__, "socket failed");
133 handleException();
134 }
135
136 return s;
137}
138
139#define UDP_ANS_PORT 30000
140#define UDP_REQ_PORT 30001
110 141
111typedef struct { 142typedef struct {
112 char rviHeader[8]; 143 char rviHeader[8];
@@ -118,102 +149,50 @@ typedef struct {
118 uint32_t ipAddress; 149 uint32_t ipAddress;
119 uint32_t defaultGateway; 150 uint32_t defaultGateway;
120 uint32_t subnetMask; 151 uint32_t subnetMask;
121 uint32_t activeConnections; 152 uint32_t activeConnections;
122} RVIConfigureInfo; 153} RVIConfigureInfo;
123 154
124static const char DST_REQ[] = { 'D', 'S', 'T', '_', 'R', 'E', 'Q', ' ', 0, 0, 0, 0x64 }; 155static const char DST_REQ[] = { 'D', 'S', 'T', '_', 'R', 'E', 'Q', ' ', 0, 0, 0, 0x64 };
125 156
126class UdpListener { 157static void* answerThread(void* pVoid) {
127public: 158 prctl(PR_SET_NAME, (unsigned long)&"gatord-discover", 0, 0, 0);
128 UdpListener() : mDstAns(), mReq(-1), mAns(-1) {} 159 const struct cmdline_t * const cmdline = (struct cmdline_t *)pVoid;
129 160 RVIConfigureInfo dstAns;
130 void setup(int port) { 161 int req = udpPort(UDP_REQ_PORT);
131 mReq = udpPort(UDP_REQ_PORT); 162 int ans = udpPort(UDP_ANS_PORT);
132 mAns = udpPort(UDP_ANS_PORT); 163
133 164 // Format the answer buffer
134 // Format the answer buffer 165 memset(&dstAns, 0, sizeof(dstAns));
135 memset(&mDstAns, 0, sizeof(mDstAns)); 166 memcpy(dstAns.rviHeader, "STR_ANS ", sizeof(dstAns.rviHeader));
136 memcpy(mDstAns.rviHeader, "STR_ANS ", sizeof(mDstAns.rviHeader)); 167 if (gethostname(dstAns.dhcpName, sizeof(dstAns.dhcpName) - 1) != 0) {
137 if (gethostname(mDstAns.dhcpName, sizeof(mDstAns.dhcpName) - 1) != 0) { 168 logg->logError(__FILE__, __LINE__, "gethostname failed");
138 logg->logError(__FILE__, __LINE__, "gethostname failed"); 169 handleException();
139 handleException();
140 }
141 // Subvert the defaultGateway field for the port number
142 if (port != DEFAULT_PORT) {
143 mDstAns.defaultGateway = port;
144 }
145 // Subvert the subnetMask field for the protocol version
146 mDstAns.subnetMask = PROTOCOL_VERSION;
147 } 170 }
148 171 // Subvert the defaultGateway field for the port number
149 int getReq() const { 172 if (cmdline->port != DEFAULT_PORT) {
150 return mReq; 173 dstAns.defaultGateway = cmdline->port;
151 } 174 }
175 // Subvert the subnetMask field for the protocol version
176 dstAns.subnetMask = PROTOCOL_VERSION;
152 177
153 void handle() { 178 for (;;) {
154 char buf[128]; 179 char buf[128];
155 struct sockaddr_in6 sockaddr; 180 struct sockaddr_in6 sockaddr;
156 socklen_t addrlen; 181 socklen_t addrlen;
157 int read; 182 int read;
158 addrlen = sizeof(sockaddr); 183 addrlen = sizeof(sockaddr);
159 read = recvfrom(mReq, &buf, sizeof(buf), 0, (struct sockaddr *)&sockaddr, &addrlen); 184 read = recvfrom(req, &buf, sizeof(buf), 0, (struct sockaddr *)&sockaddr, &addrlen);
160 if (read < 0) { 185 if (read < 0) {
161 logg->logError(__FILE__, __LINE__, "recvfrom failed"); 186 logg->logError(__FILE__, __LINE__, "recvfrom failed");
162 handleException(); 187 handleException();
163 } else if ((read == 12) && (memcmp(buf, DST_REQ, sizeof(DST_REQ)) == 0)) { 188 } else if ((read == 12) && (memcmp(buf, DST_REQ, sizeof(DST_REQ)) == 0)) {
164 if (sendto(mAns, &mDstAns, sizeof(mDstAns), 0, (struct sockaddr *)&sockaddr, addrlen) != sizeof(mDstAns)) { 189 if (sendto(ans, &dstAns, sizeof(dstAns), 0, (struct sockaddr *)&sockaddr, addrlen) != sizeof(dstAns)) {
165 logg->logError(__FILE__, __LINE__, "sendto failed"); 190 logg->logError(__FILE__, __LINE__, "sendto failed");
166 handleException(); 191 handleException();
167 } 192 }
168 } 193 }
169 } 194 }
170 195}
171 void close() {
172 ::close(mReq);
173 ::close(mAns);
174 }
175
176private:
177 int udpPort(int port) {
178 int s;
179 struct sockaddr_in6 sockaddr;
180 int on;
181 int family = AF_INET6;
182
183 s = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP);
184 if (s == -1) {
185 family = AF_INET;
186 s = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
187 if (s == -1) {
188 logg->logError(__FILE__, __LINE__, "socket failed");
189 handleException();
190 }
191 }
192
193 on = 1;
194 if (setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (const char*)&on, sizeof(on)) != 0) {
195 logg->logError(__FILE__, __LINE__, "setsockopt failed");
196 handleException();
197 }
198
199 memset((void*)&sockaddr, 0, sizeof(sockaddr));
200 sockaddr.sin6_family = family;
201 sockaddr.sin6_port = htons(port);
202 sockaddr.sin6_addr = in6addr_any;
203 if (bind(s, (struct sockaddr *)&sockaddr, sizeof(sockaddr)) < 0) {
204 logg->logError(__FILE__, __LINE__, "socket failed");
205 handleException();
206 }
207
208 return s;
209 }
210
211 RVIConfigureInfo mDstAns;
212 int mReq;
213 int mAns;
214};
215
216static UdpListener udpListener;
217 196
218// retval: -1 = failure; 0 = was already mounted; 1 = successfully mounted 197// retval: -1 = failure; 0 = was already mounted; 1 = successfully mounted
219static int mountGatorFS() { 198static int mountGatorFS() {
@@ -239,7 +218,7 @@ static bool init_module (const char * const location) {
239 if (fstat(fd, &st) == 0) { 218 if (fstat(fd, &st) == 0) {
240 void * const p = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0); 219 void * const p = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
241 if (p != MAP_FAILED) { 220 if (p != MAP_FAILED) {
242 if (syscall(__NR_init_module, p, (unsigned long)st.st_size, "") == 0) { 221 if (syscall(__NR_init_module, p, st.st_size, "") == 0) {
243 ret = true; 222 ret = true;
244 } 223 }
245 munmap(p, st.st_size); 224 munmap(p, st.st_size);
@@ -285,14 +264,8 @@ static bool setupFilesystem(char* module) {
285 } 264 }
286 265
287 if (access(location, F_OK) == -1) { 266 if (access(location, F_OK) == -1) {
288 if (module == NULL) { 267 // The gator kernel is not already loaded and unable to locate gator.ko
289 // The gator kernel is not already loaded and unable to locate gator.ko in the default location 268 return false;
290 return false;
291 } else {
292 // gator location specified on the command line but it was not found
293 logg->logError(__FILE__, __LINE__, "gator module not found at %s", location);
294 handleException();
295 }
296 } 269 }
297 270
298 // Load driver 271 // Load driver
@@ -407,45 +380,6 @@ static struct cmdline_t parseCommandLine(int argc, char** argv) {
407 return cmdline; 380 return cmdline;
408} 381}
409 382
410void handleClient() {
411 OlySocket client(sock->acceptConnection());
412
413 int pid = fork();
414 if (pid < 0) {
415 // Error
416 logg->logError(__FILE__, __LINE__, "Fork process failed. Please power cycle the target device if this error persists.");
417 } else if (pid == 0) {
418 // Child
419 sock->closeServerSocket();
420 udpListener.close();
421 monitor.close();
422 child = new Child(&client, numSessions + 1);
423 child->run();
424 delete child;
425 exit(0);
426 } else {
427 // Parent
428 client.closeSocket();
429
430 pthread_mutex_lock(&numSessions_mutex);
431 numSessions++;
432 pthread_mutex_unlock(&numSessions_mutex);
433
434 // Maximum number of connections is 2
435 int wait = 0;
436 while (numSessions > 1) {
437 // Throttle until one of the children exits before continuing to accept another socket connection
438 logg->logMessage("%d sessions active!", numSessions);
439 if (wait++ >= 10) { // Wait no more than 10 seconds
440 // Kill last created child
441 kill(pid, SIGALRM);
442 break;
443 }
444 sleep(1);
445 }
446 }
447}
448
449// Gator data flow: collector -> collector fifo -> sender 383// Gator data flow: collector -> collector fifo -> sender
450int main(int argc, char** argv) { 384int main(int argc, char** argv) {
451 // Ensure proper signal handling by making gatord the process group leader 385 // Ensure proper signal handling by making gatord the process group leader
@@ -486,23 +420,16 @@ int main(int argc, char** argv) {
486 logg->logMessage("Unable to setup gatorfs, trying perf"); 420 logg->logMessage("Unable to setup gatorfs, trying perf");
487 if (!gSessionData->perf.setup()) { 421 if (!gSessionData->perf.setup()) {
488 logg->logError(__FILE__, __LINE__, 422 logg->logError(__FILE__, __LINE__,
489 "Unable to locate gator.ko driver:\n" 423 "Unable to locate gator.ko driver:\n"
490 " >>> gator.ko should be co-located with gatord in the same directory\n" 424 " >>> gator.ko should be co-located with gatord in the same directory\n"
491 " >>> OR insmod gator.ko prior to launching gatord\n" 425 " >>> OR insmod gator.ko prior to launching gatord\n"
492 " >>> OR specify the location of gator.ko on the command line\n" 426 " >>> OR specify the location of gator.ko on the command line\n"
493 " >>> OR run Linux 3.4 or later with perf (CONFIG_PERF_EVENTS and CONFIG_HW_PERF_EVENTS) and tracing (CONFIG_TRACING) support to collect data via userspace only"); 427 " >>> OR run Linux 3.12 or later with perf support to collect data via userspace only");
494 handleException(); 428 handleException();
495 } 429 }
496 } 430 }
497 431
498 gSessionData->hwmon.setup(); 432 gSessionData->hwmon.setup();
499 {
500 EventsXML eventsXML;
501 mxml_node_t *xml = eventsXML.getTree();
502 gSessionData->fsDriver.setup(xml);
503 gSessionData->maliVideo.setup(xml);
504 mxmlDelete(xml);
505 }
506 433
507 // Handle child exit codes 434 // Handle child exit codes
508 signal(SIGCHLD, child_exit); 435 signal(SIGCHLD, child_exit);
@@ -517,26 +444,47 @@ int main(int argc, char** argv) {
517 child->run(); 444 child->run();
518 delete child; 445 delete child;
519 } else { 446 } else {
520 sock = new OlyServerSocket(cmdline.port); 447 pthread_t answerThreadID;
521 udpListener.setup(cmdline.port); 448 if (pthread_create(&answerThreadID, NULL, answerThread, &cmdline)) {
522 if (!monitor.init() || !monitor.add(sock->getFd()) || !monitor.add(udpListener.getReq())) { 449 logg->logError(__FILE__, __LINE__, "Failed to create answer thread");
523 logg->logError(__FILE__, __LINE__, "Monitor setup failed");
524 handleException(); 450 handleException();
525 } 451 }
452 sock = new OlyServerSocket(cmdline.port);
526 // Forever loop, can be exited via a signal or exception 453 // Forever loop, can be exited via a signal or exception
527 while (1) { 454 while (1) {
528 struct epoll_event events[2];
529 logg->logMessage("Waiting on connection..."); 455 logg->logMessage("Waiting on connection...");
530 int ready = monitor.wait(events, ARRAY_LENGTH(events), -1); 456 OlySocket client(sock->acceptConnection());
531 if (ready < 0) { 457
532 logg->logError(__FILE__, __LINE__, "Monitor::wait failed"); 458 int pid = fork();
533 handleException(); 459 if (pid < 0) {
534 } 460 // Error
535 for (int i = 0; i < ready; ++i) { 461 logg->logError(__FILE__, __LINE__, "Fork process failed. Please power cycle the target device if this error persists.");
536 if (events[i].data.fd == sock->getFd()) { 462 } else if (pid == 0) {
537 handleClient(); 463 // Child
538 } else if (events[i].data.fd == udpListener.getReq()) { 464 sock->closeServerSocket();
539 udpListener.handle(); 465 child = new Child(&client, numSessions + 1);
466 child->run();
467 delete child;
468 exit(0);
469 } else {
470 // Parent
471 client.closeSocket();
472
473 pthread_mutex_lock(&numSessions_mutex);
474 numSessions++;
475 pthread_mutex_unlock(&numSessions_mutex);
476
477 // Maximum number of connections is 2
478 int wait = 0;
479 while (numSessions > 1) {
480 // Throttle until one of the children exits before continuing to accept another socket connection
481 logg->logMessage("%d sessions active!", numSessions);
482 if (wait++ >= 10) { // Wait no more than 10 seconds
483 // Kill last created child
484 kill(pid, SIGALRM);
485 break;
486 }
487 sleep(1);
540 } 488 }
541 } 489 }
542 } 490 }
diff --git a/driver/Makefile b/driver/Makefile
index 2f86823..3dc9d05 100644
--- a/driver/Makefile
+++ b/driver/Makefile
@@ -7,14 +7,13 @@ CONFIG_GATOR ?= m
7obj-$(CONFIG_GATOR) := gator.o 7obj-$(CONFIG_GATOR) := gator.o
8 8
9gator-y := gator_main.o \ 9gator-y := gator_main.o \
10 gator_events_block.o \
11 gator_events_irq.o \ 10 gator_events_irq.o \
12 gator_events_meminfo.o \ 11 gator_events_sched.o \
13 gator_events_mmapped.o \
14 gator_events_net.o \ 12 gator_events_net.o \
13 gator_events_block.o \
14 gator_events_meminfo.o \
15 gator_events_perf_pmu.o \ 15 gator_events_perf_pmu.o \
16 gator_events_sched.o \ 16 gator_events_mmapped.o \
17 gator_events_threads.o \
18 17
19# Convert the old GATOR_WITH_MALI_SUPPORT to the new kernel flags 18# Convert the old GATOR_WITH_MALI_SUPPORT to the new kernel flags
20ifneq ($(GATOR_WITH_MALI_SUPPORT),) 19ifneq ($(GATOR_WITH_MALI_SUPPORT),)
@@ -49,14 +48,10 @@ ifeq ($(CONFIG_GATOR_WITH_MALI_SUPPORT),y)
49 ccflags-$(CONFIG_GATOR_MALI_T6XX) += -DMALI_SUPPORT=MALI_T6xx 48 ccflags-$(CONFIG_GATOR_MALI_T6XX) += -DMALI_SUPPORT=MALI_T6xx
50endif 49endif
51 50
52# GATOR_TEST controls whether to include (=1) or exclude (=0) test code. 51# GATOR_TEST controls whether to include (=1) or exclude (=0) test code.
53GATOR_TEST ?= 0 52GATOR_TEST ?= 0
54EXTRA_CFLAGS += -DGATOR_TEST=$(GATOR_TEST) 53EXTRA_CFLAGS += -DGATOR_TEST=$(GATOR_TEST)
55 54
56# Should the original or new block_rq_complete API be used?
57OLD_BLOCK_RQ_COMPLETE := $(shell grep -A3 block_rq_complete include/trace/events/block.h | grep nr_bytes > /dev/null; echo $$?)
58EXTRA_CFLAGS += -DOLD_BLOCK_RQ_COMPLETE=$(OLD_BLOCK_RQ_COMPLETE)
59
60gator-$(CONFIG_ARM) += gator_events_armv6.o \ 55gator-$(CONFIG_ARM) += gator_events_armv6.o \
61 gator_events_armv7.o \ 56 gator_events_armv7.o \
62 gator_events_ccn-504.o \ 57 gator_events_ccn-504.o \
diff --git a/driver/gator.h b/driver/gator.h
index 5ad0254..58cb0a2 100644
--- a/driver/gator.h
+++ b/driver/gator.h
@@ -42,10 +42,6 @@
42#define AARCH64 0xd0f 42#define AARCH64 0xd0f
43#define OTHER 0xfff 43#define OTHER 0xfff
44 44
45// gpu enums
46#define MALI_4xx 1
47#define MALI_T6xx 2
48
49#define MAXSIZE_CORE_NAME 32 45#define MAXSIZE_CORE_NAME 32
50 46
51struct gator_cpu { 47struct gator_cpu {
@@ -127,8 +123,6 @@ u32 gator_cpuid(void);
127 123
128void gator_backtrace_handler(struct pt_regs *const regs); 124void gator_backtrace_handler(struct pt_regs *const regs);
129 125
130void gator_marshal_activity_switch(int core, int key, int activity, int pid);
131
132#if !GATOR_IKS_SUPPORT 126#if !GATOR_IKS_SUPPORT
133 127
134#define get_physical_cpu() smp_processor_id() 128#define get_physical_cpu() smp_processor_id()
diff --git a/driver/gator_backtrace.c b/driver/gator_backtrace.c
index e03c165..9f305cf 100644
--- a/driver/gator_backtrace.c
+++ b/driver/gator_backtrace.c
@@ -178,7 +178,7 @@ static void kernel_backtrace(int cpu, struct pt_regs *const regs)
178 marshal_backtrace(PC_REG & ~1, NO_COOKIE, 1); 178 marshal_backtrace(PC_REG & ~1, NO_COOKIE, 1);
179#endif 179#endif
180} 180}
181 181
182static void gator_add_sample(int cpu, struct pt_regs *const regs, u64 time) 182static void gator_add_sample(int cpu, struct pt_regs *const regs, u64 time)
183{ 183{
184 bool in_kernel; 184 bool in_kernel;
diff --git a/driver/gator_buffer.c b/driver/gator_buffer.c
index dfbc97d..eba22df 100644
--- a/driver/gator_buffer.c
+++ b/driver/gator_buffer.c
@@ -37,12 +37,12 @@ static void marshal_frame(int cpu, int buftype)
37 case SCHED_TRACE_BUF: 37 case SCHED_TRACE_BUF:
38 frame = FRAME_SCHED_TRACE; 38 frame = FRAME_SCHED_TRACE;
39 break; 39 break;
40 case GPU_TRACE_BUF:
41 frame = FRAME_GPU_TRACE;
42 break;
40 case IDLE_BUF: 43 case IDLE_BUF:
41 frame = FRAME_IDLE; 44 frame = FRAME_IDLE;
42 break; 45 break;
43 case ACTIVITY_BUF:
44 frame = FRAME_ACTIVITY;
45 break;
46 default: 46 default:
47 frame = -1; 47 frame = -1;
48 break; 48 break;
diff --git a/driver/gator_events_armv7.c b/driver/gator_events_armv7.c
index bd8a9ba..153119b 100644
--- a/driver/gator_events_armv7.c
+++ b/driver/gator_events_armv7.c
@@ -27,9 +27,9 @@
27// ccnt reg 27// ccnt reg
28#define CCNT_REG (1 << 31) 28#define CCNT_REG (1 << 31)
29 29
30#define CCNT 0 30#define CCNT 0
31#define CNT0 1 31#define CNT0 1
32#define CNTMAX (6+1) 32#define CNTMAX (6+1)
33 33
34static const char *pmnc_name; 34static const char *pmnc_name;
35static int pmnc_counters; 35static int pmnc_counters;
diff --git a/driver/gator_events_block.c b/driver/gator_events_block.c
index 03eed4f..b2bc414 100644
--- a/driver/gator_events_block.c
+++ b/driver/gator_events_block.c
@@ -28,25 +28,15 @@ static ulong block_rq_rd_key;
28static atomic_t blockCnt[BLOCK_TOTAL]; 28static atomic_t blockCnt[BLOCK_TOTAL];
29static int blockGet[BLOCK_TOTAL * 4]; 29static int blockGet[BLOCK_TOTAL * 4];
30 30
31// Tracepoint changed in 3.15 backported to older kernels. The Makefile tries to autodetect the correct value, but if it fails change the #if below
32#if OLD_BLOCK_RQ_COMPLETE
33GATOR_DEFINE_PROBE(block_rq_complete, TP_PROTO(struct request_queue *q, struct request *rq)) 31GATOR_DEFINE_PROBE(block_rq_complete, TP_PROTO(struct request_queue *q, struct request *rq))
34#else
35GATOR_DEFINE_PROBE(block_rq_complete, TP_PROTO(struct request_queue *q, struct request *rq, unsigned int nr_bytes))
36#endif
37{ 32{
38 int write; 33 int write, size;
39 unsigned int size;
40 34
41 if (!rq) 35 if (!rq)
42 return; 36 return;
43 37
44 write = rq->cmd_flags & EVENTWRITE; 38 write = rq->cmd_flags & EVENTWRITE;
45#if OLD_BLOCK_RQ_COMPLETE
46 size = rq->resid_len; 39 size = rq->resid_len;
47#else
48 size = nr_bytes;
49#endif
50 40
51 if (!size) 41 if (!size)
52 return; 42 return;
diff --git a/driver/gator_events_mali_4xx.c b/driver/gator_events_mali_4xx.c
index 9e1c706..85d4764 100644
--- a/driver/gator_events_mali_4xx.c
+++ b/driver/gator_events_mali_4xx.c
@@ -18,27 +18,17 @@
18#include "gator_events_mali_4xx.h" 18#include "gator_events_mali_4xx.h"
19 19
20/* 20/*
21* There have been four different variants of the comms between gator and Mali depending on driver version: 21 * There are (currently) four different variants of the comms between gator and Mali:
22* # | DDK vsn range | Support | Notes 22 * 1 (deprecated): No software counter support
23* 23 * 2 (deprecated): Tracepoint called for each separate s/w counter value as it appears
24* 1 | (obsolete) | No software counter support | Obsolete patches 24 * 3 (default): Single tracepoint for all s/w counters in a bundle.
25* 2 | (obsolete) | Tracepoint called for each separate s/w counter value as it appears | Obsolete patches 25 * Interface style 3 is the default if no other is specified. 1 and 2 will be eliminated when
26* 3 | r3p0-04rel0 - r3p2-01rel2 | Single tracepoint for all s/w counters in a bundle. | 26 * existing Mali DDKs are upgraded.
27* 4 | r3p2-01rel3 - date | As above but with extensions for MP devices (Mali-450) | At least r4p0-00rel1 27 * 4. As above, but for the Utgard (Mali-450) driver.
28*/ 28 */
29 29
30#if !defined(GATOR_MALI_INTERFACE_STYLE) 30#if !defined(GATOR_MALI_INTERFACE_STYLE)
31#define GATOR_MALI_INTERFACE_STYLE (4) 31#define GATOR_MALI_INTERFACE_STYLE (3)
32#endif
33
34#if GATOR_MALI_INTERFACE_STYLE == 1
35#error GATOR_MALI_INTERFACE_STYLE 1 is obsolete
36#elif GATOR_MALI_INTERFACE_STYLE == 2
37#error GATOR_MALI_INTERFACE_STYLE 2 is obsolete
38#elif GATOR_MALI_INTERFACE_STYLE >= 3
39// Valid GATOR_MALI_INTERFACE_STYLE
40#else
41#error Unknown GATOR_MALI_INTERFACE_STYLE option.
42#endif 32#endif
43 33
44#if GATOR_MALI_INTERFACE_STYLE < 4 34#if GATOR_MALI_INTERFACE_STYLE < 4
@@ -54,8 +44,6 @@
54#error MALI_SUPPORT set to an invalid device code: expecting MALI_4xx 44#error MALI_SUPPORT set to an invalid device code: expecting MALI_4xx
55#endif 45#endif
56 46
57static const char mali_name[] = "Mali-4xx";
58
59/* gatorfs variables for counter enable state, 47/* gatorfs variables for counter enable state,
60 * the event the counter should count and the 48 * the event the counter should count and the
61 * 'key' (a unique id set by gatord and returned 49 * 'key' (a unique id set by gatord and returned
@@ -75,7 +63,6 @@ static u32 *counter_address[NUMBER_OF_EVENTS];
75 */ 63 */
76static unsigned long counter_dump[NUMBER_OF_EVENTS * 2]; 64static unsigned long counter_dump[NUMBER_OF_EVENTS * 2];
77static unsigned long counter_prev[NUMBER_OF_EVENTS]; 65static unsigned long counter_prev[NUMBER_OF_EVENTS];
78static bool prev_set[NUMBER_OF_EVENTS];
79 66
80/* Note whether tracepoints have been registered */ 67/* Note whether tracepoints have been registered */
81static int trace_registered; 68static int trace_registered;
@@ -89,11 +76,18 @@ static unsigned int n_vp_cores = MAX_NUM_VP_CORES;
89static unsigned int n_l2_cores = MAX_NUM_L2_CACHE_CORES; 76static unsigned int n_l2_cores = MAX_NUM_L2_CACHE_CORES;
90static unsigned int n_fp_cores = MAX_NUM_FP_CORES; 77static unsigned int n_fp_cores = MAX_NUM_FP_CORES;
91 78
92extern mali_counter mali_activity[2]; 79/**
93static const char* const mali_activity_names[] = { 80 * Calculate the difference and handle the overflow.
94 "fragment", 81 */
95 "vertex", 82static u32 get_difference(u32 start, u32 end)
96}; 83{
84 if (start - end >= 0) {
85 return start - end;
86 }
87
88 // Mali counters are unsigned 32 bit values that wrap.
89 return (4294967295u - end) + start;
90}
97 91
98/** 92/**
99 * Returns non-zero if the given counter ID is an activity counter. 93 * Returns non-zero if the given counter ID is an activity counter.
@@ -118,6 +112,40 @@ static inline int is_hw_counter(unsigned int event_id)
118typedef void _mali_profiling_get_mali_version_type(struct _mali_profiling_mali_version *values); 112typedef void _mali_profiling_get_mali_version_type(struct _mali_profiling_mali_version *values);
119typedef u32 _mali_profiling_get_l2_counters_type(_mali_profiling_l2_counter_values *values); 113typedef u32 _mali_profiling_get_l2_counters_type(_mali_profiling_l2_counter_values *values);
120 114
115#if GATOR_MALI_INTERFACE_STYLE == 2
116/**
117 * Returns non-zero if the given counter ID is a software counter.
118 */
119static inline int is_sw_counter(unsigned int event_id)
120{
121 return (event_id >= FIRST_SW_COUNTER && event_id <= LAST_SW_COUNTER);
122}
123#endif
124
125#if GATOR_MALI_INTERFACE_STYLE == 2
126/*
127 * The Mali DDK uses s64 types to contain software counter values, but gator
128 * can only use a maximum of 32 bits. This function scales a software counter
129 * to an appropriate range.
130 */
131static u32 scale_sw_counter_value(unsigned int event_id, signed long long value)
132{
133 u32 scaled_value;
134
135 switch (event_id) {
136 case COUNTER_GLES_UPLOAD_TEXTURE_TIME:
137 case COUNTER_GLES_UPLOAD_VBO_TIME:
138 scaled_value = (u32)div_s64(value, 1000000);
139 break;
140 default:
141 scaled_value = (u32)value;
142 break;
143 }
144
145 return scaled_value;
146}
147#endif
148
121/* Probe for continuously sampled counter */ 149/* Probe for continuously sampled counter */
122#if 0 //WE_DONT_CURRENTLY_USE_THIS_SO_SUPPRESS_WARNING 150#if 0 //WE_DONT_CURRENTLY_USE_THIS_SO_SUPPRESS_WARNING
123GATOR_DEFINE_PROBE(mali_sample_address, TP_PROTO(unsigned int event_id, u32 *addr)) 151GATOR_DEFINE_PROBE(mali_sample_address, TP_PROTO(unsigned int event_id, u32 *addr))
@@ -144,6 +172,16 @@ GATOR_DEFINE_PROBE(mali_hw_counter, TP_PROTO(unsigned int event_id, unsigned int
144 } 172 }
145} 173}
146 174
175#if GATOR_MALI_INTERFACE_STYLE == 2
176GATOR_DEFINE_PROBE(mali_sw_counter, TP_PROTO(unsigned int event_id, signed long long value))
177{
178 if (is_sw_counter(event_id)) {
179 counter_data[event_id] = scale_sw_counter_value(event_id, value);
180 }
181}
182#endif /* GATOR_MALI_INTERFACE_STYLE == 2 */
183
184#if GATOR_MALI_INTERFACE_STYLE >= 3
147GATOR_DEFINE_PROBE(mali_sw_counters, TP_PROTO(pid_t pid, pid_t tid, void *surface_id, unsigned int *counters)) 185GATOR_DEFINE_PROBE(mali_sw_counters, TP_PROTO(pid_t pid, pid_t tid, void *surface_id, unsigned int *counters))
148{ 186{
149 u32 i; 187 u32 i;
@@ -155,6 +193,7 @@ GATOR_DEFINE_PROBE(mali_sw_counters, TP_PROTO(pid_t pid, pid_t tid, void *surfac
155 } 193 }
156 } 194 }
157} 195}
196#endif /* GATOR_MALI_INTERFACE_STYLE >= 3 */
158 197
159/** 198/**
160 * Create a single filesystem entry for a specified event. 199 * Create a single filesystem entry for a specified event.
@@ -215,7 +254,6 @@ static void initialise_version_info(void)
215 symbol_put(_mali_profiling_get_mali_version); 254 symbol_put(_mali_profiling_get_mali_version);
216 } else { 255 } else {
217 printk("gator: mali online _mali_profiling_get_mali_version symbol not found\n"); 256 printk("gator: mali online _mali_profiling_get_mali_version symbol not found\n");
218 printk("gator: check your Mali DDK version versus the GATOR_MALI_INTERFACE_STYLE setting\n");
219 } 257 }
220} 258}
221#endif 259#endif
@@ -223,6 +261,7 @@ static void initialise_version_info(void)
223static int create_files(struct super_block *sb, struct dentry *root) 261static int create_files(struct super_block *sb, struct dentry *root)
224{ 262{
225 int event; 263 int event;
264 const char *mali_name = gator_mali_get_mali_name();
226 265
227 char buf[40]; 266 char buf[40];
228 int core_id; 267 int core_id;
@@ -239,14 +278,6 @@ static int create_files(struct super_block *sb, struct dentry *root)
239 initialise_version_info(); 278 initialise_version_info();
240#endif 279#endif
241 280
242 mali_activity[0].cores = n_fp_cores;
243 mali_activity[1].cores = n_vp_cores;
244 for (event = 0; event < ARRAY_SIZE(mali_activity); event++) {
245 if (gator_mali_create_file_system(mali_name, mali_activity_names[event], sb, root, &mali_activity[event], NULL) != 0) {
246 return -1;
247 }
248 }
249
250 /* Vertex processor counters */ 281 /* Vertex processor counters */
251 for (core_id = 0; core_id < n_vp_cores; core_id++) { 282 for (core_id = 0; core_id < n_vp_cores; core_id++) {
252 int activity_counter_id = ACTIVITY_VP_0; 283 int activity_counter_id = ACTIVITY_VP_0;
@@ -382,6 +413,7 @@ static void init_counters(unsigned int from_counter, unsigned int to_counter)
382static void mali_counter_initialize(void) 413static void mali_counter_initialize(void)
383{ 414{
384 int i; 415 int i;
416 int core_id;
385 417
386 mali_profiling_control_type *mali_control; 418 mali_profiling_control_type *mali_control;
387 419
@@ -431,10 +463,15 @@ static void mali_counter_initialize(void)
431 n_l2_cores = 0; 463 n_l2_cores = 0;
432 } 464 }
433 465
466 for (core_id = 0; core_id < n_l2_cores; core_id++) {
467 int counter_id = COUNTER_L2_0_C0 + (2 * core_id);
468 counter_prev[counter_id] = 0;
469 counter_prev[counter_id + 1] = 0;
470 }
471
434 /* Clear counters in the start */ 472 /* Clear counters in the start */
435 for (i = 0; i < NUMBER_OF_EVENTS; i++) { 473 for (i = 0; i < NUMBER_OF_EVENTS; i++) {
436 counter_data[i] = 0; 474 counter_data[i] = 0;
437 prev_set[i] = false;
438 } 475 }
439} 476}
440 477
@@ -491,11 +528,23 @@ static int start(void)
491 return -1; 528 return -1;
492 } 529 }
493 530
531#if GATOR_MALI_INTERFACE_STYLE == 1
532 /* None. */
533#elif GATOR_MALI_INTERFACE_STYLE == 2
534 /* For patched Mali driver. */
535 if (GATOR_REGISTER_TRACE(mali_sw_counter)) {
536 printk("gator: mali_sw_counter tracepoint failed to activate\n");
537 return -1;
538 }
539#elif GATOR_MALI_INTERFACE_STYLE >= 3
494 /* For Mali drivers with built-in support. */ 540 /* For Mali drivers with built-in support. */
495 if (GATOR_REGISTER_TRACE(mali_sw_counters)) { 541 if (GATOR_REGISTER_TRACE(mali_sw_counters)) {
496 printk("gator: mali_sw_counters tracepoint failed to activate\n"); 542 printk("gator: mali_sw_counters tracepoint failed to activate\n");
497 return -1; 543 return -1;
498 } 544 }
545#else
546#error Unknown GATOR_MALI_INTERFACE_STYLE option.
547#endif
499 548
500 trace_registered = 1; 549 trace_registered = 1;
501 550
@@ -512,8 +561,17 @@ static void stop(void)
512 if (trace_registered) { 561 if (trace_registered) {
513 GATOR_UNREGISTER_TRACE(mali_hw_counter); 562 GATOR_UNREGISTER_TRACE(mali_hw_counter);
514 563
564#if GATOR_MALI_INTERFACE_STYLE == 1
565 /* None. */
566#elif GATOR_MALI_INTERFACE_STYLE == 2
567 /* For patched Mali driver. */
568 GATOR_UNREGISTER_TRACE(mali_sw_counter);
569#elif GATOR_MALI_INTERFACE_STYLE >= 3
515 /* For Mali drivers with built-in support. */ 570 /* For Mali drivers with built-in support. */
516 GATOR_UNREGISTER_TRACE(mali_sw_counters); 571 GATOR_UNREGISTER_TRACE(mali_sw_counters);
572#else
573#error Unknown GATOR_MALI_INTERFACE_STYLE option.
574#endif
517 575
518 pr_debug("gator: mali timeline tracepoint deactivated\n"); 576 pr_debug("gator: mali timeline tracepoint deactivated\n");
519 577
@@ -578,23 +636,21 @@ static int read(int **buffer)
578 636
579 per_core = &cache_values.cores[cache_id]; 637 per_core = &cache_values.cores[cache_id];
580 638
581 if (counter_enabled[counter_id_0] && prev_set[counter_id_0]) { 639 if (counter_enabled[counter_id_0]) {
582 // Calculate and save src0's counter val0 640 // Calculate and save src0's counter val0
583 counter_dump[len++] = counter_key[counter_id_0]; 641 counter_dump[len++] = counter_key[counter_id_0];
584 counter_dump[len++] = per_core->value0 - counter_prev[counter_id_0]; 642 counter_dump[len++] = get_difference(per_core->value0, counter_prev[counter_id_0]);
585 } 643 }
586 644
587 if (counter_enabled[counter_id_1] && prev_set[counter_id_1]) { 645 if (counter_enabled[counter_id_1]) {
588 // Calculate and save src1's counter val1 646 // Calculate and save src1's counter val1
589 counter_dump[len++] = counter_key[counter_id_1]; 647 counter_dump[len++] = counter_key[counter_id_1];
590 counter_dump[len++] = per_core->value1 - counter_prev[counter_id_1]; 648 counter_dump[len++] = get_difference(per_core->value1, counter_prev[counter_id_1]);
591 } 649 }
592 650
593 // Save the previous values for the counters. 651 // Save the previous values for the counters.
594 counter_prev[counter_id_0] = per_core->value0; 652 counter_prev[counter_id_0] = per_core->value0;
595 prev_set[counter_id_0] = true;
596 counter_prev[counter_id_1] = per_core->value1; 653 counter_prev[counter_id_1] = per_core->value1;
597 prev_set[counter_id_1] = true;
598 } 654 }
599 } 655 }
600 656
@@ -653,8 +709,6 @@ int gator_events_mali_init(void)
653 709
654 pr_debug("gator: mali init\n"); 710 pr_debug("gator: mali init\n");
655 711
656 gator_mali_initialise_counters(mali_activity, ARRAY_SIZE(mali_activity));
657
658 for (cnt = 0; cnt < NUMBER_OF_EVENTS; cnt++) { 712 for (cnt = 0; cnt < NUMBER_OF_EVENTS; cnt++) {
659 counter_enabled[cnt] = 0; 713 counter_enabled[cnt] = 0;
660 counter_event[cnt] = 0; 714 counter_event[cnt] = 0;
diff --git a/driver/gator_events_mali_common.c b/driver/gator_events_mali_common.c
index 4f2cce4..dc58dcf 100644
--- a/driver/gator_events_mali_common.c
+++ b/driver/gator_events_mali_common.c
@@ -8,6 +8,26 @@
8 */ 8 */
9#include "gator_events_mali_common.h" 9#include "gator_events_mali_common.h"
10 10
11static u32 gator_mali_get_id(void)
12{
13 return MALI_SUPPORT;
14}
15
16extern const char *gator_mali_get_mali_name(void)
17{
18 u32 id = gator_mali_get_id();
19
20 switch (id) {
21 case MALI_T6xx:
22 return "Mali-T6xx";
23 case MALI_4xx:
24 return "Mali-4xx";
25 default:
26 pr_debug("gator: Mali-T6xx: unknown Mali ID (%d)\n", id);
27 return "Mali-Unknown";
28 }
29}
30
11extern int gator_mali_create_file_system(const char *mali_name, const char *event_name, struct super_block *sb, struct dentry *root, mali_counter *counter, unsigned long *event) 31extern int gator_mali_create_file_system(const char *mali_name, const char *event_name, struct super_block *sb, struct dentry *root, mali_counter *counter, unsigned long *event)
12{ 32{
13 int err; 33 int err;
@@ -22,31 +42,24 @@ extern int gator_mali_create_file_system(const char *mali_name, const char *even
22 dir = gatorfs_mkdir(sb, root, buf); 42 dir = gatorfs_mkdir(sb, root, buf);
23 43
24 if (dir == NULL) { 44 if (dir == NULL) {
25 pr_debug("gator: %s: error creating file system for: %s (%s)", mali_name, event_name, buf); 45 pr_debug("gator: Mali-T6xx: error creating file system for: %s (%s)", event_name, buf);
26 return -1; 46 return -1;
27 } 47 }
28 48
29 err = gatorfs_create_ulong(sb, dir, "enabled", &counter->enabled); 49 err = gatorfs_create_ulong(sb, dir, "enabled", &counter->enabled);
30 if (err != 0) { 50 if (err != 0) {
31 pr_debug("gator: %s: error calling gatorfs_create_ulong for: %s (%s)", mali_name, event_name, buf); 51 pr_debug("gator: Mali-T6xx: error calling gatorfs_create_ulong for: %s (%s)", event_name, buf);
32 return -1; 52 return -1;
33 } 53 }
34 err = gatorfs_create_ro_ulong(sb, dir, "key", &counter->key); 54 err = gatorfs_create_ro_ulong(sb, dir, "key", &counter->key);
35 if (err != 0) { 55 if (err != 0) {
36 pr_debug("gator: %s: error calling gatorfs_create_ro_ulong for: %s (%s)", mali_name, event_name, buf); 56 pr_debug("gator: Mali-T6xx: error calling gatorfs_create_ro_ulong for: %s (%s)", event_name, buf);
37 return -1; 57 return -1;
38 } 58 }
39 if (counter->cores != -1) {
40 err = gatorfs_create_ro_ulong(sb, dir, "cores", &counter->cores);
41 if (err != 0) {
42 pr_debug("gator: %s: error calling gatorfs_create_ro_ulong for: %s (%s)", mali_name, event_name, buf);
43 return -1;
44 }
45 }
46 if (event != NULL) { 59 if (event != NULL) {
47 err = gatorfs_create_ulong(sb, dir, "event", event); 60 err = gatorfs_create_ulong(sb, dir, "event", event);
48 if (err != 0) { 61 if (err != 0) {
49 pr_debug("gator: %s: error calling gatorfs_create_ro_ulong for: %s (%s)", mali_name, event_name, buf); 62 pr_debug("gator: Mali-T6xx: error calling gatorfs_create_ro_ulong for: %s (%s)", event_name, buf);
50 return -1; 63 return -1;
51 } 64 }
52 } 65 }
@@ -64,6 +77,5 @@ extern void gator_mali_initialise_counters(mali_counter counters[], unsigned int
64 77
65 counter->key = gator_events_get_key(); 78 counter->key = gator_events_get_key();
66 counter->enabled = 0; 79 counter->enabled = 0;
67 counter->cores = -1;
68 } 80 }
69} 81}
diff --git a/driver/gator_events_mali_common.h b/driver/gator_events_mali_common.h
index 91d871b..41c2a3c 100644
--- a/driver/gator_events_mali_common.h
+++ b/driver/gator_events_mali_common.h
@@ -18,6 +18,10 @@
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <asm/io.h> 19#include <asm/io.h>
20 20
21/* Device codes for each known GPU */
22#define MALI_4xx (0x0b07)
23#define MALI_T6xx (0x0056)
24
21/* Ensure that MALI_SUPPORT has been defined to something. */ 25/* Ensure that MALI_SUPPORT has been defined to something. */
22#ifndef MALI_SUPPORT 26#ifndef MALI_SUPPORT
23#error MALI_SUPPORT not defined! 27#error MALI_SUPPORT not defined!
@@ -31,12 +35,8 @@
31 * Runtime state information for a counter. 35 * Runtime state information for a counter.
32 */ 36 */
33typedef struct { 37typedef struct {
34 // 'key' (a unique id set by gatord and returned by gator.ko) 38 unsigned long key; /* 'key' (a unique id set by gatord and returned by gator.ko) */
35 unsigned long key; 39 unsigned long enabled; /* counter enable state */
36 // counter enable state
37 unsigned long enabled;
38 // for activity counters, the number of cores, otherwise -1
39 unsigned long cores;
40} mali_counter; 40} mali_counter;
41 41
42/* 42/*
@@ -54,9 +54,17 @@ extern void _mali_profiling_control(unsigned int, unsigned int);
54extern void _mali_profiling_get_counters(unsigned int *, unsigned int *, unsigned int *, unsigned int *); 54extern void _mali_profiling_get_counters(unsigned int *, unsigned int *, unsigned int *, unsigned int *);
55 55
56/** 56/**
57 * Returns a name which identifies the GPU type (eg Mali-4xx, Mali-T6xx).
58 *
59 * @return The name as a constant string.
60 */
61extern const char *gator_mali_get_mali_name(void);
62
63/**
57 * Creates a filesystem entry under /dev/gator relating to the specified event name and key, and 64 * Creates a filesystem entry under /dev/gator relating to the specified event name and key, and
58 * associate the key/enable values with this entry point. 65 * associate the key/enable values with this entry point.
59 * 66 *
67 * @param mali_name A name related to the type of GPU, obtained from a call to gator_mali_get_mali_name()
60 * @param event_name The name of the event. 68 * @param event_name The name of the event.
61 * @param sb Linux super block 69 * @param sb Linux super block
62 * @param root Directory under which the entry will be created. 70 * @param root Directory under which the entry will be created.
diff --git a/driver/gator_events_mali_t6xx.c b/driver/gator_events_mali_t6xx.c
index e56ba84..76f14ee 100644
--- a/driver/gator_events_mali_t6xx.c
+++ b/driver/gator_events_mali_t6xx.c
@@ -32,8 +32,6 @@
32#error MALI_SUPPORT set to an invalid device code: expecting MALI_T6xx 32#error MALI_SUPPORT set to an invalid device code: expecting MALI_T6xx
33#endif 33#endif
34 34
35static const char mali_name[] = "Mali-T6xx";
36
37/* Counters for Mali-T6xx: 35/* Counters for Mali-T6xx:
38 * 36 *
39 * - Timeline events 37 * - Timeline events
@@ -294,6 +292,7 @@ static int create_files(struct super_block *sb, struct dentry *root)
294 * Create the filesystem for all events 292 * Create the filesystem for all events
295 */ 293 */
296 int counter_index = 0; 294 int counter_index = 0;
295 const char *mali_name = gator_mali_get_mali_name();
297 mali_profiling_control_type *mali_control; 296 mali_profiling_control_type *mali_control;
298 297
299 for (event = FIRST_TIMELINE_EVENT; event < FIRST_TIMELINE_EVENT + NUMBER_OF_TIMELINE_EVENTS; event++) { 298 for (event = FIRST_TIMELINE_EVENT; event < FIRST_TIMELINE_EVENT + NUMBER_OF_TIMELINE_EVENTS; event++) {
@@ -318,7 +317,7 @@ static int create_files(struct super_block *sb, struct dentry *root)
318 } 317 }
319 318
320 mali_control = symbol_get(_mali_profiling_control); 319 mali_control = symbol_get(_mali_profiling_control);
321 if (mali_control) { 320 if (mali_control) {
322 if (gator_mali_create_file_system(mali_name, "Filmstrip_cnt0", sb, root, &counters[FILMSTRIP], &filmstrip_event) != 0) { 321 if (gator_mali_create_file_system(mali_name, "Filmstrip_cnt0", sb, root, &counters[FILMSTRIP], &filmstrip_event) != 0) {
323 return -1; 322 return -1;
324 } 323 }
diff --git a/driver/gator_events_mali_t6xx_hw.c b/driver/gator_events_mali_t6xx_hw.c
index 3a072bb..dfbc91f 100644
--- a/driver/gator_events_mali_t6xx_hw.c
+++ b/driver/gator_events_mali_t6xx_hw.c
@@ -16,10 +16,7 @@
16#include <asm/io.h> 16#include <asm/io.h>
17 17
18/* Mali T6xx DDK includes */ 18/* Mali T6xx DDK includes */
19#if defined(MALI_SIMPLE_API) 19#ifdef MALI_DIR_MIDGARD
20/* Header with wrapper functions to kbase structures and functions */
21#include "mali/mali_dd_gator_api.h"
22#elif defined(MALI_DIR_MIDGARD)
23/* New DDK Directory structure with kernel/drivers/gpu/arm/midgard*/ 20/* New DDK Directory structure with kernel/drivers/gpu/arm/midgard*/
24#include "mali_linux_trace.h" 21#include "mali_linux_trace.h"
25#include "mali_kbase.h" 22#include "mali_kbase.h"
@@ -31,49 +28,37 @@
31#include "kbase/src/linux/mali_kbase_mem_linux.h" 28#include "kbase/src/linux/mali_kbase_mem_linux.h"
32#endif 29#endif
33 30
31#include "gator_events_mali_common.h"
32
34/* If API version is not specified then assume API version 1. */ 33/* If API version is not specified then assume API version 1. */
35#ifndef MALI_DDK_GATOR_API_VERSION 34#ifndef MALI_DDK_GATOR_API_VERSION
36#define MALI_DDK_GATOR_API_VERSION 1 35#define MALI_DDK_GATOR_API_VERSION 1
37#endif 36#endif
38 37
39#if (MALI_DDK_GATOR_API_VERSION != 1) && (MALI_DDK_GATOR_API_VERSION != 2) && (MALI_DDK_GATOR_API_VERSION != 3) 38#if (MALI_DDK_GATOR_API_VERSION != 1) && (MALI_DDK_GATOR_API_VERSION != 2)
40#error MALI_DDK_GATOR_API_VERSION is invalid (must be 1 for r1/r2 DDK, or 2 for r3 DDK, or 3 for r? DDK). 39#error MALI_DDK_GATOR_API_VERSION is invalid (must be 1 for r1/r2 DDK, or 2 for r3 DDK).
41#endif 40#endif
42 41
43#include "gator_events_mali_common.h"
44
45/* 42/*
46 * Mali-T6xx 43 * Mali-T6xx
47 */ 44 */
48#if MALI_DDK_GATOR_API_VERSION == 3
49typedef uint32_t kbase_dd_instr_hwcnt_dump_irq_type(struct mali_dd_hwcnt_handles *);
50typedef uint32_t kbase_dd_instr_hwcnt_dump_complete_type(struct mali_dd_hwcnt_handles *, uint32_t *);
51typedef struct mali_dd_hwcnt_handles* mali_dd_hwcnt_init_type(struct mali_dd_hwcnt_info *);
52typedef void mali_dd_hwcnt_clear_type(struct mali_dd_hwcnt_info *, struct mali_dd_hwcnt_handles *);
53
54static kbase_dd_instr_hwcnt_dump_irq_type *kbase_dd_instr_hwcnt_dump_irq_symbol;
55static kbase_dd_instr_hwcnt_dump_complete_type *kbase_dd_instr_hwcnt_dump_complete_symbol;
56static mali_dd_hwcnt_init_type *mali_dd_hwcnt_init_symbol;
57static mali_dd_hwcnt_clear_type *mali_dd_hwcnt_clear_symbol;
58
59#else
60typedef struct kbase_device *kbase_find_device_type(int); 45typedef struct kbase_device *kbase_find_device_type(int);
61typedef struct kbase_context *kbase_create_context_type(struct kbase_device *); 46typedef kbase_context *kbase_create_context_type(kbase_device *);
62typedef void kbase_destroy_context_type(struct kbase_context *); 47typedef void kbase_destroy_context_type(kbase_context *);
63 48
64#if MALI_DDK_GATOR_API_VERSION == 1 49#if MALI_DDK_GATOR_API_VERSION == 1
65typedef void *kbase_va_alloc_type(struct kbase_context *, u32); 50typedef void *kbase_va_alloc_type(kbase_context *, u32);
66typedef void kbase_va_free_type(struct kbase_context *, void *); 51typedef void kbase_va_free_type(kbase_context *, void *);
67#elif MALI_DDK_GATOR_API_VERSION == 2 52#elif MALI_DDK_GATOR_API_VERSION == 2
68typedef void *kbase_va_alloc_type(struct kbase_context *, u32, kbase_hwc_dma_mapping * handle); 53typedef void *kbase_va_alloc_type(kbase_context *, u32, kbase_hwc_dma_mapping * handle);
69typedef void kbase_va_free_type(struct kbase_context *, kbase_hwc_dma_mapping * handle); 54typedef void kbase_va_free_type(kbase_context *, kbase_hwc_dma_mapping * handle);
70#endif 55#endif
71 56
72typedef mali_error kbase_instr_hwcnt_enable_type(struct kbase_context *, struct kbase_uk_hwcnt_setup *); 57typedef mali_error kbase_instr_hwcnt_enable_type(kbase_context *, kbase_uk_hwcnt_setup *);
73typedef mali_error kbase_instr_hwcnt_disable_type(struct kbase_context *); 58typedef mali_error kbase_instr_hwcnt_disable_type(kbase_context *);
74typedef mali_error kbase_instr_hwcnt_clear_type(struct kbase_context *); 59typedef mali_error kbase_instr_hwcnt_clear_type(kbase_context *);
75typedef mali_error kbase_instr_hwcnt_dump_irq_type(struct kbase_context *); 60typedef mali_error kbase_instr_hwcnt_dump_irq_type(kbase_context *);
76typedef mali_bool kbase_instr_hwcnt_dump_complete_type(struct kbase_context *, mali_bool *); 61typedef mali_bool kbase_instr_hwcnt_dump_complete_type(kbase_context *, mali_bool *);
77 62
78static kbase_find_device_type *kbase_find_device_symbol; 63static kbase_find_device_type *kbase_find_device_symbol;
79static kbase_create_context_type *kbase_create_context_symbol; 64static kbase_create_context_type *kbase_create_context_symbol;
@@ -85,7 +70,6 @@ static kbase_instr_hwcnt_dump_complete_type *kbase_instr_hwcnt_dump_complete_sym
85static kbase_instr_hwcnt_disable_type *kbase_instr_hwcnt_disable_symbol; 70static kbase_instr_hwcnt_disable_type *kbase_instr_hwcnt_disable_symbol;
86static kbase_va_free_type *kbase_va_free_symbol; 71static kbase_va_free_type *kbase_va_free_symbol;
87static kbase_destroy_context_type *kbase_destroy_context_symbol; 72static kbase_destroy_context_type *kbase_destroy_context_symbol;
88#endif
89 73
90static long shader_present_low = 0; 74static long shader_present_low = 0;
91 75
@@ -115,8 +99,6 @@ enum {
115 MMU_BLOCK 99 MMU_BLOCK
116}; 100};
117 101
118static const char mali_name[] = "Mali-T6xx";
119
120/* Counters for Mali-T6xx: 102/* Counters for Mali-T6xx:
121 * 103 *
122 * - HW counters, 4 blocks 104 * - HW counters, 4 blocks
@@ -399,14 +381,6 @@ static const char *const hardware_counter_names[] = {
399#define GET_HW_BLOCK(c) (((c) >> 6) & 0x3) 381#define GET_HW_BLOCK(c) (((c) >> 6) & 0x3)
400#define GET_COUNTER_OFFSET(c) ((c) & 0x3f) 382#define GET_COUNTER_OFFSET(c) ((c) & 0x3f)
401 383
402#if MALI_DDK_GATOR_API_VERSION == 3
403/* Opaque handles for kbase_context and kbase_hwc_dma_mapping */
404static struct mali_dd_hwcnt_handles *handles;
405
406/* Information about hardware counters */
407static struct mali_dd_hwcnt_info *in_out_info;
408
409#else
410/* Memory to dump hardware counters into */ 384/* Memory to dump hardware counters into */
411static void *kernel_dump_buffer; 385static void *kernel_dump_buffer;
412 386
@@ -416,9 +390,14 @@ kbase_hwc_dma_mapping kernel_dump_buffer_handle;
416#endif 390#endif
417 391
418/* kbase context and device */ 392/* kbase context and device */
419static struct kbase_context *kbcontext = NULL; 393static kbase_context *kbcontext = NULL;
420static struct kbase_device *kbdevice = NULL; 394static struct kbase_device *kbdevice = NULL;
421#endif 395
396/*
397 * The following function has no external prototype in older DDK revisions. When the DDK
398 * is updated then this should be removed.
399 */
400struct kbase_device *kbase_find_device(int minor);
422 401
423static volatile bool kbase_device_busy = false; 402static volatile bool kbase_device_busy = false;
424static unsigned int num_hardware_counters_enabled; 403static unsigned int num_hardware_counters_enabled;
@@ -433,13 +412,6 @@ static mali_counter counters[NUMBER_OF_HARDWARE_COUNTERS];
433 */ 412 */
434static unsigned long counter_dump[NUMBER_OF_HARDWARE_COUNTERS * 2]; 413static unsigned long counter_dump[NUMBER_OF_HARDWARE_COUNTERS * 2];
435 414
436extern mali_counter mali_activity[3];
437static const char* const mali_activity_names[] = {
438 "fragment",
439 "vertex",
440 "opencl",
441};
442
443#define SYMBOL_GET(FUNCTION, ERROR_COUNT) \ 415#define SYMBOL_GET(FUNCTION, ERROR_COUNT) \
444 if(FUNCTION ## _symbol) \ 416 if(FUNCTION ## _symbol) \
445 { \ 417 { \
@@ -459,8 +431,8 @@ static const char* const mali_activity_names[] = {
459#define SYMBOL_CLEANUP(FUNCTION) \ 431#define SYMBOL_CLEANUP(FUNCTION) \
460 if(FUNCTION ## _symbol) \ 432 if(FUNCTION ## _symbol) \
461 { \ 433 { \
462 symbol_put(FUNCTION); \ 434 symbol_put(FUNCTION); \
463 FUNCTION ## _symbol = NULL; \ 435 FUNCTION ## _symbol = NULL; \
464 } 436 }
465 437
466/** 438/**
@@ -470,12 +442,6 @@ static const char* const mali_activity_names[] = {
470static int init_symbols(void) 442static int init_symbols(void)
471{ 443{
472 int error_count = 0; 444 int error_count = 0;
473#if MALI_DDK_GATOR_API_VERSION == 3
474 SYMBOL_GET(kbase_dd_instr_hwcnt_dump_irq, error_count);
475 SYMBOL_GET(kbase_dd_instr_hwcnt_dump_complete, error_count);
476 SYMBOL_GET(mali_dd_hwcnt_init, error_count);
477 SYMBOL_GET(mali_dd_hwcnt_clear, error_count);
478#else
479 SYMBOL_GET(kbase_find_device, error_count); 445 SYMBOL_GET(kbase_find_device, error_count);
480 SYMBOL_GET(kbase_create_context, error_count); 446 SYMBOL_GET(kbase_create_context, error_count);
481 SYMBOL_GET(kbase_va_alloc, error_count); 447 SYMBOL_GET(kbase_va_alloc, error_count);
@@ -486,7 +452,6 @@ static int init_symbols(void)
486 SYMBOL_GET(kbase_instr_hwcnt_disable, error_count); 452 SYMBOL_GET(kbase_instr_hwcnt_disable, error_count);
487 SYMBOL_GET(kbase_va_free, error_count); 453 SYMBOL_GET(kbase_va_free, error_count);
488 SYMBOL_GET(kbase_destroy_context, error_count); 454 SYMBOL_GET(kbase_destroy_context, error_count);
489#endif
490 455
491 return error_count; 456 return error_count;
492} 457}
@@ -496,12 +461,6 @@ static int init_symbols(void)
496 */ 461 */
497static void clean_symbols(void) 462static void clean_symbols(void)
498{ 463{
499#if MALI_DDK_GATOR_API_VERSION == 3
500 SYMBOL_CLEANUP(kbase_dd_instr_hwcnt_dump_irq);
501 SYMBOL_CLEANUP(kbase_dd_instr_hwcnt_dump_complete);
502 SYMBOL_CLEANUP(mali_dd_hwcnt_init);
503 SYMBOL_CLEANUP(mali_dd_hwcnt_clear);
504#else
505 SYMBOL_CLEANUP(kbase_find_device); 464 SYMBOL_CLEANUP(kbase_find_device);
506 SYMBOL_CLEANUP(kbase_create_context); 465 SYMBOL_CLEANUP(kbase_create_context);
507 SYMBOL_CLEANUP(kbase_va_alloc); 466 SYMBOL_CLEANUP(kbase_va_alloc);
@@ -512,7 +471,6 @@ static void clean_symbols(void)
512 SYMBOL_CLEANUP(kbase_instr_hwcnt_disable); 471 SYMBOL_CLEANUP(kbase_instr_hwcnt_disable);
513 SYMBOL_CLEANUP(kbase_va_free); 472 SYMBOL_CLEANUP(kbase_va_free);
514 SYMBOL_CLEANUP(kbase_destroy_context); 473 SYMBOL_CLEANUP(kbase_destroy_context);
515#endif
516} 474}
517 475
518/** 476/**
@@ -544,13 +502,11 @@ static int is_read_scheduled(const struct timespec *current_time, u32 *prev_time
544 502
545static int start(void) 503static int start(void)
546{ 504{
547#if MALI_DDK_GATOR_API_VERSION < 3 505 kbase_uk_hwcnt_setup setup;
548 struct kbase_uk_hwcnt_setup setup;
549 unsigned long long shadersPresent = 0;
550 u16 bitmask[] = { 0, 0, 0, 0 };
551 mali_error err; 506 mali_error err;
552#endif
553 int cnt; 507 int cnt;
508 u16 bitmask[] = { 0, 0, 0, 0 };
509 unsigned long long shadersPresent = 0;
554 510
555 /* Setup HW counters */ 511 /* Setup HW counters */
556 num_hardware_counters_enabled = 0; 512 num_hardware_counters_enabled = 0;
@@ -559,52 +515,18 @@ static int start(void)
559 pr_debug("Unexpected number of hardware counters defined: expecting 256, got %d\n", NUMBER_OF_HARDWARE_COUNTERS); 515 pr_debug("Unexpected number of hardware counters defined: expecting 256, got %d\n", NUMBER_OF_HARDWARE_COUNTERS);
560 } 516 }
561 517
562#if MALI_DDK_GATOR_API_VERSION == 3
563 /* Declare and initialise mali_dd_hwcnt_info structure */
564 in_out_info = kmalloc(sizeof(struct mali_dd_hwcnt_info), GFP_KERNEL);
565 for (cnt = 0; cnt < 4; cnt++){
566 in_out_info->bitmask[cnt] = 0;
567 }
568#endif
569 /* Calculate enable bitmasks based on counters_enabled array */ 518 /* Calculate enable bitmasks based on counters_enabled array */
570 for (cnt = 0; cnt < NUMBER_OF_HARDWARE_COUNTERS; cnt++) { 519 for (cnt = 0; cnt < NUMBER_OF_HARDWARE_COUNTERS; cnt++) {
571 const mali_counter *counter = &counters[cnt]; 520 const mali_counter *counter = &counters[cnt];
572 if (counter->enabled) { 521 if (counter->enabled) {
573 int block = GET_HW_BLOCK(cnt); 522 int block = GET_HW_BLOCK(cnt);
574 int enable_bit = GET_COUNTER_OFFSET(cnt) / 4; 523 int enable_bit = GET_COUNTER_OFFSET(cnt) / 4;
575#if MALI_DDK_GATOR_API_VERSION == 3
576 in_out_info->bitmask[block] |= (1 << enable_bit);
577#else
578 bitmask[block] |= (1 << enable_bit); 524 bitmask[block] |= (1 << enable_bit);
579#endif
580 pr_debug("gator: Mali-T6xx: hardware counter %s selected [%d]\n", hardware_counter_names[cnt], cnt); 525 pr_debug("gator: Mali-T6xx: hardware counter %s selected [%d]\n", hardware_counter_names[cnt], cnt);
581 num_hardware_counters_enabled++; 526 num_hardware_counters_enabled++;
582 } 527 }
583 } 528 }
584 529
585#if MALI_DDK_GATOR_API_VERSION == 3
586 /* Create a kbase context for HW counters */
587 if (num_hardware_counters_enabled > 0) {
588 if (init_symbols() > 0) {
589 clean_symbols();
590 /* No Mali driver code entrypoints found - not a fault. */
591 return 0;
592 }
593
594 handles = mali_dd_hwcnt_init_symbol(in_out_info);
595
596 if(handles == NULL) {
597 goto out;
598 }
599
600 /* See if we can get the number of shader cores */
601 shader_present_low = (unsigned long)in_out_info->shader_present_bitmap;
602
603 kbase_device_busy = false;
604 }
605
606 return 0;
607#else
608 /* Create a kbase context for HW counters */ 530 /* Create a kbase context for HW counters */
609 if (num_hardware_counters_enabled > 0) { 531 if (num_hardware_counters_enabled > 0) {
610 if (init_symbols() > 0) { 532 if (init_symbols() > 0) {
@@ -684,7 +606,6 @@ free_buffer:
684 606
685destroy_context: 607destroy_context:
686 kbase_destroy_context_symbol(kbcontext); 608 kbase_destroy_context_symbol(kbcontext);
687#endif
688 609
689out: 610out:
690 clean_symbols(); 611 clean_symbols();
@@ -694,11 +615,7 @@ out:
694static void stop(void) 615static void stop(void)
695{ 616{
696 unsigned int cnt; 617 unsigned int cnt;
697#if MALI_DDK_GATOR_API_VERSION == 3 618 kbase_context *temp_kbcontext;
698 struct mali_dd_hwcnt_handles *temp_hand;
699#else
700 struct kbase_context *temp_kbcontext;
701#endif
702 619
703 pr_debug("gator: Mali-T6xx: stop\n"); 620 pr_debug("gator: Mali-T6xx: stop\n");
704 621
@@ -708,20 +625,6 @@ static void stop(void)
708 } 625 }
709 626
710 /* Destroy the context for HW counters */ 627 /* Destroy the context for HW counters */
711#if MALI_DDK_GATOR_API_VERSION == 3
712 if (num_hardware_counters_enabled > 0 && handles != NULL) {
713 /*
714 * Set the global variable to NULL before destroying it, because
715 * other function will check this before using it.
716 */
717 temp_hand = handles;
718 handles = NULL;
719
720 mali_dd_hwcnt_clear_symbol(in_out_info, temp_hand);
721
722 kfree(in_out_info);
723
724#else
725 if (num_hardware_counters_enabled > 0 && kbcontext != NULL) { 628 if (num_hardware_counters_enabled > 0 && kbcontext != NULL) {
726 /* 629 /*
727 * Set the global variable to NULL before destroying it, because 630 * Set the global variable to NULL before destroying it, because
@@ -739,7 +642,6 @@ static void stop(void)
739#endif 642#endif
740 643
741 kbase_destroy_context_symbol(temp_kbcontext); 644 kbase_destroy_context_symbol(temp_kbcontext);
742#endif
743 645
744 pr_debug("gator: Mali-T6xx: hardware counters stopped\n"); 646 pr_debug("gator: Mali-T6xx: hardware counters stopped\n");
745 647
@@ -752,7 +654,7 @@ static int read(int **buffer)
752 int cnt; 654 int cnt;
753 int len = 0; 655 int len = 0;
754 u32 value = 0; 656 u32 value = 0;
755 uint32_t success; 657 mali_bool success;
756 658
757 struct timespec current_time; 659 struct timespec current_time;
758 static u32 prev_time_s = 0; 660 static u32 prev_time_s = 0;
@@ -784,21 +686,12 @@ static int read(int **buffer)
784 0x500 /* VITHAR_MEMORY_SYSTEM, Block 3 */ 686 0x500 /* VITHAR_MEMORY_SYSTEM, Block 3 */
785 }; 687 };
786 688
787#if MALI_DDK_GATOR_API_VERSION == 3
788 if (!handles) {
789 return -1;
790 }
791
792 /* Mali symbols can be called safely since a kbcontext is valid */
793 if (kbase_dd_instr_hwcnt_dump_complete_symbol(handles, &success) == MALI_TRUE) {
794#else
795 if (!kbcontext) { 689 if (!kbcontext) {
796 return -1; 690 return -1;
797 } 691 }
798 692
799 /* Mali symbols can be called safely since a kbcontext is valid */ 693 /* Mali symbols can be called safely since a kbcontext is valid */
800 if (kbase_instr_hwcnt_dump_complete_symbol(kbcontext, &success) == MALI_TRUE) { 694 if (kbase_instr_hwcnt_dump_complete_symbol(kbcontext, &success) == MALI_TRUE) {
801#endif
802 kbase_device_busy = false; 695 kbase_device_busy = false;
803 696
804 if (success == MALI_TRUE) { 697 if (success == MALI_TRUE) {
@@ -809,11 +702,7 @@ static int read(int **buffer)
809 const int block = GET_HW_BLOCK(cnt); 702 const int block = GET_HW_BLOCK(cnt);
810 const int counter_offset = GET_COUNTER_OFFSET(cnt); 703 const int counter_offset = GET_COUNTER_OFFSET(cnt);
811 704
812#if MALI_DDK_GATOR_API_VERSION == 3
813 const char* block_base_address = (char*)in_out_info->kernel_dump_buffer + vithar_blocks[block];
814#else
815 const char* block_base_address = (char*)kernel_dump_buffer + vithar_blocks[block]; 705 const char* block_base_address = (char*)kernel_dump_buffer + vithar_blocks[block];
816#endif
817 706
818 /* If counter belongs to shader block need to take into account all cores */ 707 /* If counter belongs to shader block need to take into account all cores */
819 if (block == SHADER_BLOCK) { 708 if (block == SHADER_BLOCK) {
@@ -852,11 +741,7 @@ static int read(int **buffer)
852 741
853 if (!kbase_device_busy) { 742 if (!kbase_device_busy) {
854 kbase_device_busy = true; 743 kbase_device_busy = true;
855#if MALI_DDK_GATOR_API_VERSION == 3
856 kbase_dd_instr_hwcnt_dump_irq_symbol(handles);
857#else
858 kbase_instr_hwcnt_dump_irq_symbol(kbcontext); 744 kbase_instr_hwcnt_dump_irq_symbol(kbcontext);
859#endif
860 } 745 }
861 } 746 }
862 747
@@ -875,12 +760,7 @@ static int create_files(struct super_block *sb, struct dentry *root)
875 * Create the filesystem for all events 760 * Create the filesystem for all events
876 */ 761 */
877 int counter_index = 0; 762 int counter_index = 0;
878 763 const char *mali_name = gator_mali_get_mali_name();
879 for (event = 0; event < ARRAY_SIZE(mali_activity); event++) {
880 if (gator_mali_create_file_system(mali_name, mali_activity_names[event], sb, root, &mali_activity[event], NULL) != 0) {
881 return -1;
882 }
883 }
884 764
885 for (event = 0; event < NUMBER_OF_HARDWARE_COUNTERS; event++) { 765 for (event = 0; event < NUMBER_OF_HARDWARE_COUNTERS; event++) {
886 if (gator_mali_create_file_system(mali_name, hardware_counter_names[counter_index], sb, root, &counters[event], NULL) != 0) 766 if (gator_mali_create_file_system(mali_name, hardware_counter_names[counter_index], sb, root, &counters[event], NULL) != 0)
@@ -906,7 +786,6 @@ int gator_events_mali_t6xx_hw_init(void)
906 test_all_is_read_scheduled(); 786 test_all_is_read_scheduled();
907#endif 787#endif
908 788
909 gator_mali_initialise_counters(mali_activity, ARRAY_SIZE(mali_activity));
910 gator_mali_initialise_counters(counters, NUMBER_OF_HARDWARE_COUNTERS); 789 gator_mali_initialise_counters(counters, NUMBER_OF_HARDWARE_COUNTERS);
911 790
912 return gator_events_install(&gator_events_mali_t6xx_interface); 791 return gator_events_install(&gator_events_mali_t6xx_interface);
diff --git a/driver/gator_events_mmapped.c b/driver/gator_events_mmapped.c
index 5bc01c4..3b248ec 100644
--- a/driver/gator_events_mmapped.c
+++ b/driver/gator_events_mmapped.c
@@ -8,25 +8,21 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 * Similar entries to those below must be present in the events.xml file. 10 * Similar entries to those below must be present in the events.xml file.
11 * To add them to the events.xml, create an events-mmap.xml with the 11 * To add them to the events.xml, create an events-mmap.xml with the
12 * following contents and rebuild gatord: 12 * following contents and rebuild gatord:
13 * 13 *
14 * <category name="mmapped"> 14 * <counter_set name="mmapped_cnt" count="3"/>
15 * <event counter="mmapped_cnt0" title="Simulated1" name="Sine" display="maximum" class="absolute" description="Sort-of-sine"/> 15 * <category name="mmapped" counter_set="mmapped_cnt" per_cpu="no">
16 * <event counter="mmapped_cnt1" title="Simulated2" name="Triangle" display="maximum" class="absolute" description="Triangular wave"/> 16 * <event event="0x0" title="Simulated1" name="Sine" display="maximum" average_selection="yes" description="Sort-of-sine"/>
17 * <event counter="mmapped_cnt2" title="Simulated3" name="PWM" display="maximum" class="absolute" description="PWM Signal"/> 17 * <event event="0x1" title="Simulated2" name="Triangle" display="maximum" average_selection="yes" description="Triangular wave"/>
18 * <event event="0x2" title="Simulated3" name="PWM" display="maximum" average_selection="yes" description="PWM Signal"/>
18 * </category> 19 * </category>
19 * 20 *
20 * When adding custom events, be sure to do the following: 21 * When adding custom events, be sure do the following
21 * - add any needed .c files to the gator driver Makefile 22 * - add any needed .c files to the gator driver Makefile
22 * - call gator_events_install in the events init function 23 * - call gator_events_install in the events init function
23 * - add the init function to GATOR_EVENTS_LIST in gator_main.c 24 * - add the init function to GATOR_EVENTS_LIST in gator_main.c
24 * - add a new events-*.xml file to the gator daemon and rebuild 25 * - add a new events-*.xml file to the gator daemon and rebuild
25 *
26 * Troubleshooting:
27 * - verify the new events are part of events.xml, which is created when building the daemon
28 * - verify the new events exist at /dev/gator/events/ once gatord is launched
29 * - verify the counter name in the XML matches the name at /dev/gator/events
30 */ 26 */
31 27
32#include <linux/init.h> 28#include <linux/init.h>
@@ -41,6 +37,7 @@ static int mmapped_global_enabled;
41 37
42static struct { 38static struct {
43 unsigned long enabled; 39 unsigned long enabled;
40 unsigned long event;
44 unsigned long key; 41 unsigned long key;
45} mmapped_counters[MMAPPED_COUNTERS_NUM]; 42} mmapped_counters[MMAPPED_COUNTERS_NUM];
46 43
@@ -50,7 +47,7 @@ static s64 prev_time;
50 47
51/* Adds mmapped_cntX directories and enabled, event, and key files to /dev/gator/events */ 48/* Adds mmapped_cntX directories and enabled, event, and key files to /dev/gator/events */
52static int gator_events_mmapped_create_files(struct super_block *sb, 49static int gator_events_mmapped_create_files(struct super_block *sb,
53 struct dentry *root) 50 struct dentry *root)
54{ 51{
55 int i; 52 int i;
56 53
@@ -64,6 +61,8 @@ static int gator_events_mmapped_create_files(struct super_block *sb,
64 return -1; 61 return -1;
65 gatorfs_create_ulong(sb, dir, "enabled", 62 gatorfs_create_ulong(sb, dir, "enabled",
66 &mmapped_counters[i].enabled); 63 &mmapped_counters[i].enabled);
64 gatorfs_create_ulong(sb, dir, "event",
65 &mmapped_counters[i].event);
67 gatorfs_create_ro_ulong(sb, dir, "key", 66 gatorfs_create_ro_ulong(sb, dir, "key",
68 &mmapped_counters[i].key); 67 &mmapped_counters[i].key);
69 } 68 }
@@ -178,7 +177,8 @@ static int gator_events_mmapped_read(int **buffer)
178 if (mmapped_counters[i].enabled) { 177 if (mmapped_counters[i].enabled) {
179 mmapped_buffer[len++] = mmapped_counters[i].key; 178 mmapped_buffer[len++] = mmapped_counters[i].key;
180 mmapped_buffer[len++] = 179 mmapped_buffer[len++] =
181 mmapped_simulate(i, delta_in_us); 180 mmapped_simulate(mmapped_counters[i].event,
181 delta_in_us);
182 } 182 }
183 } 183 }
184 184
diff --git a/driver/gator_events_perf_pmu.c b/driver/gator_events_perf_pmu.c
index 06bbad5..8b2d67a 100644
--- a/driver/gator_events_perf_pmu.c
+++ b/driver/gator_events_perf_pmu.c
@@ -470,10 +470,10 @@ static void gator_events_perf_pmu_cci_init(const int type)
470 470
471 switch (probe_cci_revision()) { 471 switch (probe_cci_revision()) {
472 case 0: 472 case 0:
473 cci_name = "CCI_400"; 473 cci_name = "cci-400";
474 break; 474 break;
475 case 1: 475 case 1:
476 cci_name = "CCI_400-r1"; 476 cci_name = "cci-400-r1";
477 break; 477 break;
478 default: 478 default:
479 pr_debug("gator: unrecognized cci-400 revision\n"); 479 pr_debug("gator: unrecognized cci-400 revision\n");
@@ -549,7 +549,7 @@ int gator_events_perf_pmu_init(void)
549 } 549 }
550 550
551 if (pe->pmu != NULL && type == pe->pmu->type) { 551 if (pe->pmu != NULL && type == pe->pmu->type) {
552 if (strcmp("CCI", pe->pmu->name) == 0 || strcmp("CCI_400", pe->pmu->name) == 0 || strcmp("CCI_400-r1", pe->pmu->name) == 0) { 552 if (strcmp("CCI", pe->pmu->name) == 0 || strcmp("CCI_400", pe->pmu->name) == 0) {
553 gator_events_perf_pmu_cci_init(type); 553 gator_events_perf_pmu_cci_init(type);
554 } else if ((gator_cpu = gator_find_cpu_by_pmu_name(pe->pmu->name)) != NULL) { 554 } else if ((gator_cpu = gator_find_cpu_by_pmu_name(pe->pmu->name)) != NULL) {
555 found_cpu = true; 555 found_cpu = true;
diff --git a/driver/gator_events_scorpion.c b/driver/gator_events_scorpion.c
index 2e5be8d..8ca251a 100644
--- a/driver/gator_events_scorpion.c
+++ b/driver/gator_events_scorpion.c
@@ -26,9 +26,9 @@ static int pmnc_counters;
26// ccnt reg 26// ccnt reg
27#define CCNT_REG (1 << 31) 27#define CCNT_REG (1 << 31)
28 28
29#define CCNT 0 29#define CCNT 0
30#define CNT0 1 30#define CNT0 1
31#define CNTMAX (4+1) 31#define CNTMAX (4+1)
32 32
33static unsigned long pmnc_enabled[CNTMAX]; 33static unsigned long pmnc_enabled[CNTMAX];
34static unsigned long pmnc_event[CNTMAX]; 34static unsigned long pmnc_event[CNTMAX];
diff --git a/driver/gator_iks.c b/driver/gator_iks.c
index 9180b87..e90dfcc 100644
--- a/driver/gator_iks.c
+++ b/driver/gator_iks.c
@@ -150,7 +150,7 @@ static void gator_send_iks_core_names(void)
150 preempt_disable(); 150 preempt_disable();
151 for (cpu = 0; cpu < nr_cpu_ids; ++cpu) { 151 for (cpu = 0; cpu < nr_cpu_ids; ++cpu) {
152 if (mpidr_cpus[cpu] != NULL) { 152 if (mpidr_cpus[cpu] != NULL) {
153 gator_send_core_name(cpu, mpidr_cpus[cpu]->cpuid); 153 gator_send_core_name(cpu, mpidr_cpus[cpu]->cpuid, mpidr_cpus[cpu]);
154 } 154 }
155 } 155 }
156 preempt_enable(); 156 preempt_enable();
diff --git a/driver/gator_main.c b/driver/gator_main.c
index 0d867f2..55772ef 100644
--- a/driver/gator_main.c
+++ b/driver/gator_main.c
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10// This version must match the gator daemon version 10// This version must match the gator daemon version
11#define PROTOCOL_VERSION 19 11#define PROTOCOL_VERSION 18
12static unsigned long gator_protocol_version = PROTOCOL_VERSION; 12static unsigned long gator_protocol_version = PROTOCOL_VERSION;
13 13
14#include <linux/slab.h> 14#include <linux/slab.h>
@@ -55,9 +55,9 @@ static unsigned long gator_protocol_version = PROTOCOL_VERSION;
55 55
56#if (GATOR_PERF_SUPPORT) && (!(GATOR_PERF_PMU_SUPPORT)) 56#if (GATOR_PERF_SUPPORT) && (!(GATOR_PERF_PMU_SUPPORT))
57#ifndef CONFIG_PERF_EVENTS 57#ifndef CONFIG_PERF_EVENTS
58#error gator requires the kernel to have CONFIG_PERF_EVENTS defined to support pmu hardware counters 58#warning gator requires the kernel to have CONFIG_PERF_EVENTS defined to support pmu hardware counters
59#elif !defined CONFIG_HW_PERF_EVENTS 59#elif !defined CONFIG_HW_PERF_EVENTS
60#error gator requires the kernel to have CONFIG_HW_PERF_EVENTS defined to support pmu hardware counters 60#warning gator requires the kernel to have CONFIG_HW_PERF_EVENTS defined to support pmu hardware counters
61#endif 61#endif
62#endif 62#endif
63 63
@@ -71,8 +71,8 @@ static unsigned long gator_protocol_version = PROTOCOL_VERSION;
71#define BLOCK_COUNTER_BUFFER_SIZE (128*1024) 71#define BLOCK_COUNTER_BUFFER_SIZE (128*1024)
72#define ANNOTATE_BUFFER_SIZE (128*1024) // annotate counters have the core as part of the data and the core value in the frame header may be discarded 72#define ANNOTATE_BUFFER_SIZE (128*1024) // annotate counters have the core as part of the data and the core value in the frame header may be discarded
73#define SCHED_TRACE_BUFFER_SIZE (128*1024) 73#define SCHED_TRACE_BUFFER_SIZE (128*1024)
74#define GPU_TRACE_BUFFER_SIZE (64*1024) // gpu trace counters have the core as part of the data and the core value in the frame header may be discarded
74#define IDLE_BUFFER_SIZE (32*1024) // idle counters have the core as part of the data and the core value in the frame header may be discarded 75#define IDLE_BUFFER_SIZE (32*1024) // idle counters have the core as part of the data and the core value in the frame header may be discarded
75#define ACTIVITY_BUFFER_SIZE (128*1024)
76 76
77#define NO_COOKIE 0U 77#define NO_COOKIE 0U
78#define UNRESOLVED_COOKIE ~0U 78#define UNRESOLVED_COOKIE ~0U
@@ -84,8 +84,8 @@ static unsigned long gator_protocol_version = PROTOCOL_VERSION;
84#define FRAME_BLOCK_COUNTER 5 84#define FRAME_BLOCK_COUNTER 5
85#define FRAME_ANNOTATE 6 85#define FRAME_ANNOTATE 6
86#define FRAME_SCHED_TRACE 7 86#define FRAME_SCHED_TRACE 7
87#define FRAME_GPU_TRACE 8
87#define FRAME_IDLE 9 88#define FRAME_IDLE 9
88#define FRAME_ACTIVITY 13
89 89
90#define MESSAGE_END_BACKTRACE 1 90#define MESSAGE_END_BACKTRACE 1
91 91
@@ -94,9 +94,14 @@ static unsigned long gator_protocol_version = PROTOCOL_VERSION;
94#define MESSAGE_THREAD_NAME 2 94#define MESSAGE_THREAD_NAME 2
95#define MESSAGE_LINK 4 95#define MESSAGE_LINK 4
96 96
97// GPU Trace Frame Messages
98#define MESSAGE_GPU_START 1
99#define MESSAGE_GPU_STOP 2
100
97// Scheduler Trace Frame Messages 101// Scheduler Trace Frame Messages
98#define MESSAGE_SCHED_SWITCH 1 102#define MESSAGE_SCHED_SWITCH 1
99#define MESSAGE_SCHED_EXIT 2 103#define MESSAGE_SCHED_EXIT 2
104#define MESSAGE_SCHED_START 3
100 105
101// Idle Frame Messages 106// Idle Frame Messages
102#define MESSAGE_IDLE_ENTER 1 107#define MESSAGE_IDLE_ENTER 1
@@ -106,10 +111,6 @@ static unsigned long gator_protocol_version = PROTOCOL_VERSION;
106#define MESSAGE_SUMMARY 1 111#define MESSAGE_SUMMARY 1
107#define MESSAGE_CORE_NAME 3 112#define MESSAGE_CORE_NAME 3
108 113
109// Activity Frame Messages
110#define MESSAGE_SWITCH 2
111#define MESSAGE_EXIT 3
112
113#define MAXSIZE_PACK32 5 114#define MAXSIZE_PACK32 5
114#define MAXSIZE_PACK64 10 115#define MAXSIZE_PACK64 10
115 116
@@ -131,8 +132,8 @@ enum {
131 BLOCK_COUNTER_BUF, 132 BLOCK_COUNTER_BUF,
132 ANNOTATE_BUF, 133 ANNOTATE_BUF,
133 SCHED_TRACE_BUF, 134 SCHED_TRACE_BUF,
135 GPU_TRACE_BUF,
134 IDLE_BUF, 136 IDLE_BUF,
135 ACTIVITY_BUF,
136 NUM_GATOR_BUFS 137 NUM_GATOR_BUFS
137}; 138};
138 139
@@ -174,7 +175,6 @@ static DEFINE_PER_CPU(u64, last_timestamp);
174 175
175static bool printed_monotonic_warning; 176static bool printed_monotonic_warning;
176 177
177static u32 gator_cpuids[NR_CPUS];
178static bool sent_core_name[NR_CPUS]; 178static bool sent_core_name[NR_CPUS];
179 179
180static DEFINE_PER_CPU(bool, in_scheduler_context); 180static DEFINE_PER_CPU(bool, in_scheduler_context);
@@ -226,7 +226,6 @@ static DEFINE_PER_CPU(u64, gator_buffer_commit_time);
226 GATOR_EVENT(gator_events_perf_pmu_init) \ 226 GATOR_EVENT(gator_events_perf_pmu_init) \
227 GATOR_EVENT(gator_events_sched_init) \ 227 GATOR_EVENT(gator_events_sched_init) \
228 GATOR_EVENT(gator_events_scorpion_init) \ 228 GATOR_EVENT(gator_events_scorpion_init) \
229 GATOR_EVENT(gator_events_threads_init) \
230 229
231#define GATOR_EVENT(EVENT_INIT) __weak int EVENT_INIT(void); 230#define GATOR_EVENT(EVENT_INIT) __weak int EVENT_INIT(void);
232GATOR_EVENTS_LIST 231GATOR_EVENTS_LIST
@@ -571,37 +570,25 @@ static void gator_timer_stop(void)
571 } 570 }
572} 571}
573 572
574static void gator_send_core_name(const int cpu, const u32 cpuid)
575{
576#if defined(__arm__) || defined(__aarch64__) 573#if defined(__arm__) || defined(__aarch64__)
577 if (!sent_core_name[cpu] || (cpuid != gator_cpuids[cpu])) { 574static void gator_send_core_name(int cpu, const u32 cpuid, const struct gator_cpu *const gator_cpu)
578 const struct gator_cpu *const gator_cpu = gator_find_cpu_by_cpuid(cpuid); 575{
579 const char *core_name = NULL; 576 const char *core_name = NULL;
580 char core_name_buf[32]; 577 char core_name_buf[32];
581 578
582 // Save off this cpuid 579 if (!sent_core_name[cpu]) {
583 gator_cpuids[cpu] = cpuid;
584 if (gator_cpu != NULL) { 580 if (gator_cpu != NULL) {
585 core_name = gator_cpu->core_name; 581 core_name = gator_cpu->core_name;
586 } else { 582 } else {
587 if (cpuid == -1) { 583 snprintf(core_name_buf, sizeof(core_name_buf), "Unknown (0x%.3x)", cpuid);
588 snprintf(core_name_buf, sizeof(core_name_buf), "Unknown");
589 } else {
590 snprintf(core_name_buf, sizeof(core_name_buf), "Unknown (0x%.3x)", cpuid);
591 }
592 core_name = core_name_buf; 584 core_name = core_name_buf;
593 } 585 }
594 586
595 marshal_core_name(cpu, cpuid, core_name); 587 marshal_core_name(cpu, cpuid, core_name);
596 sent_core_name[cpu] = true; 588 sent_core_name[cpu] = true;
597 } 589 }
598#endif
599}
600
601static void gator_read_cpuid(void * arg)
602{
603 gator_cpuids[get_physical_cpu()] = gator_cpuid();
604} 590}
591#endif
605 592
606// This function runs in interrupt context and on the appropriate core 593// This function runs in interrupt context and on the appropriate core
607static void gator_timer_online(void *migrate) 594static void gator_timer_online(void *migrate)
@@ -611,9 +598,6 @@ static void gator_timer_online(void *migrate)
611 int *buffer; 598 int *buffer;
612 u64 time; 599 u64 time;
613 600
614 // Send what is currently running on this core
615 marshal_sched_trace_switch(current->pid, 0);
616
617 gator_trace_power_online(); 601 gator_trace_power_online();
618 602
619 // online any events and output counters 603 // online any events and output counters
@@ -633,7 +617,12 @@ static void gator_timer_online(void *migrate)
633 gator_hrtimer_online(); 617 gator_hrtimer_online();
634 } 618 }
635 619
636 gator_send_core_name(cpu, gator_cpuid()); 620#if defined(__arm__) || defined(__aarch64__)
621 if (!sent_core_name[cpu]) {
622 const u32 cpuid = gator_cpuid();
623 gator_send_core_name(cpu, cpuid, gator_find_cpu_by_cpuid(cpuid));
624 }
625#endif
637} 626}
638 627
639// This function runs in interrupt context and may be running on a core other than core 'cpu' 628// This function runs in interrupt context and may be running on a core other than core 'cpu'
@@ -669,13 +658,6 @@ static int gator_timer_start(unsigned long sample_rate)
669 if (gator_hrtimer_init(sample_rate, gator_timer_interrupt) == -1) 658 if (gator_hrtimer_init(sample_rate, gator_timer_interrupt) == -1)
670 return -1; 659 return -1;
671 660
672 // Send off the previously saved cpuids
673 for_each_present_cpu(cpu) {
674 preempt_disable();
675 gator_send_core_name(cpu, gator_cpuids[cpu]);
676 preempt_enable();
677 }
678
679 gator_send_iks_core_names(); 661 gator_send_iks_core_names();
680 for_each_online_cpu(cpu) { 662 for_each_online_cpu(cpu) {
681 gator_timer_online_dispatch(lcpu_to_pcpu(cpu), false); 663 gator_timer_online_dispatch(lcpu_to_pcpu(cpu), false);
@@ -1027,12 +1009,12 @@ static int gator_op_setup(void)
1027 gator_buffer_size[SCHED_TRACE_BUF] = SCHED_TRACE_BUFFER_SIZE; 1009 gator_buffer_size[SCHED_TRACE_BUF] = SCHED_TRACE_BUFFER_SIZE;
1028 gator_buffer_mask[SCHED_TRACE_BUF] = SCHED_TRACE_BUFFER_SIZE - 1; 1010 gator_buffer_mask[SCHED_TRACE_BUF] = SCHED_TRACE_BUFFER_SIZE - 1;
1029 1011
1012 gator_buffer_size[GPU_TRACE_BUF] = GPU_TRACE_BUFFER_SIZE;
1013 gator_buffer_mask[GPU_TRACE_BUF] = GPU_TRACE_BUFFER_SIZE - 1;
1014
1030 gator_buffer_size[IDLE_BUF] = IDLE_BUFFER_SIZE; 1015 gator_buffer_size[IDLE_BUF] = IDLE_BUFFER_SIZE;
1031 gator_buffer_mask[IDLE_BUF] = IDLE_BUFFER_SIZE - 1; 1016 gator_buffer_mask[IDLE_BUF] = IDLE_BUFFER_SIZE - 1;
1032 1017
1033 gator_buffer_size[ACTIVITY_BUF] = ACTIVITY_BUFFER_SIZE;
1034 gator_buffer_mask[ACTIVITY_BUF] = ACTIVITY_BUFFER_SIZE - 1;
1035
1036 // Initialize percpu per buffer variables 1018 // Initialize percpu per buffer variables
1037 for (i = 0; i < NUM_GATOR_BUFS; i++) { 1019 for (i = 0; i < NUM_GATOR_BUFS; i++) {
1038 // Verify buffers are a power of 2 1020 // Verify buffers are a power of 2
@@ -1391,7 +1373,6 @@ static void gator_op_create_files(struct super_block *sb, struct dentry *root)
1391 GATOR_HANDLE_TRACEPOINT(mm_page_alloc); \ 1373 GATOR_HANDLE_TRACEPOINT(mm_page_alloc); \
1392 GATOR_HANDLE_TRACEPOINT(mm_page_free); \ 1374 GATOR_HANDLE_TRACEPOINT(mm_page_free); \
1393 GATOR_HANDLE_TRACEPOINT(mm_page_free_batched); \ 1375 GATOR_HANDLE_TRACEPOINT(mm_page_free_batched); \
1394 GATOR_HANDLE_TRACEPOINT(sched_process_exec); \
1395 GATOR_HANDLE_TRACEPOINT(sched_process_fork); \ 1376 GATOR_HANDLE_TRACEPOINT(sched_process_fork); \
1396 GATOR_HANDLE_TRACEPOINT(sched_process_free); \ 1377 GATOR_HANDLE_TRACEPOINT(sched_process_free); \
1397 GATOR_HANDLE_TRACEPOINT(sched_switch); \ 1378 GATOR_HANDLE_TRACEPOINT(sched_switch); \
@@ -1434,10 +1415,6 @@ static int __init gator_module_init(void)
1434 1415
1435 setup_timer(&gator_buffer_wake_up_timer, gator_buffer_wake_up, 0); 1416 setup_timer(&gator_buffer_wake_up_timer, gator_buffer_wake_up, 0);
1436 1417
1437 // Initialize the list of cpuids
1438 memset(gator_cpuids, -1, sizeof(gator_cpuids));
1439 on_each_cpu(gator_read_cpuid, NULL, 1);
1440
1441 return 0; 1418 return 0;
1442} 1419}
1443 1420
diff --git a/driver/gator_marshaling.c b/driver/gator_marshaling.c
index 97b4ae6..18c890d 100644
--- a/driver/gator_marshaling.c
+++ b/driver/gator_marshaling.c
@@ -231,28 +231,77 @@ static void marshal_event_single(int core, int key, int value)
231 // Check and commit; commit is set to occur once buffer is 3/4 full 231 // Check and commit; commit is set to occur once buffer is 3/4 full
232 buffer_check(cpu, COUNTER_BUF, time); 232 buffer_check(cpu, COUNTER_BUF, time);
233} 233}
234#endif
234 235
235static void marshal_event_single64(int core, int key, long long value) 236#if defined(MALI_SUPPORT)
237static void marshal_sched_gpu_start(int unit, int core, int tgid, int pid)
236{ 238{
237 unsigned long flags, cpu; 239 unsigned long cpu = get_physical_cpu(), flags;
238 u64 time; 240 u64 time;
239 241
242 if (!per_cpu(gator_buffer, cpu)[GPU_TRACE_BUF])
243 return;
244
240 local_irq_save(flags); 245 local_irq_save(flags);
241 cpu = get_physical_cpu();
242 time = gator_get_time(); 246 time = gator_get_time();
243 if (buffer_check_space(cpu, COUNTER_BUF, 2 * MAXSIZE_PACK64 + 2 * MAXSIZE_PACK32)) { 247 if (buffer_check_space(cpu, GPU_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
244 gator_buffer_write_packed_int64(cpu, COUNTER_BUF, time); 248 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, MESSAGE_GPU_START);
245 gator_buffer_write_packed_int(cpu, COUNTER_BUF, core); 249 gator_buffer_write_packed_int64(cpu, GPU_TRACE_BUF, time);
246 gator_buffer_write_packed_int(cpu, COUNTER_BUF, key); 250 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, unit);
247 gator_buffer_write_packed_int64(cpu, COUNTER_BUF, value); 251 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, core);
252 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, tgid);
253 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, pid);
248 } 254 }
249 local_irq_restore(flags); 255 local_irq_restore(flags);
250 // Check and commit; commit is set to occur once buffer is 3/4 full 256 // Check and commit; commit is set to occur once buffer is 3/4 full
251 buffer_check(cpu, COUNTER_BUF, time); 257 buffer_check(cpu, GPU_TRACE_BUF, time);
258}
259
260static void marshal_sched_gpu_stop(int unit, int core)
261{
262 unsigned long cpu = get_physical_cpu(), flags;
263 u64 time;
264
265 if (!per_cpu(gator_buffer, cpu)[GPU_TRACE_BUF])
266 return;
267
268 local_irq_save(flags);
269 time = gator_get_time();
270 if (buffer_check_space(cpu, GPU_TRACE_BUF, MAXSIZE_PACK64 + 3 * MAXSIZE_PACK32)) {
271 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, MESSAGE_GPU_STOP);
272 gator_buffer_write_packed_int64(cpu, GPU_TRACE_BUF, time);
273 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, unit);
274 gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, core);
275 }
276 local_irq_restore(flags);
277 // Check and commit; commit is set to occur once buffer is 3/4 full
278 buffer_check(cpu, GPU_TRACE_BUF, time);
252} 279}
253#endif 280#endif
254 281
255static void marshal_sched_trace_switch(int pid, int state) 282static void marshal_sched_trace_start(int tgid, int pid, int cookie)
283{
284 unsigned long cpu = get_physical_cpu(), flags;
285 u64 time;
286
287 if (!per_cpu(gator_buffer, cpu)[SCHED_TRACE_BUF])
288 return;
289
290 local_irq_save(flags);
291 time = gator_get_time();
292 if (buffer_check_space(cpu, SCHED_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
293 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, MESSAGE_SCHED_START);
294 gator_buffer_write_packed_int64(cpu, SCHED_TRACE_BUF, time);
295 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, tgid);
296 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, pid);
297 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, cookie);
298 }
299 local_irq_restore(flags);
300 // Check and commit; commit is set to occur once buffer is 3/4 full
301 buffer_check(cpu, SCHED_TRACE_BUF, time);
302}
303
304static void marshal_sched_trace_switch(int tgid, int pid, int cookie, int state)
256{ 305{
257 unsigned long cpu = get_physical_cpu(), flags; 306 unsigned long cpu = get_physical_cpu(), flags;
258 u64 time; 307 u64 time;
@@ -265,7 +314,9 @@ static void marshal_sched_trace_switch(int pid, int state)
265 if (buffer_check_space(cpu, SCHED_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) { 314 if (buffer_check_space(cpu, SCHED_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
266 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, MESSAGE_SCHED_SWITCH); 315 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, MESSAGE_SCHED_SWITCH);
267 gator_buffer_write_packed_int64(cpu, SCHED_TRACE_BUF, time); 316 gator_buffer_write_packed_int64(cpu, SCHED_TRACE_BUF, time);
317 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, tgid);
268 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, pid); 318 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, pid);
319 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, cookie);
269 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, state); 320 gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, state);
270 } 321 }
271 local_irq_restore(flags); 322 local_irq_restore(flags);
@@ -330,33 +381,3 @@ static void marshal_core_name(const int core, const int cpuid, const char *name)
330 gator_commit_buffer(cpu, SUMMARY_BUF, gator_get_time()); 381 gator_commit_buffer(cpu, SUMMARY_BUF, gator_get_time());
331} 382}
332#endif 383#endif
333
334static void marshal_activity_switch(int core, int key, int activity, int pid, int state)
335{
336 unsigned long cpu = get_physical_cpu(), flags;
337 u64 time;
338
339 if (!per_cpu(gator_buffer, cpu)[ACTIVITY_BUF])
340 return;
341
342 local_irq_save(flags);
343 time = gator_get_time();
344 if (buffer_check_space(cpu, ACTIVITY_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
345 gator_buffer_write_packed_int(cpu, ACTIVITY_BUF, MESSAGE_SWITCH);
346 gator_buffer_write_packed_int64(cpu, ACTIVITY_BUF, time);
347 gator_buffer_write_packed_int(cpu, ACTIVITY_BUF, core);
348 gator_buffer_write_packed_int(cpu, ACTIVITY_BUF, key);
349 gator_buffer_write_packed_int(cpu, ACTIVITY_BUF, activity);
350 gator_buffer_write_packed_int(cpu, ACTIVITY_BUF, pid);
351 gator_buffer_write_packed_int(cpu, ACTIVITY_BUF, state);
352 }
353 local_irq_restore(flags);
354 // Check and commit; commit is set to occur once buffer is 3/4 full
355 buffer_check(cpu, ACTIVITY_BUF, time);
356}
357
358void gator_marshal_activity_switch(int core, int key, int activity, int pid)
359{
360 // state is reserved for cpu use only
361 marshal_activity_switch(core, key, activity, pid, 0);
362}
diff --git a/driver/gator_trace_gpu.c b/driver/gator_trace_gpu.c
index a8b9e7d..6afa548 100644
--- a/driver/gator_trace_gpu.c
+++ b/driver/gator_trace_gpu.c
@@ -44,19 +44,21 @@ enum {
44 NUMBER_OF_GPU_UNITS 44 NUMBER_OF_GPU_UNITS
45}; 45};
46 46
47#define MALI_4xx (0x0b07)
48#define MALI_T6xx (0x0056)
49
47#if defined(MALI_SUPPORT) 50#if defined(MALI_SUPPORT)
48 51
49struct mali_activity { 52struct mali_gpu_job {
50 int core;
51 int key;
52 int count; 53 int count;
53 int last_activity; 54 int last_tgid;
54 int last_pid; 55 int last_pid;
56 int last_job_id;
55}; 57};
56 58
57#define NUMBER_OF_GPU_CORES 16 59#define NUMBER_OF_GPU_CORES 16
58static struct mali_activity mali_activities[NUMBER_OF_GPU_UNITS*NUMBER_OF_GPU_CORES]; 60static struct mali_gpu_job mali_gpu_jobs[NUMBER_OF_GPU_UNITS][NUMBER_OF_GPU_CORES];
59static DEFINE_SPINLOCK(mali_activities_lock); 61static DEFINE_SPINLOCK(mali_gpu_jobs_lock);
60 62
61/* Only one event should be running on a unit and core at a time (ie, a start 63/* Only one event should be running on a unit and core at a time (ie, a start
62 * event can only be followed by a stop and vice versa), but because the kernel 64 * event can only be followed by a stop and vice versa), but because the kernel
@@ -64,95 +66,52 @@ static DEFINE_SPINLOCK(mali_activities_lock);
64 * start1, start2, stop1, stop2. Change it back into start1, stop1, start2, 66 * start1, start2, stop1, stop2. Change it back into start1, stop1, start2,
65 * stop2 by queueing up start2 and releasing it when stop1 is received. 67 * stop2 by queueing up start2 and releasing it when stop1 is received.
66 */ 68 */
67 69static void mali_gpu_enqueue(int unit, int core, int tgid, int pid, int job_id)
68static int mali_activity_index(int core, int key)
69{
70 int i;
71
72 for (i = 0; i < ARRAY_SIZE(mali_activities); ++i) {
73 if ((mali_activities[i].core == core) && (mali_activities[i].key == key)) {
74 break;
75 }
76 if ((mali_activities[i].core == 0) && (mali_activities[i].key == 0)) {
77 mali_activities[i].core = core;
78 mali_activities[i].key = key;
79 break;
80 }
81 }
82 BUG_ON(i >= ARRAY_SIZE(mali_activities));
83
84 return i;
85}
86
87static void mali_activity_enqueue(int core, int key, int activity, int pid)
88{ 70{
89 int i;
90 int count; 71 int count;
91 72
92 spin_lock(&mali_activities_lock); 73 spin_lock(&mali_gpu_jobs_lock);
93 i = mali_activity_index(core, key); 74 count = mali_gpu_jobs[unit][core].count;
94
95 count = mali_activities[i].count;
96 BUG_ON(count < 0); 75 BUG_ON(count < 0);
97 ++mali_activities[i].count; 76 ++mali_gpu_jobs[unit][core].count;
98 if (count) { 77 if (count) {
99 mali_activities[i].last_activity = activity; 78 mali_gpu_jobs[unit][core].last_tgid = tgid;
100 mali_activities[i].last_pid = pid; 79 mali_gpu_jobs[unit][core].last_pid = pid;
80 mali_gpu_jobs[unit][core].last_job_id = job_id;
101 } 81 }
102 spin_unlock(&mali_activities_lock); 82 spin_unlock(&mali_gpu_jobs_lock);
103 83
104 if (!count) { 84 if (!count) {
105 gator_marshal_activity_switch(core, key, activity, pid); 85 marshal_sched_gpu_start(unit, core, tgid, pid/*, job_id*/);
106 } 86 }
107} 87}
108 88
109static void mali_activity_stop(int core, int key) 89static void mali_gpu_stop(int unit, int core)
110{ 90{
111 int i;
112 int count; 91 int count;
113 int last_activity = 0; 92 int last_tgid = 0;
114 int last_pid = 0; 93 int last_pid = 0;
94 //int last_job_id = 0;
115 95
116 spin_lock(&mali_activities_lock); 96 spin_lock(&mali_gpu_jobs_lock);
117 i = mali_activity_index(core, key); 97 if (mali_gpu_jobs[unit][core].count == 0) {
118 98 spin_unlock(&mali_gpu_jobs_lock);
119 if (mali_activities[i].count == 0) {
120 spin_unlock(&mali_activities_lock);
121 return; 99 return;
122 } 100 }
123 --mali_activities[i].count; 101 --mali_gpu_jobs[unit][core].count;
124 count = mali_activities[i].count; 102 count = mali_gpu_jobs[unit][core].count;
125 if (count) { 103 if (count) {
126 last_activity = mali_activities[i].last_activity; 104 last_tgid = mali_gpu_jobs[unit][core].last_tgid;
127 last_pid = mali_activities[i].last_pid; 105 last_pid = mali_gpu_jobs[unit][core].last_pid;
106 //last_job_id = mali_gpu_jobs[unit][core].last_job_id;
128 } 107 }
129 spin_unlock(&mali_activities_lock); 108 spin_unlock(&mali_gpu_jobs_lock);
130 109
131 gator_marshal_activity_switch(core, key, 0, 0); 110 marshal_sched_gpu_stop(unit, core);
132 if (count) { 111 if (count) {
133 gator_marshal_activity_switch(core, key, last_activity, last_pid); 112 marshal_sched_gpu_start(unit, core, last_tgid, last_pid/*, last_job_id*/);
134 } 113 }
135} 114}
136
137void mali_activity_clear(mali_counter mali_activity[], size_t mali_activity_size)
138{
139 int activity;
140 int cores;
141 int core;
142
143 for (activity = 0; activity < mali_activity_size; ++activity) {
144 cores = mali_activity[activity].cores;
145 if (cores < 0) {
146 cores = 1;
147 }
148 for (core = 0; core < cores; ++core) {
149 if (mali_activity[activity].enabled) {
150 gator_marshal_activity_switch(core, mali_activity[activity].key, 0, 0);
151 }
152 }
153 }
154}
155
156#endif 115#endif
157 116
158#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx) 117#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx)
@@ -183,8 +142,6 @@ enum {
183 EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE = 1, 142 EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE = 1,
184}; 143};
185 144
186mali_counter mali_activity[2];
187
188GATOR_DEFINE_PROBE(mali_timeline_event, TP_PROTO(unsigned int event_id, unsigned int d0, unsigned int d1, unsigned int d2, unsigned int d3, unsigned int d4)) 145GATOR_DEFINE_PROBE(mali_timeline_event, TP_PROTO(unsigned int event_id, unsigned int d0, unsigned int d1, unsigned int d2, unsigned int d3, unsigned int d4))
189{ 146{
190 unsigned int component, state; 147 unsigned int component, state;
@@ -197,26 +154,18 @@ GATOR_DEFINE_PROBE(mali_timeline_event, TP_PROTO(unsigned int event_id, unsigned
197 case EVENT_TYPE_START: 154 case EVENT_TYPE_START:
198 if (component == EVENT_CHANNEL_VP0) { 155 if (component == EVENT_CHANNEL_VP0) {
199 /* tgid = d0; pid = d1; */ 156 /* tgid = d0; pid = d1; */
200 if (mali_activity[1].enabled) { 157 mali_gpu_enqueue(GPU_UNIT_VP, 0, d0, d1, 0);
201 mali_activity_enqueue(0, mali_activity[1].key, 1, d1);
202 }
203 } else if (component >= EVENT_CHANNEL_FP0 && component <= EVENT_CHANNEL_FP7) { 158 } else if (component >= EVENT_CHANNEL_FP0 && component <= EVENT_CHANNEL_FP7) {
204 /* tgid = d0; pid = d1; */ 159 /* tgid = d0; pid = d1; */
205 if (mali_activity[0].enabled) { 160 mali_gpu_enqueue(GPU_UNIT_FP, component - EVENT_CHANNEL_FP0, d0, d1, 0);
206 mali_activity_enqueue(component - EVENT_CHANNEL_FP0, mali_activity[0].key, 1, d1);
207 }
208 } 161 }
209 break; 162 break;
210 163
211 case EVENT_TYPE_STOP: 164 case EVENT_TYPE_STOP:
212 if (component == EVENT_CHANNEL_VP0) { 165 if (component == EVENT_CHANNEL_VP0) {
213 if (mali_activity[1].enabled) { 166 mali_gpu_stop(GPU_UNIT_VP, 0);
214 mali_activity_stop(0, mali_activity[1].key);
215 }
216 } else if (component >= EVENT_CHANNEL_FP0 && component <= EVENT_CHANNEL_FP7) { 167 } else if (component >= EVENT_CHANNEL_FP0 && component <= EVENT_CHANNEL_FP7) {
217 if (mali_activity[0].enabled) { 168 mali_gpu_stop(GPU_UNIT_FP, component - EVENT_CHANNEL_FP0);
218 mali_activity_stop(component - EVENT_CHANNEL_FP0, mali_activity[0].key);
219 }
220 } 169 }
221 break; 170 break;
222 171
@@ -237,9 +186,6 @@ GATOR_DEFINE_PROBE(mali_timeline_event, TP_PROTO(unsigned int event_id, unsigned
237#endif 186#endif
238 187
239#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx) 188#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx)
240
241mali_counter mali_activity[3];
242
243#if defined(MALI_JOB_SLOTS_EVENT_CHANGED) 189#if defined(MALI_JOB_SLOTS_EVENT_CHANGED)
244GATOR_DEFINE_PROBE(mali_job_slots_event, TP_PROTO(unsigned int event_id, unsigned int tgid, unsigned int pid, unsigned char job_id)) 190GATOR_DEFINE_PROBE(mali_job_slots_event, TP_PROTO(unsigned int event_id, unsigned int tgid, unsigned int pid, unsigned char job_id))
245#else 191#else
@@ -271,16 +217,16 @@ GATOR_DEFINE_PROBE(mali_job_slots_event, TP_PROTO(unsigned int event_id, unsigne
271 if (unit != GPU_UNIT_NONE) { 217 if (unit != GPU_UNIT_NONE) {
272 switch (state) { 218 switch (state) {
273 case EVENT_TYPE_START: 219 case EVENT_TYPE_START:
274 if (mali_activity[component].enabled) { 220 mali_gpu_enqueue(unit, 0, tgid, (pid != 0 ? pid : tgid), job_id);
275 mali_activity_enqueue(0, mali_activity[component].key, 1, (pid != 0 ? pid : tgid));
276 }
277 break; 221 break;
278 case EVENT_TYPE_STOP: 222 case EVENT_TYPE_STOP:
279 default: // Some jobs can be soft-stopped, so ensure that this terminates the activity trace. 223 mali_gpu_stop(unit, 0);
280 if (mali_activity[component].enabled) {
281 mali_activity_stop(0, mali_activity[component].key);
282 }
283 break; 224 break;
225 default:
226 /*
227 * Some jobs can be soft-stopped, so ensure that this terminates the activity trace.
228 */
229 mali_gpu_stop(unit, 0);
284 } 230 }
285 } 231 }
286} 232}
@@ -294,19 +240,17 @@ static int gator_trace_gpu_start(void)
294 */ 240 */
295 241
296#if defined(MALI_SUPPORT) 242#if defined(MALI_SUPPORT)
297 memset(&mali_activities, 0, sizeof(mali_activities)); 243 memset(&mali_gpu_jobs, 0, sizeof(mali_gpu_jobs));
298#endif 244#endif
299 mali_timeline_trace_registered = mali_job_slots_trace_registered = 0; 245 mali_timeline_trace_registered = mali_job_slots_trace_registered = 0;
300 246
301#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx) 247#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx)
302 mali_activity_clear(mali_activity, ARRAY_SIZE(mali_activity));
303 if (!GATOR_REGISTER_TRACE(mali_timeline_event)) { 248 if (!GATOR_REGISTER_TRACE(mali_timeline_event)) {
304 mali_timeline_trace_registered = 1; 249 mali_timeline_trace_registered = 1;
305 } 250 }
306#endif 251#endif
307 252
308#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx) 253#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx)
309 mali_activity_clear(mali_activity, ARRAY_SIZE(mali_activity));
310 if (!GATOR_REGISTER_TRACE(mali_job_slots_event)) { 254 if (!GATOR_REGISTER_TRACE(mali_job_slots_event)) {
311 mali_job_slots_trace_registered = 1; 255 mali_job_slots_trace_registered = 1;
312 } 256 }
diff --git a/driver/gator_trace_power.c b/driver/gator_trace_power.c
index f2754b1..1895bb9 100644
--- a/driver/gator_trace_power.c
+++ b/driver/gator_trace_power.c
@@ -75,7 +75,7 @@ static int gator_trace_power_create_files(struct super_block *sb, struct dentry
75GATOR_DEFINE_PROBE(cpu_frequency, TP_PROTO(unsigned int frequency, unsigned int cpu)) 75GATOR_DEFINE_PROBE(cpu_frequency, TP_PROTO(unsigned int frequency, unsigned int cpu))
76{ 76{
77 cpu = lcpu_to_pcpu(cpu); 77 cpu = lcpu_to_pcpu(cpu);
78 marshal_event_single64(cpu, power_cpu_key[POWER_CPU_FREQ], frequency * 1000L); 78 marshal_event_single(cpu, power_cpu_key[POWER_CPU_FREQ], frequency * 1000);
79} 79}
80 80
81GATOR_DEFINE_PROBE(cpu_idle, TP_PROTO(unsigned int state, unsigned int cpu)) 81GATOR_DEFINE_PROBE(cpu_idle, TP_PROTO(unsigned int state, unsigned int cpu))
@@ -109,7 +109,7 @@ static void gator_trace_power_online(void)
109 int pcpu = get_physical_cpu(); 109 int pcpu = get_physical_cpu();
110 int lcpu = get_logical_cpu(); 110 int lcpu = get_logical_cpu();
111 if (power_cpu_enabled[POWER_CPU_FREQ]) { 111 if (power_cpu_enabled[POWER_CPU_FREQ]) {
112 marshal_event_single64(pcpu, power_cpu_key[POWER_CPU_FREQ], cpufreq_quick_get(lcpu) * 1000L); 112 marshal_event_single(pcpu, power_cpu_key[POWER_CPU_FREQ], cpufreq_quick_get(lcpu) * 1000);
113 } 113 }
114} 114}
115 115
diff --git a/driver/gator_trace_sched.c b/driver/gator_trace_sched.c
index 6550086..52990e9 100644
--- a/driver/gator_trace_sched.c
+++ b/driver/gator_trace_sched.c
@@ -114,7 +114,7 @@ static void collect_counters(u64 time, struct task_struct *task)
114 114
115 // Commit buffers on timeout 115 // Commit buffers on timeout
116 if (gator_live_rate > 0 && time >= per_cpu(gator_buffer_commit_time, cpu)) { 116 if (gator_live_rate > 0 && time >= per_cpu(gator_buffer_commit_time, cpu)) {
117 static const int buftypes[] = { NAME_BUF, COUNTER_BUF, BLOCK_COUNTER_BUF, SCHED_TRACE_BUF, ACTIVITY_BUF }; 117 static const int buftypes[] = { NAME_BUF, COUNTER_BUF, BLOCK_COUNTER_BUF, SCHED_TRACE_BUF };
118 int i; 118 int i;
119 119
120 for (i = 0; i < ARRAY_SIZE(buftypes); ++i) { 120 for (i = 0; i < ARRAY_SIZE(buftypes); ++i) {
@@ -137,44 +137,35 @@ static void collect_counters(u64 time, struct task_struct *task)
137// special case used during a suspend of the system 137// special case used during a suspend of the system
138static void trace_sched_insert_idle(void) 138static void trace_sched_insert_idle(void)
139{ 139{
140 marshal_sched_trace_switch(0, 0); 140 marshal_sched_trace_switch(0, 0, 0, 0);
141} 141}
142 142
143static void gator_trace_emit_link(struct task_struct *p) 143GATOR_DEFINE_PROBE(sched_process_fork, TP_PROTO(struct task_struct *parent, struct task_struct *child))
144{ 144{
145 int cookie; 145 int cookie;
146 int cpu = get_physical_cpu(); 146 int cpu = get_physical_cpu();
147 147
148 cookie = get_exec_cookie(cpu, p); 148 cookie = get_exec_cookie(cpu, child);
149 emit_pid_name(p); 149 emit_pid_name(child);
150 150
151 marshal_link(cookie, p->tgid, p->pid); 151 marshal_sched_trace_start(child->tgid, child->pid, cookie);
152} 152}
153 153
154GATOR_DEFINE_PROBE(sched_process_fork, TP_PROTO(struct task_struct *parent, struct task_struct *child))
155{
156 gator_trace_emit_link(child);
157}
158
159#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
160GATOR_DEFINE_PROBE(sched_process_exec, TP_PROTO(struct task_struct *p, pid_t old_pid, struct linux_binprm *bprm))
161{
162 gator_trace_emit_link(p);
163}
164#endif
165
166#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) 154#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
167GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct rq *rq, struct task_struct *prev, struct task_struct *next)) 155GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct rq *rq, struct task_struct *prev, struct task_struct *next))
168#else 156#else
169GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct task_struct *prev, struct task_struct *next)) 157GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct task_struct *prev, struct task_struct *next))
170#endif 158#endif
171{ 159{
160 int cookie;
172 int state; 161 int state;
173 int cpu = get_physical_cpu(); 162 int cpu = get_physical_cpu();
174 163
175 per_cpu(in_scheduler_context, cpu) = true; 164 per_cpu(in_scheduler_context, cpu) = true;
176 165
177 // do as much work as possible before disabling interrupts 166 // do as much work as possible before disabling interrupts
167 cookie = get_exec_cookie(cpu, next);
168 emit_pid_name(next);
178 if (prev->state == TASK_RUNNING) { 169 if (prev->state == TASK_RUNNING) {
179 state = STATE_CONTENTION; 170 state = STATE_CONTENTION;
180 } else if (prev->in_iowait) { 171 } else if (prev->in_iowait) {
@@ -187,10 +178,7 @@ GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct task_struct *prev, struct task_
187 collect_counters(gator_get_time(), prev); 178 collect_counters(gator_get_time(), prev);
188 per_cpu(collecting, cpu) = 0; 179 per_cpu(collecting, cpu) = 0;
189 180
190#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0) 181 marshal_sched_trace_switch(next->tgid, next->pid, cookie, state);
191 gator_trace_emit_link(next);
192#endif
193 marshal_sched_trace_switch(next->pid, state);
194 182
195 per_cpu(in_scheduler_context, cpu) = false; 183 per_cpu(in_scheduler_context, cpu) = false;
196} 184}
@@ -211,10 +199,6 @@ static int register_scheduler_tracepoints(void)
211 // register tracepoints 199 // register tracepoints
212 if (GATOR_REGISTER_TRACE(sched_process_fork)) 200 if (GATOR_REGISTER_TRACE(sched_process_fork))
213 goto fail_sched_process_fork; 201 goto fail_sched_process_fork;
214#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
215 if (GATOR_REGISTER_TRACE(sched_process_exec))
216 goto fail_sched_process_exec;
217#endif
218 if (GATOR_REGISTER_TRACE(sched_switch)) 202 if (GATOR_REGISTER_TRACE(sched_switch))
219 goto fail_sched_switch; 203 goto fail_sched_switch;
220 if (GATOR_REGISTER_TRACE(sched_process_free)) 204 if (GATOR_REGISTER_TRACE(sched_process_free))
@@ -232,42 +216,15 @@ fail_sched_process_free:
232 GATOR_UNREGISTER_TRACE(sched_switch); 216 GATOR_UNREGISTER_TRACE(sched_switch);
233fail_sched_switch: 217fail_sched_switch:
234 GATOR_UNREGISTER_TRACE(sched_process_fork); 218 GATOR_UNREGISTER_TRACE(sched_process_fork);
235#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
236fail_sched_process_exec:
237 GATOR_UNREGISTER_TRACE(sched_process_exec);
238#endif
239fail_sched_process_fork: 219fail_sched_process_fork:
240 pr_err("gator: tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n"); 220 pr_err("gator: tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n");
241 221
242 return -1; 222 return -1;
243} 223}
244 224
245static void unregister_scheduler_tracepoints(void)
246{
247 GATOR_UNREGISTER_TRACE(sched_process_fork);
248#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
249 GATOR_UNREGISTER_TRACE(sched_process_exec);
250#endif
251 GATOR_UNREGISTER_TRACE(sched_switch);
252 GATOR_UNREGISTER_TRACE(sched_process_free);
253 pr_debug("gator: unregistered tracepoints\n");
254}
255
256static void gator_trace_sched_stop(void)
257{
258 int cpu;
259
260 unregister_scheduler_tracepoints();
261
262 for_each_present_cpu(cpu) {
263 kfree(per_cpu(taskname_keys, cpu));
264 }
265}
266
267static int gator_trace_sched_start(void) 225static int gator_trace_sched_start(void)
268{ 226{
269 int cpu, size; 227 int cpu, size;
270 int ret;
271 228
272 for_each_present_cpu(cpu) { 229 for_each_present_cpu(cpu) {
273 size = TASK_MAP_ENTRIES * TASK_MAX_COLLISIONS * sizeof(uint64_t); 230 size = TASK_MAP_ENTRIES * TASK_MAX_COLLISIONS * sizeof(uint64_t);
@@ -277,9 +234,7 @@ static int gator_trace_sched_start(void)
277 memset(per_cpu(taskname_keys, cpu), 0, size); 234 memset(per_cpu(taskname_keys, cpu), 0, size);
278 } 235 }
279 236
280 ret = register_scheduler_tracepoints(); 237 return register_scheduler_tracepoints();
281
282 return ret;
283} 238}
284 239
285static void gator_trace_sched_offline(void) 240static void gator_trace_sched_offline(void)
@@ -287,6 +242,24 @@ static void gator_trace_sched_offline(void)
287 trace_sched_insert_idle(); 242 trace_sched_insert_idle();
288} 243}
289 244
245static void unregister_scheduler_tracepoints(void)
246{
247 GATOR_UNREGISTER_TRACE(sched_process_fork);
248 GATOR_UNREGISTER_TRACE(sched_switch);
249 GATOR_UNREGISTER_TRACE(sched_process_free);
250 pr_debug("gator: unregistered tracepoints\n");
251}
252
253static void gator_trace_sched_stop(void)
254{
255 int cpu;
256 unregister_scheduler_tracepoints();
257
258 for_each_present_cpu(cpu) {
259 kfree(per_cpu(taskname_keys, cpu));
260 }
261}
262
290static void gator_trace_sched_init(void) 263static void gator_trace_sched_init(void)
291{ 264{
292 int i; 265 int i;
diff --git a/driver/mali_t6xx.mk b/driver/mali_t6xx.mk
index fa7571d..059d47a 100644
--- a/driver/mali_t6xx.mk
+++ b/driver/mali_t6xx.mk
@@ -21,10 +21,6 @@ OSK_DIR = $(DDK_DIR)/drivers/gpu/arm/midgard/osk
21EXTRA_CFLAGS += -DMALI_DIR_MIDGARD=1 21EXTRA_CFLAGS += -DMALI_DIR_MIDGARD=1
22endif 22endif
23 23
24ifneq ($(wildcard $(DDK_DIR)/drivers/gpu/arm/midgard/mali_dd_gator_api.h),)
25EXTRA_CFLAGS += -DMALI_SIMPLE_API=1
26endif
27
28UMP_DIR = $(DDK_DIR)/include/linux 24UMP_DIR = $(DDK_DIR)/include/linux
29 25
30# Include directories in the DDK 26# Include directories in the DDK