diff options
Diffstat (limited to 'daemon/events-Cortex-A15.xml')
| -rw-r--r-- | daemon/events-Cortex-A15.xml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/daemon/events-Cortex-A15.xml b/daemon/events-Cortex-A15.xml index e3de814..faa8b1c 100644 --- a/daemon/events-Cortex-A15.xml +++ b/daemon/events-Cortex-A15.xml | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | <counter_set name="ARM_Cortex-A15_cnt" count="6"/> | 1 | <counter_set name="ARM_Cortex-A15_cnt" count="6"/> |
| 2 | <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes"> | 2 | <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes"> |
| 3 | <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> | 3 | <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/> |
| 4 | <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> | 4 | <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> |
| 5 | <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> | 5 | <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> |
| 6 | <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> | 6 | <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> |