diff options
Diffstat (limited to 'daemon/events-Cortex-A5.xml')
| -rw-r--r-- | daemon/events-Cortex-A5.xml | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/daemon/events-Cortex-A5.xml b/daemon/events-Cortex-A5.xml index 4a894d3..77dd838 100644 --- a/daemon/events-Cortex-A5.xml +++ b/daemon/events-Cortex-A5.xml | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | <counter_set name="ARM_Cortex-A5_cnt" count="2"/> | 1 | <counter_set name="ARM_Cortex-A5_cnt" count="2"/> |
| 2 | <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cnt" per_cpu="yes" supports_event_based_sampling="yes"> | 2 | <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cnt" per_cpu="yes" supports_event_based_sampling="yes"> |
| 3 | <event counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> | 3 | <event counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> |
| 4 | <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> | 4 | <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/> |
| 5 | <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> | 5 | <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> |
| 6 | <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> | 6 | <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> |
| @@ -30,7 +30,7 @@ | |||
| 30 | <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/> | 30 | <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/> |
| 31 | <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/> | 31 | <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/> |
| 32 | <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/> | 32 | <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/> |
| 33 | <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/> | 33 | <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description="ETM - ETM Ext Out[0]"/> |
| 34 | <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/> | 34 | <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description="ETM - ETM Ext Out[1]"/> |
| 35 | <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/> | 35 | <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/> |
| 36 | </category> | 36 | </category> |