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Diffstat (limited to 'omap5/sgx_src/eurasia_km/services4/srvkm/hwdefs/sgx543defs.h')
| -rw-r--r-- | omap5/sgx_src/eurasia_km/services4/srvkm/hwdefs/sgx543defs.h | 1487 |
1 files changed, 0 insertions, 1487 deletions
diff --git a/omap5/sgx_src/eurasia_km/services4/srvkm/hwdefs/sgx543defs.h b/omap5/sgx_src/eurasia_km/services4/srvkm/hwdefs/sgx543defs.h deleted file mode 100644 index 0d3568d..0000000 --- a/omap5/sgx_src/eurasia_km/services4/srvkm/hwdefs/sgx543defs.h +++ /dev/null | |||
| @@ -1,1487 +0,0 @@ | |||
| 1 | /*************************************************************************/ /*! | ||
| 2 | @Title Hardware defs for SGX543. | ||
| 3 | @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved | ||
| 4 | @License Dual MIT/GPLv2 | ||
| 5 | |||
| 6 | The contents of this file are subject to the MIT license as set out below. | ||
| 7 | |||
| 8 | Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| 9 | of this software and associated documentation files (the "Software"), to deal | ||
| 10 | in the Software without restriction, including without limitation the rights | ||
| 11 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| 12 | copies of the Software, and to permit persons to whom the Software is | ||
| 13 | furnished to do so, subject to the following conditions: | ||
| 14 | |||
| 15 | The above copyright notice and this permission notice shall be included in | ||
| 16 | all copies or substantial portions of the Software. | ||
| 17 | |||
| 18 | Alternatively, the contents of this file may be used under the terms of | ||
| 19 | the GNU General Public License Version 2 ("GPL") in which case the provisions | ||
| 20 | of GPL are applicable instead of those above. | ||
| 21 | |||
| 22 | If you wish to allow use of your version of this file only under the terms of | ||
| 23 | GPL, and not to allow others to use your version of this file under the terms | ||
| 24 | of the MIT license, indicate your decision by deleting the provisions above | ||
| 25 | and replace them with the notice and other provisions required by GPL as set | ||
| 26 | out in the file called "GPL-COPYING" included in this distribution. If you do | ||
| 27 | not delete the provisions above, a recipient may use your version of this file | ||
| 28 | under the terms of either the MIT license or GPL. | ||
| 29 | |||
| 30 | This License is also included in this distribution in the file called | ||
| 31 | "MIT-COPYING". | ||
| 32 | |||
| 33 | EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS | ||
| 34 | PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING | ||
| 35 | BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR | ||
| 36 | PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR | ||
| 37 | COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER | ||
| 38 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
| 39 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
| 40 | */ /**************************************************************************/ | ||
| 41 | |||
| 42 | #ifndef _SGX543DEFS_KM_H_ | ||
| 43 | #define _SGX543DEFS_KM_H_ | ||
| 44 | |||
| 45 | /* Register EUR_CR_CLKGATECTL */ | ||
| 46 | #define EUR_CR_CLKGATECTL 0x0000 | ||
| 47 | #define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U | ||
| 48 | #define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0 | ||
| 49 | #define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0 | ||
| 50 | #define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU | ||
| 51 | #define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2 | ||
| 52 | #define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0 | ||
| 53 | #define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U | ||
| 54 | #define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4 | ||
| 55 | #define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0 | ||
| 56 | #define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U | ||
| 57 | #define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6 | ||
| 58 | #define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0 | ||
| 59 | #define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U | ||
| 60 | #define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8 | ||
| 61 | #define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0 | ||
| 62 | #define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U | ||
| 63 | #define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10 | ||
| 64 | #define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0 | ||
| 65 | #define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U | ||
| 66 | #define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12 | ||
| 67 | #define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0 | ||
| 68 | #define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U | ||
| 69 | #define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14 | ||
| 70 | #define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0 | ||
| 71 | #define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U | ||
| 72 | #define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16 | ||
| 73 | #define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0 | ||
| 74 | #define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U | ||
| 75 | #define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 | ||
| 76 | #define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0 | ||
| 77 | #define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U | ||
| 78 | #define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20 | ||
| 79 | #define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0 | ||
| 80 | #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U | ||
| 81 | #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 | ||
| 82 | #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0 | ||
| 83 | #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U | ||
| 84 | #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28 | ||
| 85 | #define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0 | ||
| 86 | /* Register EUR_CR_CLKGATECTL2 */ | ||
| 87 | #define EUR_CR_CLKGATECTL2 0x0004 | ||
| 88 | #define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U | ||
| 89 | #define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0 | ||
| 90 | #define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0 | ||
| 91 | #define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU | ||
| 92 | #define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2 | ||
| 93 | #define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0 | ||
| 94 | #define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U | ||
| 95 | #define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4 | ||
| 96 | #define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0 | ||
| 97 | #define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U | ||
| 98 | #define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6 | ||
| 99 | #define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0 | ||
| 100 | #define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U | ||
| 101 | #define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8 | ||
| 102 | #define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0 | ||
| 103 | #define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U | ||
| 104 | #define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10 | ||
| 105 | #define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0 | ||
| 106 | #define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U | ||
| 107 | #define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14 | ||
| 108 | #define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0 | ||
| 109 | #define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U | ||
| 110 | #define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16 | ||
| 111 | #define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0 | ||
| 112 | #define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U | ||
| 113 | #define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18 | ||
| 114 | #define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0 | ||
| 115 | #define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U | ||
| 116 | #define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22 | ||
| 117 | #define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0 | ||
| 118 | #define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U | ||
| 119 | #define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24 | ||
| 120 | #define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0 | ||
| 121 | #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U | ||
| 122 | #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26 | ||
| 123 | #define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0 | ||
| 124 | /* Register EUR_CR_CLKGATESTATUS */ | ||
| 125 | #define EUR_CR_CLKGATESTATUS 0x0008 | ||
| 126 | #define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U | ||
| 127 | #define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0 | ||
| 128 | #define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0 | ||
| 129 | #define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U | ||
| 130 | #define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1 | ||
| 131 | #define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0 | ||
| 132 | #define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U | ||
| 133 | #define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2 | ||
| 134 | #define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0 | ||
| 135 | #define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U | ||
| 136 | #define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3 | ||
| 137 | #define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0 | ||
| 138 | #define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U | ||
| 139 | #define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4 | ||
| 140 | #define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0 | ||
| 141 | #define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U | ||
| 142 | #define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5 | ||
| 143 | #define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0 | ||
| 144 | #define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U | ||
| 145 | #define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6 | ||
| 146 | #define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0 | ||
| 147 | #define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U | ||
| 148 | #define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7 | ||
| 149 | #define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0 | ||
| 150 | #define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U | ||
| 151 | #define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8 | ||
| 152 | #define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0 | ||
| 153 | #define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U | ||
| 154 | #define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9 | ||
| 155 | #define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0 | ||
| 156 | #define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U | ||
| 157 | #define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10 | ||
| 158 | #define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0 | ||
| 159 | #define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U | ||
| 160 | #define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11 | ||
| 161 | #define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0 | ||
| 162 | #define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U | ||
| 163 | #define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12 | ||
| 164 | #define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0 | ||
| 165 | #define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U | ||
| 166 | #define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13 | ||
| 167 | #define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0 | ||
| 168 | #define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U | ||
| 169 | #define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15 | ||
| 170 | #define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0 | ||
| 171 | #define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U | ||
| 172 | #define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16 | ||
| 173 | #define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0 | ||
| 174 | #define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U | ||
| 175 | #define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17 | ||
| 176 | #define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0 | ||
| 177 | #define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U | ||
| 178 | #define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19 | ||
| 179 | #define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0 | ||
| 180 | #define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U | ||
| 181 | #define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20 | ||
| 182 | #define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0 | ||
| 183 | #define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U | ||
| 184 | #define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21 | ||
| 185 | #define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0 | ||
| 186 | #define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U | ||
| 187 | #define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22 | ||
| 188 | #define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0 | ||
| 189 | #define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U | ||
| 190 | #define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23 | ||
| 191 | #define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0 | ||
| 192 | #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U | ||
| 193 | #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24 | ||
| 194 | #define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0 | ||
| 195 | /* Register EUR_CR_CLKGATECTLOVR */ | ||
| 196 | #define EUR_CR_CLKGATECTLOVR 0x000C | ||
| 197 | #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U | ||
| 198 | #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 | ||
| 199 | #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0 | ||
| 200 | #define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU | ||
| 201 | #define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2 | ||
| 202 | #define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0 | ||
| 203 | #define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U | ||
| 204 | #define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4 | ||
| 205 | #define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0 | ||
| 206 | #define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U | ||
| 207 | #define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6 | ||
| 208 | #define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0 | ||
| 209 | #define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U | ||
| 210 | #define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8 | ||
| 211 | #define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0 | ||
| 212 | #define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U | ||
| 213 | #define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10 | ||
| 214 | #define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0 | ||
| 215 | #define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U | ||
| 216 | #define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12 | ||
| 217 | #define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0 | ||
| 218 | #define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U | ||
| 219 | #define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14 | ||
| 220 | #define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0 | ||
| 221 | #define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U | ||
| 222 | #define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16 | ||
| 223 | #define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0 | ||
| 224 | #define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U | ||
| 225 | #define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 | ||
| 226 | #define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0 | ||
| 227 | #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U | ||
| 228 | #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20 | ||
| 229 | #define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0 | ||
| 230 | /* Register EUR_CR_POWER */ | ||
| 231 | #define EUR_CR_POWER 0x001C | ||
| 232 | #define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U | ||
| 233 | #define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 | ||
| 234 | #define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0 | ||
| 235 | /* Register EUR_CR_CORE_ID */ | ||
| 236 | #define EUR_CR_CORE_ID 0x0020 | ||
| 237 | #define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U | ||
| 238 | #define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0 | ||
| 239 | #define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0 | ||
| 240 | #define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U | ||
| 241 | #define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1 | ||
| 242 | #define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0 | ||
| 243 | #define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU | ||
| 244 | #define EUR_CR_CORE_ID_CONFIG_SHIFT 2 | ||
| 245 | #define EUR_CR_CORE_ID_CONFIG_SIGNED 0 | ||
| 246 | #define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U | ||
| 247 | #define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8 | ||
| 248 | #define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0 | ||
| 249 | #define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U | ||
| 250 | #define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12 | ||
| 251 | #define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0 | ||
| 252 | #define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U | ||
| 253 | #define EUR_CR_CORE_ID_ID_SHIFT 16 | ||
| 254 | #define EUR_CR_CORE_ID_ID_SIGNED 0 | ||
| 255 | /* Register EUR_CR_CORE_REVISION */ | ||
| 256 | #define EUR_CR_CORE_REVISION 0x0024 | ||
| 257 | #define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU | ||
| 258 | #define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0 | ||
| 259 | #define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0 | ||
| 260 | #define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U | ||
| 261 | #define EUR_CR_CORE_REVISION_MINOR_SHIFT 8 | ||
| 262 | #define EUR_CR_CORE_REVISION_MINOR_SIGNED 0 | ||
| 263 | #define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U | ||
| 264 | #define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16 | ||
| 265 | #define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0 | ||
| 266 | #define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U | ||
| 267 | #define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24 | ||
| 268 | #define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0 | ||
| 269 | /* Register EUR_CR_DESIGNER_REV_FIELD1 */ | ||
| 270 | #define EUR_CR_DESIGNER_REV_FIELD1 0x0028 | ||
| 271 | #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU | ||
| 272 | #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0 | ||
| 273 | #define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0 | ||
| 274 | /* Register EUR_CR_DESIGNER_REV_FIELD2 */ | ||
| 275 | #define EUR_CR_DESIGNER_REV_FIELD2 0x002C | ||
| 276 | #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU | ||
| 277 | #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0 | ||
| 278 | #define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0 | ||
| 279 | /* Register EUR_CR_SOFT_RESET */ | ||
| 280 | #define EUR_CR_SOFT_RESET 0x0080 | ||
| 281 | #define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U | ||
| 282 | #define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 | ||
| 283 | #define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0 | ||
| 284 | #define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U | ||
| 285 | #define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1 | ||
| 286 | #define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0 | ||
| 287 | #define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U | ||
| 288 | #define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 | ||
| 289 | #define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0 | ||
| 290 | #define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U | ||
| 291 | #define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3 | ||
| 292 | #define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0 | ||
| 293 | #define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U | ||
| 294 | #define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4 | ||
| 295 | #define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0 | ||
| 296 | #define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U | ||
| 297 | #define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5 | ||
| 298 | #define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0 | ||
| 299 | #define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U | ||
| 300 | #define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6 | ||
| 301 | #define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0 | ||
| 302 | #define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U | ||
| 303 | #define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7 | ||
| 304 | #define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0 | ||
| 305 | #define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U | ||
| 306 | #define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8 | ||
| 307 | #define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0 | ||
| 308 | #define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U | ||
| 309 | #define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9 | ||
| 310 | #define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0 | ||
| 311 | #define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U | ||
| 312 | #define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10 | ||
| 313 | #define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0 | ||
| 314 | #define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U | ||
| 315 | #define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11 | ||
| 316 | #define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0 | ||
| 317 | #define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U | ||
| 318 | #define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13 | ||
| 319 | #define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0 | ||
| 320 | #define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U | ||
| 321 | #define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14 | ||
| 322 | #define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0 | ||
| 323 | #define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U | ||
| 324 | #define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15 | ||
| 325 | #define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0 | ||
| 326 | #define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U | ||
| 327 | #define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16 | ||
| 328 | #define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0 | ||
| 329 | #define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U | ||
| 330 | #define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17 | ||
| 331 | #define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0 | ||
| 332 | #define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U | ||
| 333 | #define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18 | ||
| 334 | #define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0 | ||
| 335 | #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U | ||
| 336 | #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19 | ||
| 337 | #define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0 | ||
| 338 | /* Register EUR_CR_EVENT_HOST_ENABLE2 */ | ||
| 339 | #define EUR_CR_EVENT_HOST_ENABLE2 0x0110 | ||
| 340 | #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U | ||
| 341 | #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 | ||
| 342 | #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 | ||
| 343 | #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U | ||
| 344 | #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 | ||
| 345 | #define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 | ||
| 346 | #define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U | ||
| 347 | #define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9 | ||
| 348 | #define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0 | ||
| 349 | #define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U | ||
| 350 | #define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 | ||
| 351 | #define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 | ||
| 352 | #define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U | ||
| 353 | #define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7 | ||
| 354 | #define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0 | ||
| 355 | #define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U | ||
| 356 | #define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6 | ||
| 357 | #define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0 | ||
| 358 | #define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U | ||
| 359 | #define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 | ||
| 360 | #define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 | ||
| 361 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U | ||
| 362 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 | ||
| 363 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0 | ||
| 364 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U | ||
| 365 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 | ||
| 366 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0 | ||
| 367 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U | ||
| 368 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 | ||
| 369 | #define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0 | ||
| 370 | #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U | ||
| 371 | #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 | ||
| 372 | #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0 | ||
| 373 | #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U | ||
| 374 | #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 | ||
| 375 | #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0 | ||
| 376 | /* Register EUR_CR_EVENT_HOST_CLEAR2 */ | ||
| 377 | #define EUR_CR_EVENT_HOST_CLEAR2 0x0114 | ||
| 378 | #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U | ||
| 379 | #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 | ||
| 380 | #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 | ||
| 381 | #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U | ||
| 382 | #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 | ||
| 383 | #define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 | ||
| 384 | #define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U | ||
| 385 | #define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9 | ||
| 386 | #define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0 | ||
| 387 | #define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U | ||
| 388 | #define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 | ||
| 389 | #define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 | ||
| 390 | #define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U | ||
| 391 | #define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7 | ||
| 392 | #define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0 | ||
| 393 | #define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U | ||
| 394 | #define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6 | ||
| 395 | #define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0 | ||
| 396 | #define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U | ||
| 397 | #define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 | ||
| 398 | #define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 | ||
| 399 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U | ||
| 400 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 | ||
| 401 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0 | ||
| 402 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U | ||
| 403 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 | ||
| 404 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0 | ||
| 405 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U | ||
| 406 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 | ||
| 407 | #define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0 | ||
| 408 | #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U | ||
| 409 | #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 | ||
| 410 | #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0 | ||
| 411 | #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U | ||
| 412 | #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 | ||
| 413 | #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0 | ||
| 414 | /* Register EUR_CR_EVENT_STATUS2 */ | ||
| 415 | #define EUR_CR_EVENT_STATUS2 0x0118 | ||
| 416 | #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U | ||
| 417 | #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11 | ||
| 418 | #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0 | ||
| 419 | #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U | ||
| 420 | #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10 | ||
| 421 | #define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0 | ||
| 422 | #define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U | ||
| 423 | #define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9 | ||
| 424 | #define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0 | ||
| 425 | #define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U | ||
| 426 | #define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8 | ||
| 427 | #define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0 | ||
| 428 | #define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U | ||
| 429 | #define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7 | ||
| 430 | #define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0 | ||
| 431 | #define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U | ||
| 432 | #define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6 | ||
| 433 | #define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0 | ||
| 434 | #define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U | ||
| 435 | #define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5 | ||
| 436 | #define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0 | ||
| 437 | #define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U | ||
| 438 | #define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 | ||
| 439 | #define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0 | ||
| 440 | #define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U | ||
| 441 | #define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 | ||
| 442 | #define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0 | ||
| 443 | #define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U | ||
| 444 | #define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 | ||
| 445 | #define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0 | ||
| 446 | #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U | ||
| 447 | #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 | ||
| 448 | #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0 | ||
| 449 | #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U | ||
| 450 | #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 | ||
| 451 | #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0 | ||
| 452 | /* Register EUR_CR_EVENT_STATUS */ | ||
| 453 | #define EUR_CR_EVENT_STATUS 0x012C | ||
| 454 | #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U | ||
| 455 | #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 | ||
| 456 | #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0 | ||
| 457 | #define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U | ||
| 458 | #define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 | ||
| 459 | #define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0 | ||
| 460 | #define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U | ||
| 461 | #define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 | ||
| 462 | #define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0 | ||
| 463 | #define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U | ||
| 464 | #define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26 | ||
| 465 | #define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0 | ||
| 466 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U | ||
| 467 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 | ||
| 468 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 | ||
| 469 | #define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U | ||
| 470 | #define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24 | ||
| 471 | #define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0 | ||
| 472 | #define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U | ||
| 473 | #define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23 | ||
| 474 | #define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0 | ||
| 475 | #define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U | ||
| 476 | #define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22 | ||
| 477 | #define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0 | ||
| 478 | #define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U | ||
| 479 | #define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21 | ||
| 480 | #define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0 | ||
| 481 | #define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U | ||
| 482 | #define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20 | ||
| 483 | #define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0 | ||
| 484 | #define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U | ||
| 485 | #define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19 | ||
| 486 | #define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0 | ||
| 487 | #define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U | ||
| 488 | #define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18 | ||
| 489 | #define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0 | ||
| 490 | #define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U | ||
| 491 | #define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15 | ||
| 492 | #define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0 | ||
| 493 | #define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U | ||
| 494 | #define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14 | ||
| 495 | #define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0 | ||
| 496 | #define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U | ||
| 497 | #define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13 | ||
| 498 | #define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0 | ||
| 499 | #define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U | ||
| 500 | #define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12 | ||
| 501 | #define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0 | ||
| 502 | #define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U | ||
| 503 | #define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11 | ||
| 504 | #define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0 | ||
| 505 | #define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U | ||
| 506 | #define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10 | ||
| 507 | #define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0 | ||
| 508 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U | ||
| 509 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9 | ||
| 510 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0 | ||
| 511 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U | ||
| 512 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8 | ||
| 513 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0 | ||
| 514 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U | ||
| 515 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7 | ||
| 516 | #define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0 | ||
| 517 | #define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U | ||
| 518 | #define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6 | ||
| 519 | #define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0 | ||
| 520 | #define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U | ||
| 521 | #define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5 | ||
| 522 | #define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0 | ||
| 523 | #define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U | ||
| 524 | #define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4 | ||
| 525 | #define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0 | ||
| 526 | #define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U | ||
| 527 | #define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3 | ||
| 528 | #define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0 | ||
| 529 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U | ||
| 530 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 | ||
| 531 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 | ||
| 532 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U | ||
| 533 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1 | ||
| 534 | #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0 | ||
| 535 | #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U | ||
| 536 | #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0 | ||
| 537 | #define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0 | ||
| 538 | /* Register EUR_CR_EVENT_HOST_ENABLE */ | ||
| 539 | #define EUR_CR_EVENT_HOST_ENABLE 0x0130 | ||
| 540 | #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U | ||
| 541 | #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31 | ||
| 542 | #define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0 | ||
| 543 | #define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U | ||
| 544 | #define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 | ||
| 545 | #define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0 | ||
| 546 | #define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U | ||
| 547 | #define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 | ||
| 548 | #define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0 | ||
| 549 | #define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U | ||
| 550 | #define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26 | ||
| 551 | #define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0 | ||
| 552 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U | ||
| 553 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 | ||
| 554 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 | ||
| 555 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U | ||
| 556 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24 | ||
| 557 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0 | ||
| 558 | #define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U | ||
| 559 | #define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23 | ||
| 560 | #define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0 | ||
| 561 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U | ||
| 562 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22 | ||
| 563 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0 | ||
| 564 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U | ||
| 565 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21 | ||
| 566 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0 | ||
| 567 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U | ||
| 568 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20 | ||
| 569 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0 | ||
| 570 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U | ||
| 571 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19 | ||
| 572 | #define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0 | ||
| 573 | #define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U | ||
| 574 | #define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18 | ||
| 575 | #define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0 | ||
| 576 | #define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U | ||
| 577 | #define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15 | ||
| 578 | #define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0 | ||
| 579 | #define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U | ||
| 580 | #define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14 | ||
| 581 | #define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0 | ||
| 582 | #define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U | ||
| 583 | #define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13 | ||
| 584 | #define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0 | ||
| 585 | #define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U | ||
| 586 | #define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12 | ||
| 587 | #define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0 | ||
| 588 | #define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U | ||
| 589 | #define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11 | ||
| 590 | #define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0 | ||
| 591 | #define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U | ||
| 592 | #define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10 | ||
| 593 | #define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0 | ||
| 594 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U | ||
| 595 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9 | ||
| 596 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0 | ||
| 597 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U | ||
| 598 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8 | ||
| 599 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0 | ||
| 600 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U | ||
| 601 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7 | ||
| 602 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0 | ||
| 603 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U | ||
| 604 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6 | ||
| 605 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0 | ||
| 606 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U | ||
| 607 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5 | ||
| 608 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0 | ||
| 609 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U | ||
| 610 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4 | ||
| 611 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0 | ||
| 612 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U | ||
| 613 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3 | ||
| 614 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0 | ||
| 615 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U | ||
| 616 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 | ||
| 617 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 | ||
| 618 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U | ||
| 619 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1 | ||
| 620 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0 | ||
| 621 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U | ||
| 622 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0 | ||
| 623 | #define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0 | ||
| 624 | /* Register EUR_CR_EVENT_HOST_CLEAR */ | ||
| 625 | #define EUR_CR_EVENT_HOST_CLEAR 0x0134 | ||
| 626 | #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U | ||
| 627 | #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31 | ||
| 628 | #define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0 | ||
| 629 | #define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U | ||
| 630 | #define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 | ||
| 631 | #define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0 | ||
| 632 | #define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U | ||
| 633 | #define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 | ||
| 634 | #define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0 | ||
| 635 | #define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U | ||
| 636 | #define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26 | ||
| 637 | #define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0 | ||
| 638 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U | ||
| 639 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25 | ||
| 640 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0 | ||
| 641 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U | ||
| 642 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24 | ||
| 643 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0 | ||
| 644 | #define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U | ||
| 645 | #define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23 | ||
| 646 | #define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0 | ||
| 647 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U | ||
| 648 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22 | ||
| 649 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0 | ||
| 650 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U | ||
| 651 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21 | ||
| 652 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0 | ||
| 653 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U | ||
| 654 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20 | ||
| 655 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0 | ||
| 656 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U | ||
| 657 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19 | ||
| 658 | #define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0 | ||
| 659 | #define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U | ||
| 660 | #define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18 | ||
| 661 | #define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0 | ||
| 662 | #define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U | ||
| 663 | #define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15 | ||
| 664 | #define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0 | ||
| 665 | #define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U | ||
| 666 | #define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14 | ||
| 667 | #define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0 | ||
| 668 | #define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U | ||
| 669 | #define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13 | ||
| 670 | #define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0 | ||
| 671 | #define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U | ||
| 672 | #define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12 | ||
| 673 | #define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0 | ||
| 674 | #define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U | ||
| 675 | #define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11 | ||
| 676 | #define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0 | ||
| 677 | #define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U | ||
| 678 | #define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10 | ||
| 679 | #define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0 | ||
| 680 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U | ||
| 681 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9 | ||
| 682 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0 | ||
| 683 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U | ||
| 684 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8 | ||
| 685 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0 | ||
| 686 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U | ||
| 687 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7 | ||
| 688 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0 | ||
| 689 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U | ||
| 690 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6 | ||
| 691 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0 | ||
| 692 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U | ||
| 693 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5 | ||
| 694 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0 | ||
| 695 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U | ||
| 696 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4 | ||
| 697 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0 | ||
| 698 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U | ||
| 699 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3 | ||
| 700 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0 | ||
| 701 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U | ||
| 702 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2 | ||
| 703 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0 | ||
| 704 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U | ||
| 705 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 | ||
| 706 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0 | ||
| 707 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U | ||
| 708 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 | ||
| 709 | #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0 | ||
| 710 | /* Register EUR_CR_TIMER */ | ||
| 711 | #define EUR_CR_TIMER 0x0144 | ||
| 712 | #define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU | ||
| 713 | #define EUR_CR_TIMER_VALUE_SHIFT 0 | ||
| 714 | #define EUR_CR_TIMER_VALUE_SIGNED 0 | ||
| 715 | /* Register EUR_CR_EVENT_KICK1 */ | ||
| 716 | #define EUR_CR_EVENT_KICK1 0x0AB0 | ||
| 717 | #define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU | ||
| 718 | #define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 | ||
| 719 | #define EUR_CR_EVENT_KICK1_NOW_SIGNED 0 | ||
| 720 | /* Register EUR_CR_EVENT_KICK2 */ | ||
| 721 | #define EUR_CR_EVENT_KICK2 0x0AC0 | ||
| 722 | #define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U | ||
| 723 | #define EUR_CR_EVENT_KICK2_NOW_SHIFT 0 | ||
| 724 | #define EUR_CR_EVENT_KICK2_NOW_SIGNED 0 | ||
| 725 | /* Register EUR_CR_EVENT_KICKER */ | ||
| 726 | #define EUR_CR_EVENT_KICKER 0x0AC4 | ||
| 727 | #define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U | ||
| 728 | #define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 | ||
| 729 | #define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0 | ||
| 730 | /* Register EUR_CR_EVENT_KICK */ | ||
| 731 | #define EUR_CR_EVENT_KICK 0x0AC8 | ||
| 732 | #define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U | ||
| 733 | #define EUR_CR_EVENT_KICK_NOW_SHIFT 0 | ||
| 734 | #define EUR_CR_EVENT_KICK_NOW_SIGNED 0 | ||
| 735 | /* Register EUR_CR_EVENT_TIMER */ | ||
| 736 | #define EUR_CR_EVENT_TIMER 0x0ACC | ||
| 737 | #define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U | ||
| 738 | #define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24 | ||
| 739 | #define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0 | ||
| 740 | #define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU | ||
| 741 | #define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0 | ||
| 742 | #define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0 | ||
| 743 | /* Register EUR_CR_PDS_INV0 */ | ||
| 744 | #define EUR_CR_PDS_INV0 0x0AD0 | ||
| 745 | #define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U | ||
| 746 | #define EUR_CR_PDS_INV0_DSC_SHIFT 0 | ||
| 747 | #define EUR_CR_PDS_INV0_DSC_SIGNED 0 | ||
| 748 | /* Register EUR_CR_PDS_INV1 */ | ||
| 749 | #define EUR_CR_PDS_INV1 0x0AD4 | ||
| 750 | #define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U | ||
| 751 | #define EUR_CR_PDS_INV1_DSC_SHIFT 0 | ||
| 752 | #define EUR_CR_PDS_INV1_DSC_SIGNED 0 | ||
| 753 | /* Register EUR_CR_EVENT_KICK3 */ | ||
| 754 | #define EUR_CR_EVENT_KICK3 0x0AD8 | ||
| 755 | #define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U | ||
| 756 | #define EUR_CR_EVENT_KICK3_NOW_SHIFT 0 | ||
| 757 | #define EUR_CR_EVENT_KICK3_NOW_SIGNED 0 | ||
| 758 | /* Register EUR_CR_PDS_INV3 */ | ||
| 759 | #define EUR_CR_PDS_INV3 0x0ADC | ||
| 760 | #define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U | ||
| 761 | #define EUR_CR_PDS_INV3_DSC_SHIFT 0 | ||
| 762 | #define EUR_CR_PDS_INV3_DSC_SIGNED 0 | ||
| 763 | /* Register EUR_CR_PDS_INV_CSC */ | ||
| 764 | #define EUR_CR_PDS_INV_CSC 0x0AE0 | ||
| 765 | #define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U | ||
| 766 | #define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0 | ||
| 767 | #define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0 | ||
| 768 | /* Register EUR_CR_BIF_CTRL */ | ||
| 769 | #define EUR_CR_BIF_CTRL 0x0C00 | ||
| 770 | #define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U | ||
| 771 | #define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0 | ||
| 772 | #define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0 | ||
| 773 | #define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U | ||
| 774 | #define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1 | ||
| 775 | #define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0 | ||
| 776 | #define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U | ||
| 777 | #define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4 | ||
| 778 | #define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0 | ||
| 779 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U | ||
| 780 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 | ||
| 781 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0 | ||
| 782 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U | ||
| 783 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10 | ||
| 784 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0 | ||
| 785 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U | ||
| 786 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 | ||
| 787 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0 | ||
| 788 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U | ||
| 789 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13 | ||
| 790 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0 | ||
| 791 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U | ||
| 792 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 | ||
| 793 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0 | ||
| 794 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U | ||
| 795 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 | ||
| 796 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0 | ||
| 797 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U | ||
| 798 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16 | ||
| 799 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0 | ||
| 800 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U | ||
| 801 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17 | ||
| 802 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0 | ||
| 803 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U | ||
| 804 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18 | ||
| 805 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0 | ||
| 806 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U | ||
| 807 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19 | ||
| 808 | #define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0 | ||
| 809 | /* Register EUR_CR_BIF_INT_STAT */ | ||
| 810 | #define EUR_CR_BIF_INT_STAT 0x0C04 | ||
| 811 | #define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU | ||
| 812 | #define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0 | ||
| 813 | #define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0 | ||
| 814 | #define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U | ||
| 815 | #define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16 | ||
| 816 | #define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0 | ||
| 817 | #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U | ||
| 818 | #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19 | ||
| 819 | #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0 | ||
| 820 | /* Register EUR_CR_BIF_FAULT */ | ||
| 821 | #define EUR_CR_BIF_FAULT 0x0C08 | ||
| 822 | #define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU | ||
| 823 | #define EUR_CR_BIF_FAULT_CID_SHIFT 0 | ||
| 824 | #define EUR_CR_BIF_FAULT_CID_SIGNED 0 | ||
| 825 | #define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U | ||
| 826 | #define EUR_CR_BIF_FAULT_SB_SHIFT 4 | ||
| 827 | #define EUR_CR_BIF_FAULT_SB_SIGNED 0 | ||
| 828 | #define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U | ||
| 829 | #define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 | ||
| 830 | #define EUR_CR_BIF_FAULT_ADDR_SIGNED 0 | ||
| 831 | /* Register EUR_CR_BIF_TILE0 */ | ||
| 832 | #define EUR_CR_BIF_TILE0 0x0C0C | ||
| 833 | #define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 834 | #define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 | ||
| 835 | #define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0 | ||
| 836 | #define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 837 | #define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 | ||
| 838 | #define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0 | ||
| 839 | #define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U | ||
| 840 | #define EUR_CR_BIF_TILE0_CFG_SHIFT 24 | ||
| 841 | #define EUR_CR_BIF_TILE0_CFG_SIGNED 0 | ||
| 842 | /* Register EUR_CR_BIF_TILE1 */ | ||
| 843 | #define EUR_CR_BIF_TILE1 0x0C10 | ||
| 844 | #define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 845 | #define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 | ||
| 846 | #define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0 | ||
| 847 | #define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 848 | #define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 | ||
| 849 | #define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0 | ||
| 850 | #define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U | ||
| 851 | #define EUR_CR_BIF_TILE1_CFG_SHIFT 24 | ||
| 852 | #define EUR_CR_BIF_TILE1_CFG_SIGNED 0 | ||
| 853 | /* Register EUR_CR_BIF_TILE2 */ | ||
| 854 | #define EUR_CR_BIF_TILE2 0x0C14 | ||
| 855 | #define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 856 | #define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 | ||
| 857 | #define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0 | ||
| 858 | #define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 859 | #define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 | ||
| 860 | #define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0 | ||
| 861 | #define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U | ||
| 862 | #define EUR_CR_BIF_TILE2_CFG_SHIFT 24 | ||
| 863 | #define EUR_CR_BIF_TILE2_CFG_SIGNED 0 | ||
| 864 | /* Register EUR_CR_BIF_TILE3 */ | ||
| 865 | #define EUR_CR_BIF_TILE3 0x0C18 | ||
| 866 | #define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 867 | #define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 | ||
| 868 | #define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0 | ||
| 869 | #define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 870 | #define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 | ||
| 871 | #define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0 | ||
| 872 | #define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U | ||
| 873 | #define EUR_CR_BIF_TILE3_CFG_SHIFT 24 | ||
| 874 | #define EUR_CR_BIF_TILE3_CFG_SIGNED 0 | ||
| 875 | /* Register EUR_CR_BIF_TILE4 */ | ||
| 876 | #define EUR_CR_BIF_TILE4 0x0C1C | ||
| 877 | #define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 878 | #define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 | ||
| 879 | #define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0 | ||
| 880 | #define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 881 | #define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 | ||
| 882 | #define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0 | ||
| 883 | #define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U | ||
| 884 | #define EUR_CR_BIF_TILE4_CFG_SHIFT 24 | ||
| 885 | #define EUR_CR_BIF_TILE4_CFG_SIGNED 0 | ||
| 886 | /* Register EUR_CR_BIF_TILE5 */ | ||
| 887 | #define EUR_CR_BIF_TILE5 0x0C20 | ||
| 888 | #define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 889 | #define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 | ||
| 890 | #define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0 | ||
| 891 | #define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 892 | #define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 | ||
| 893 | #define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0 | ||
| 894 | #define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U | ||
| 895 | #define EUR_CR_BIF_TILE5_CFG_SHIFT 24 | ||
| 896 | #define EUR_CR_BIF_TILE5_CFG_SIGNED 0 | ||
| 897 | /* Register EUR_CR_BIF_TILE6 */ | ||
| 898 | #define EUR_CR_BIF_TILE6 0x0C24 | ||
| 899 | #define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 900 | #define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 | ||
| 901 | #define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0 | ||
| 902 | #define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 903 | #define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 | ||
| 904 | #define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0 | ||
| 905 | #define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U | ||
| 906 | #define EUR_CR_BIF_TILE6_CFG_SHIFT 24 | ||
| 907 | #define EUR_CR_BIF_TILE6_CFG_SIGNED 0 | ||
| 908 | /* Register EUR_CR_BIF_TILE7 */ | ||
| 909 | #define EUR_CR_BIF_TILE7 0x0C28 | ||
| 910 | #define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 911 | #define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 | ||
| 912 | #define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0 | ||
| 913 | #define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 914 | #define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 | ||
| 915 | #define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0 | ||
| 916 | #define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U | ||
| 917 | #define EUR_CR_BIF_TILE7_CFG_SHIFT 24 | ||
| 918 | #define EUR_CR_BIF_TILE7_CFG_SIGNED 0 | ||
| 919 | /* Register EUR_CR_BIF_TILE8 */ | ||
| 920 | #define EUR_CR_BIF_TILE8 0x0C2C | ||
| 921 | #define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 922 | #define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 | ||
| 923 | #define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0 | ||
| 924 | #define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 925 | #define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 | ||
| 926 | #define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0 | ||
| 927 | #define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U | ||
| 928 | #define EUR_CR_BIF_TILE8_CFG_SHIFT 24 | ||
| 929 | #define EUR_CR_BIF_TILE8_CFG_SIGNED 0 | ||
| 930 | /* Register EUR_CR_BIF_TILE9 */ | ||
| 931 | #define EUR_CR_BIF_TILE9 0x0C30 | ||
| 932 | #define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU | ||
| 933 | #define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 | ||
| 934 | #define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0 | ||
| 935 | #define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U | ||
| 936 | #define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 | ||
| 937 | #define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0 | ||
| 938 | #define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U | ||
| 939 | #define EUR_CR_BIF_TILE9_CFG_SHIFT 24 | ||
| 940 | #define EUR_CR_BIF_TILE9_CFG_SIGNED 0 | ||
| 941 | /* Register EUR_CR_BIF_CTRL_INVAL */ | ||
| 942 | #define EUR_CR_BIF_CTRL_INVAL 0x0C34 | ||
| 943 | #define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U | ||
| 944 | #define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2 | ||
| 945 | #define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0 | ||
| 946 | #define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U | ||
| 947 | #define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3 | ||
| 948 | #define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0 | ||
| 949 | /* Register EUR_CR_BIF_DIR_LIST_BASE1 */ | ||
| 950 | #define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 | ||
| 951 | #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U | ||
| 952 | #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 | ||
| 953 | #define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0 | ||
| 954 | /* Register EUR_CR_BIF_DIR_LIST_BASE2 */ | ||
| 955 | #define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C | ||
| 956 | #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U | ||
| 957 | #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 | ||
| 958 | #define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0 | ||
| 959 | /* Register EUR_CR_BIF_DIR_LIST_BASE3 */ | ||
| 960 | #define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 | ||
| 961 | #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U | ||
| 962 | #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 | ||
| 963 | #define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0 | ||
| 964 | /* Register EUR_CR_BIF_DIR_LIST_BASE4 */ | ||
| 965 | #define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 | ||
| 966 | #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U | ||
| 967 | #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 | ||
| 968 | #define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0 | ||
| 969 | /* Register EUR_CR_BIF_DIR_LIST_BASE5 */ | ||
| 970 | #define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 | ||
| 971 | #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U | ||
| 972 | #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 | ||
| 973 | #define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0 | ||
| 974 | /* Register EUR_CR_BIF_DIR_LIST_BASE6 */ | ||
| 975 | #define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C | ||
| 976 | #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U | ||
| 977 | #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 | ||
| 978 | #define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0 | ||
| 979 | /* Register EUR_CR_BIF_DIR_LIST_BASE7 */ | ||
| 980 | #define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 | ||
| 981 | #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U | ||
| 982 | #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 | ||
| 983 | #define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0 | ||
| 984 | /* Register EUR_CR_BIF_BANK_SET */ | ||
| 985 | #define EUR_CR_BIF_BANK_SET 0x0C74 | ||
| 986 | #define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U | ||
| 987 | #define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0 | ||
| 988 | #define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0 | ||
| 989 | #define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU | ||
| 990 | #define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2 | ||
| 991 | #define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0 | ||
| 992 | #define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U | ||
| 993 | #define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4 | ||
| 994 | #define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0 | ||
| 995 | #define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U | ||
| 996 | #define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6 | ||
| 997 | #define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0 | ||
| 998 | #define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U | ||
| 999 | #define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8 | ||
| 1000 | #define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0 | ||
| 1001 | #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U | ||
| 1002 | #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9 | ||
| 1003 | #define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0 | ||
| 1004 | /* Register EUR_CR_BIF_BANK0 */ | ||
| 1005 | #define EUR_CR_BIF_BANK0 0x0C78 | ||
| 1006 | #define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU | ||
| 1007 | #define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 | ||
| 1008 | #define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0 | ||
| 1009 | #define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U | ||
| 1010 | #define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 | ||
| 1011 | #define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0 | ||
| 1012 | #define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U | ||
| 1013 | #define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 | ||
| 1014 | #define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0 | ||
| 1015 | #define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U | ||
| 1016 | #define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16 | ||
| 1017 | #define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0 | ||
| 1018 | /* Register EUR_CR_BIF_BANK1 */ | ||
| 1019 | #define EUR_CR_BIF_BANK1 0x0C7C | ||
| 1020 | #define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU | ||
| 1021 | #define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 | ||
| 1022 | #define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0 | ||
| 1023 | #define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U | ||
| 1024 | #define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 | ||
| 1025 | #define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0 | ||
| 1026 | #define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U | ||
| 1027 | #define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 | ||
| 1028 | #define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0 | ||
| 1029 | /* Register EUR_CR_BIF_DIR_LIST_BASE0 */ | ||
| 1030 | #define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 | ||
| 1031 | #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U | ||
| 1032 | #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 | ||
| 1033 | #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0 | ||
| 1034 | /* Register EUR_CR_BIF_TA_REQ_BASE */ | ||
| 1035 | #define EUR_CR_BIF_TA_REQ_BASE 0x0C90 | ||
| 1036 | #define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U | ||
| 1037 | #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 | ||
| 1038 | #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0 | ||
| 1039 | /* Register EUR_CR_BIF_MEM_REQ_STAT */ | ||
| 1040 | #define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 | ||
| 1041 | #define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU | ||
| 1042 | #define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 | ||
| 1043 | #define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0 | ||
| 1044 | /* Register EUR_CR_BIF_3D_REQ_BASE */ | ||
| 1045 | #define EUR_CR_BIF_3D_REQ_BASE 0x0CAC | ||
| 1046 | #define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U | ||
| 1047 | #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 | ||
| 1048 | #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0 | ||
| 1049 | /* Register EUR_CR_BIF_ZLS_REQ_BASE */ | ||
| 1050 | #define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 | ||
| 1051 | #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U | ||
| 1052 | #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 | ||
| 1053 | #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0 | ||
| 1054 | /* Register EUR_CR_BIF_BANK_STATUS */ | ||
| 1055 | #define EUR_CR_BIF_BANK_STATUS 0x0CB4 | ||
| 1056 | #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U | ||
| 1057 | #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 | ||
| 1058 | #define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0 | ||
| 1059 | #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U | ||
| 1060 | #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 | ||
| 1061 | #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 | ||
| 1062 | /* Register EUR_CR_BIF_MMU_CTRL */ | ||
| 1063 | #define EUR_CR_BIF_MMU_CTRL 0x0CD0 | ||
| 1064 | #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U | ||
| 1065 | #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 | ||
| 1066 | #define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0 | ||
| 1067 | #define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U | ||
| 1068 | #define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1 | ||
| 1069 | #define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0 | ||
| 1070 | #define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U | ||
| 1071 | #define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3 | ||
| 1072 | #define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0 | ||
| 1073 | #define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U | ||
| 1074 | #define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 | ||
| 1075 | #define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 | ||
| 1076 | #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U | ||
| 1077 | #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5 | ||
| 1078 | #define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0 | ||
| 1079 | /* Register EUR_CR_2D_BLIT_STATUS */ | ||
| 1080 | #define EUR_CR_2D_BLIT_STATUS 0x0E04 | ||
| 1081 | #define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU | ||
| 1082 | #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 | ||
| 1083 | #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0 | ||
| 1084 | #define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U | ||
| 1085 | #define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 | ||
| 1086 | #define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0 | ||
| 1087 | /* Register EUR_CR_2D_VIRTUAL_FIFO_0 */ | ||
| 1088 | #define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 | ||
| 1089 | #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U | ||
| 1090 | #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 | ||
| 1091 | #define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0 | ||
| 1092 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU | ||
| 1093 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 | ||
| 1094 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0 | ||
| 1095 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U | ||
| 1096 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 | ||
| 1097 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0 | ||
| 1098 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U | ||
| 1099 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 | ||
| 1100 | #define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0 | ||
| 1101 | /* Register EUR_CR_2D_VIRTUAL_FIFO_1 */ | ||
| 1102 | #define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 | ||
| 1103 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU | ||
| 1104 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 | ||
| 1105 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0 | ||
| 1106 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U | ||
| 1107 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 | ||
| 1108 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0 | ||
| 1109 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U | ||
| 1110 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 | ||
| 1111 | #define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0 | ||
| 1112 | /* Register EUR_CR_BREAKPOINT0_START */ | ||
| 1113 | #define EUR_CR_BREAKPOINT0_START 0x0F44 | ||
| 1114 | #define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1115 | #define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4 | ||
| 1116 | #define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0 | ||
| 1117 | /* Register EUR_CR_BREAKPOINT0_END */ | ||
| 1118 | #define EUR_CR_BREAKPOINT0_END 0x0F48 | ||
| 1119 | #define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1120 | #define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4 | ||
| 1121 | #define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0 | ||
| 1122 | /* Register EUR_CR_BREAKPOINT0 */ | ||
| 1123 | #define EUR_CR_BREAKPOINT0 0x0F4C | ||
| 1124 | #define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U | ||
| 1125 | #define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3 | ||
| 1126 | #define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0 | ||
| 1127 | #define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U | ||
| 1128 | #define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2 | ||
| 1129 | #define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0 | ||
| 1130 | #define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U | ||
| 1131 | #define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1 | ||
| 1132 | #define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0 | ||
| 1133 | #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U | ||
| 1134 | #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0 | ||
| 1135 | #define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0 | ||
| 1136 | /* Register EUR_CR_BREAKPOINT1_START */ | ||
| 1137 | #define EUR_CR_BREAKPOINT1_START 0x0F50 | ||
| 1138 | #define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1139 | #define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4 | ||
| 1140 | #define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0 | ||
| 1141 | /* Register EUR_CR_BREAKPOINT1_END */ | ||
| 1142 | #define EUR_CR_BREAKPOINT1_END 0x0F54 | ||
| 1143 | #define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1144 | #define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4 | ||
| 1145 | #define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0 | ||
| 1146 | /* Register EUR_CR_BREAKPOINT1 */ | ||
| 1147 | #define EUR_CR_BREAKPOINT1 0x0F58 | ||
| 1148 | #define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U | ||
| 1149 | #define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3 | ||
| 1150 | #define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0 | ||
| 1151 | #define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U | ||
| 1152 | #define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2 | ||
| 1153 | #define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0 | ||
| 1154 | #define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U | ||
| 1155 | #define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1 | ||
| 1156 | #define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0 | ||
| 1157 | #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U | ||
| 1158 | #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0 | ||
| 1159 | #define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0 | ||
| 1160 | /* Register EUR_CR_BREAKPOINT2_START */ | ||
| 1161 | #define EUR_CR_BREAKPOINT2_START 0x0F5C | ||
| 1162 | #define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1163 | #define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4 | ||
| 1164 | #define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0 | ||
| 1165 | /* Register EUR_CR_BREAKPOINT2_END */ | ||
| 1166 | #define EUR_CR_BREAKPOINT2_END 0x0F60 | ||
| 1167 | #define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1168 | #define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4 | ||
| 1169 | #define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0 | ||
| 1170 | /* Register EUR_CR_BREAKPOINT2 */ | ||
| 1171 | #define EUR_CR_BREAKPOINT2 0x0F64 | ||
| 1172 | #define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U | ||
| 1173 | #define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3 | ||
| 1174 | #define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0 | ||
| 1175 | #define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U | ||
| 1176 | #define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2 | ||
| 1177 | #define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0 | ||
| 1178 | #define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U | ||
| 1179 | #define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1 | ||
| 1180 | #define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0 | ||
| 1181 | #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U | ||
| 1182 | #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0 | ||
| 1183 | #define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0 | ||
| 1184 | /* Register EUR_CR_BREAKPOINT3_START */ | ||
| 1185 | #define EUR_CR_BREAKPOINT3_START 0x0F68 | ||
| 1186 | #define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1187 | #define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4 | ||
| 1188 | #define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0 | ||
| 1189 | /* Register EUR_CR_BREAKPOINT3_END */ | ||
| 1190 | #define EUR_CR_BREAKPOINT3_END 0x0F6C | ||
| 1191 | #define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1192 | #define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4 | ||
| 1193 | #define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0 | ||
| 1194 | /* Register EUR_CR_BREAKPOINT3 */ | ||
| 1195 | #define EUR_CR_BREAKPOINT3 0x0F70 | ||
| 1196 | #define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U | ||
| 1197 | #define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3 | ||
| 1198 | #define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0 | ||
| 1199 | #define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U | ||
| 1200 | #define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2 | ||
| 1201 | #define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0 | ||
| 1202 | #define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U | ||
| 1203 | #define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1 | ||
| 1204 | #define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0 | ||
| 1205 | #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U | ||
| 1206 | #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0 | ||
| 1207 | #define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0 | ||
| 1208 | /* Register EUR_CR_BREAKPOINT_READ */ | ||
| 1209 | #define EUR_CR_BREAKPOINT_READ 0x0F74 | ||
| 1210 | #define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1211 | #define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 | ||
| 1212 | #define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 | ||
| 1213 | /* Register EUR_CR_PARTITION_BREAKPOINT_TRAP */ | ||
| 1214 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78 | ||
| 1215 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U | ||
| 1216 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 | ||
| 1217 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 | ||
| 1218 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U | ||
| 1219 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 | ||
| 1220 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 | ||
| 1221 | /* Register EUR_CR_PARTITION_BREAKPOINT */ | ||
| 1222 | #define EUR_CR_PARTITION_BREAKPOINT 0x0F7C | ||
| 1223 | #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U | ||
| 1224 | #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6 | ||
| 1225 | #define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SIGNED 0 | ||
| 1226 | #define EUR_CR_PARTITION_BREAKPOINT_ID_MASK 0x00000030U | ||
| 1227 | #define EUR_CR_PARTITION_BREAKPOINT_ID_SHIFT 4 | ||
| 1228 | #define EUR_CR_PARTITION_BREAKPOINT_ID_SIGNED 0 | ||
| 1229 | #define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_MASK 0x00000008U | ||
| 1230 | #define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SHIFT 3 | ||
| 1231 | #define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SIGNED 0 | ||
| 1232 | #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U | ||
| 1233 | #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2 | ||
| 1234 | #define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0 | ||
| 1235 | /* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 */ | ||
| 1236 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80 | ||
| 1237 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1238 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 | ||
| 1239 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 | ||
| 1240 | /* Register EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 */ | ||
| 1241 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84 | ||
| 1242 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U | ||
| 1243 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 | ||
| 1244 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 | ||
| 1245 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U | ||
| 1246 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 | ||
| 1247 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 | ||
| 1248 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U | ||
| 1249 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 | ||
| 1250 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 | ||
| 1251 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U | ||
| 1252 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 | ||
| 1253 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 | ||
| 1254 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U | ||
| 1255 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 | ||
| 1256 | #define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 | ||
| 1257 | /* Register EUR_CR_USE_CODE_BASE_0 */ | ||
| 1258 | #define EUR_CR_USE_CODE_BASE_0 0x0A0C | ||
| 1259 | #define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU | ||
| 1260 | #define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 | ||
| 1261 | #define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0 | ||
| 1262 | #define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U | ||
| 1263 | #define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26 | ||
| 1264 | #define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0 | ||
| 1265 | /* Register EUR_CR_USE_CODE_BASE_1 */ | ||
| 1266 | #define EUR_CR_USE_CODE_BASE_1 0x0A10 | ||
| 1267 | #define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU | ||
| 1268 | #define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 | ||
| 1269 | #define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0 | ||
| 1270 | #define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U | ||
| 1271 | #define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26 | ||
| 1272 | #define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0 | ||
| 1273 | /* Register EUR_CR_USE_CODE_BASE_2 */ | ||
| 1274 | #define EUR_CR_USE_CODE_BASE_2 0x0A14 | ||
| 1275 | #define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU | ||
| 1276 | #define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 | ||
| 1277 | #define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0 | ||
| 1278 | #define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U | ||
| 1279 | #define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26 | ||
| 1280 | #define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0 | ||
| 1281 | /* Register EUR_CR_USE_CODE_BASE_3 */ | ||
| 1282 | #define EUR_CR_USE_CODE_BASE_3 0x0A18 | ||
| 1283 | #define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU | ||
| 1284 | #define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 | ||
| 1285 | #define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0 | ||
| 1286 | #define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U | ||
| 1287 | #define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26 | ||
| 1288 | #define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0 | ||
| 1289 | /* Register EUR_CR_USE_CODE_BASE_4 */ | ||
| 1290 | #define EUR_CR_USE_CODE_BASE_4 0x0A1C | ||
| 1291 | #define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU | ||
| 1292 | #define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 | ||
| 1293 | #define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0 | ||
| 1294 | #define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U | ||
| 1295 | #define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26 | ||
| 1296 | #define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0 | ||
| 1297 | /* Register EUR_CR_USE_CODE_BASE_5 */ | ||
| 1298 | #define EUR_CR_USE_CODE_BASE_5 0x0A20 | ||
| 1299 | #define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU | ||
| 1300 | #define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 | ||
| 1301 | #define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0 | ||
| 1302 | #define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U | ||
| 1303 | #define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26 | ||
| 1304 | #define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0 | ||
| 1305 | /* Register EUR_CR_USE_CODE_BASE_6 */ | ||
| 1306 | #define EUR_CR_USE_CODE_BASE_6 0x0A24 | ||
| 1307 | #define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU | ||
| 1308 | #define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 | ||
| 1309 | #define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0 | ||
| 1310 | #define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U | ||
| 1311 | #define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26 | ||
| 1312 | #define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0 | ||
| 1313 | /* Register EUR_CR_USE_CODE_BASE_7 */ | ||
| 1314 | #define EUR_CR_USE_CODE_BASE_7 0x0A28 | ||
| 1315 | #define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU | ||
| 1316 | #define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 | ||
| 1317 | #define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0 | ||
| 1318 | #define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U | ||
| 1319 | #define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26 | ||
| 1320 | #define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0 | ||
| 1321 | /* Register EUR_CR_USE_CODE_BASE_8 */ | ||
| 1322 | #define EUR_CR_USE_CODE_BASE_8 0x0A2C | ||
| 1323 | #define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU | ||
| 1324 | #define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 | ||
| 1325 | #define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0 | ||
| 1326 | #define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U | ||
| 1327 | #define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26 | ||
| 1328 | #define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0 | ||
| 1329 | /* Register EUR_CR_USE_CODE_BASE_9 */ | ||
| 1330 | #define EUR_CR_USE_CODE_BASE_9 0x0A30 | ||
| 1331 | #define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU | ||
| 1332 | #define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 | ||
| 1333 | #define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0 | ||
| 1334 | #define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U | ||
| 1335 | #define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26 | ||
| 1336 | #define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0 | ||
| 1337 | /* Register EUR_CR_USE_CODE_BASE_10 */ | ||
| 1338 | #define EUR_CR_USE_CODE_BASE_10 0x0A34 | ||
| 1339 | #define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU | ||
| 1340 | #define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 | ||
| 1341 | #define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0 | ||
| 1342 | #define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U | ||
| 1343 | #define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26 | ||
| 1344 | #define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0 | ||
| 1345 | /* Register EUR_CR_USE_CODE_BASE_11 */ | ||
| 1346 | #define EUR_CR_USE_CODE_BASE_11 0x0A38 | ||
| 1347 | #define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU | ||
| 1348 | #define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 | ||
| 1349 | #define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0 | ||
| 1350 | #define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U | ||
| 1351 | #define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26 | ||
| 1352 | #define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0 | ||
| 1353 | /* Register EUR_CR_USE_CODE_BASE_12 */ | ||
| 1354 | #define EUR_CR_USE_CODE_BASE_12 0x0A3C | ||
| 1355 | #define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU | ||
| 1356 | #define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 | ||
| 1357 | #define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0 | ||
| 1358 | #define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U | ||
| 1359 | #define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26 | ||
| 1360 | #define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0 | ||
| 1361 | /* Register EUR_CR_USE_CODE_BASE_13 */ | ||
| 1362 | #define EUR_CR_USE_CODE_BASE_13 0x0A40 | ||
| 1363 | #define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU | ||
| 1364 | #define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 | ||
| 1365 | #define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0 | ||
| 1366 | #define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U | ||
| 1367 | #define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26 | ||
| 1368 | #define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0 | ||
| 1369 | /* Register EUR_CR_USE_CODE_BASE_14 */ | ||
| 1370 | #define EUR_CR_USE_CODE_BASE_14 0x0A44 | ||
| 1371 | #define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU | ||
| 1372 | #define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 | ||
| 1373 | #define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0 | ||
| 1374 | #define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U | ||
| 1375 | #define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26 | ||
| 1376 | #define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0 | ||
| 1377 | /* Register EUR_CR_USE_CODE_BASE_15 */ | ||
| 1378 | #define EUR_CR_USE_CODE_BASE_15 0x0A48 | ||
| 1379 | #define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU | ||
| 1380 | #define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 | ||
| 1381 | #define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0 | ||
| 1382 | #define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U | ||
| 1383 | #define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26 | ||
| 1384 | #define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0 | ||
| 1385 | /* Register EUR_CR_PIPE0_BREAKPOINT_TRAP */ | ||
| 1386 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88 | ||
| 1387 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U | ||
| 1388 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 | ||
| 1389 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 | ||
| 1390 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U | ||
| 1391 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 | ||
| 1392 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 | ||
| 1393 | /* Register EUR_CR_PIPE0_BREAKPOINT */ | ||
| 1394 | #define EUR_CR_PIPE0_BREAKPOINT 0x0F8C | ||
| 1395 | #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U | ||
| 1396 | #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6 | ||
| 1397 | #define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SIGNED 0 | ||
| 1398 | #define EUR_CR_PIPE0_BREAKPOINT_ID_MASK 0x00000030U | ||
| 1399 | #define EUR_CR_PIPE0_BREAKPOINT_ID_SHIFT 4 | ||
| 1400 | #define EUR_CR_PIPE0_BREAKPOINT_ID_SIGNED 0 | ||
| 1401 | #define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_MASK 0x00000008U | ||
| 1402 | #define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SHIFT 3 | ||
| 1403 | #define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SIGNED 0 | ||
| 1404 | #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U | ||
| 1405 | #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2 | ||
| 1406 | #define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0 | ||
| 1407 | /* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 */ | ||
| 1408 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90 | ||
| 1409 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1410 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 | ||
| 1411 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 | ||
| 1412 | /* Register EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 */ | ||
| 1413 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94 | ||
| 1414 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U | ||
| 1415 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 | ||
| 1416 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 | ||
| 1417 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U | ||
| 1418 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 | ||
| 1419 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 | ||
| 1420 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U | ||
| 1421 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 | ||
| 1422 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 | ||
| 1423 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U | ||
| 1424 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 | ||
| 1425 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 | ||
| 1426 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U | ||
| 1427 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 | ||
| 1428 | #define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 | ||
| 1429 | /* Register EUR_CR_PIPE1_BREAKPOINT_TRAP */ | ||
| 1430 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98 | ||
| 1431 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U | ||
| 1432 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 | ||
| 1433 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 | ||
| 1434 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U | ||
| 1435 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 | ||
| 1436 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 | ||
| 1437 | /* Register EUR_CR_PIPE1_BREAKPOINT */ | ||
| 1438 | #define EUR_CR_PIPE1_BREAKPOINT 0x0F9C | ||
| 1439 | #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U | ||
| 1440 | #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6 | ||
| 1441 | #define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SIGNED 0 | ||
| 1442 | #define EUR_CR_PIPE1_BREAKPOINT_ID_MASK 0x00000030U | ||
| 1443 | #define EUR_CR_PIPE1_BREAKPOINT_ID_SHIFT 4 | ||
| 1444 | #define EUR_CR_PIPE1_BREAKPOINT_ID_SIGNED 0 | ||
| 1445 | #define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_MASK 0x00000008U | ||
| 1446 | #define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SHIFT 3 | ||
| 1447 | #define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SIGNED 0 | ||
| 1448 | #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U | ||
| 1449 | #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2 | ||
| 1450 | #define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0 | ||
| 1451 | /* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 */ | ||
| 1452 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0 | ||
| 1453 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U | ||
| 1454 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 | ||
| 1455 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 | ||
| 1456 | /* Register EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 */ | ||
| 1457 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4 | ||
| 1458 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U | ||
| 1459 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 | ||
| 1460 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 | ||
| 1461 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U | ||
| 1462 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 | ||
| 1463 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 | ||
| 1464 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U | ||
| 1465 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 | ||
| 1466 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 | ||
| 1467 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U | ||
| 1468 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 | ||
| 1469 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 | ||
| 1470 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U | ||
| 1471 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 | ||
| 1472 | #define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 | ||
| 1473 | /* Table EUR_CR_USE_CODE_BASE */ | ||
| 1474 | /* Register EUR_CR_USE_CODE_BASE */ | ||
| 1475 | #define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) | ||
| 1476 | #define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU | ||
| 1477 | #define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 | ||
| 1478 | #define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0 | ||
| 1479 | #define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U | ||
| 1480 | #define EUR_CR_USE_CODE_BASE_DM_SHIFT 26 | ||
| 1481 | #define EUR_CR_USE_CODE_BASE_DM_SIGNED 0 | ||
| 1482 | /* Number of entries in table EUR_CR_USE_CODE_BASE */ | ||
| 1483 | #define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 | ||
| 1484 | #define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 | ||
| 1485 | |||
| 1486 | #endif /* _SGX543DEFS_KM_H_ */ | ||
| 1487 | |||