mmc: omap_hsmmc: Update max clk divider

Max clock divider is MMC_FCLK / 1023.

Change-Id: Idc56e08af3c1d71756e672406b445c845b7ea7e0
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index aa0440817c50..e50f42de660c 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -79,6 +79,7 @@
 #define CEN                     (1 << 2)
 #define CLKD_MASK               0x0000FFC0
 #define CLKD_SHIFT              6
+#define CLKD_MAX                1023
 #define DTO_MASK                0x000F0000
 #define DTO_SHIFT               16
 #define INIT_STREAM             (1 << 1)
@@ -525,8 +526,8 @@ static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 
         if (ios->clock) {
                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
-                if (dsor > 250)
-                        dsor = 250;
+                if (dsor > CLKD_MAX)
+                        dsor = CLKD_MAX;
         }
 
         return dsor;