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authorPraveen Rao2013-08-08 13:37:35 -0500
committerPraneeth Bajjuri2013-08-09 17:05:14 -0500
commit6d90709163afd1f314ad688428bb929215f8e295 (patch)
tree0b07b3f87e4e8c587c987f00f0a09d40ca5152dd
parentdeff0ef5f52b2d4f2677a3d98d22b957ec14be08 (diff)
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arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVM
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and sleep states and enable them in board evm dts file. Change-Id: I5524a2d4c2713388ba59da75fa6e90b27c100fc1 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflict and rebased on 3.8 kernel. This patch is based on http://git.ti.com/cgit/cgit.cgi/~mugunthanvnm/ti-linux-kernel/mugunth-connectivity-linux-feature-tree.git/commit/?h=dra7-3.11-rc3-cpsw&id=8da845bd7fbab68b4899d5a6477e70a34748f6c6 ] Update the pinmux configuration for CPSW and MDIO by removing the macro definitons to match the 3.8 implementation. Signed-off-by: Praveen Rao <prao@ti.com>
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts59
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index d16605bbbb55..238a28d3dc7a 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -174,6 +174,65 @@
174 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */ 174 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */
175 >; 175 >;
176 }; 176 };
177
178 cpsw_default_pins: pinmux_cpsw_default_pins {
179 pinctrl-single,pins = <
180 /* Slave 1 */
181 0x250 0x0 /* rgmii1_tclk PIN_OUTPUT | MUX_MODE0 */
182 0x254 0x0 /* rgmii1_tctl PIN_OUTPUT | MUX_MODE0 */
183 0x258 0x0 /* rgmii1_td3 PIN_OUTPUT | MUX_MODE0 */
184 0x25c 0x0 /* rgmii1_td2 PIN_OUTPUT | MUX_MODE0 */
185 0x260 0x0 /* rgmii1_td1 PIN_OUTPUT | MUX_MODE0 */
186 0x264 0x0 /* rgmii1_td0 PIN_OUTPUT | MUX_MODE0 */
187 0x268 0x00040000 /* rgmii1_rclk PIN_INPUT | MUX_MODE0 */
188 0x26c 0x00040000 /* rgmii1_rctl PIN_INPUT | MUX_MODE0 */
189 0x270 0x00040000 /* rgmii1_rd3 PIN_INPUT | MUX_MODE0 */
190 0x274 0x00040000 /* rgmii1_rd2 PIN_INPUT | MUX_MODE0 */
191 0x278 0x00040000 /* rgmii1_rd1 PIN_INPUT | MUX_MODE0 */
192 0x27c 0x00040000 /* rgmii1_rd0 PIN_INPUT | MUX_MODE0 */
193
194 /* Slave 2 */
195 0x198 0x4 /* rgmii2_tclk PIN_OUTPUT | MUX_MODE4 */
196 0x19c 0x4 /* rgmii2_tctl PIN_OUTPUT | MUX_MODE4 */
197 0x1a0 0x4 /* rgmii2_td3 PIN_OUTPUT | MUX_MODE4 */
198 0x1a4 0x4 /* rgmii2_td2 PIN_OUTPUT | MUX_MODE4 */
199 0x1a8 0x4 /* rgmii2_td1 PIN_OUTPUT | MUX_MODE4 */
200 0x1ac 0x4 /* rgmii2_td0 PIN_OUTPUT | MUX_MODE4 */
201 0x1b0 0x00040004 /* rgmii2_rclk PIN_INPUT | MUX_MODE4 */
202 0x1b4 0x00040004 /* rgmii2_rctl PIN_INPUT | MUX_MODE4 */
203 0x1b8 0x00040004 /* rgmii2_rd3 PIN_INPUT | MUX_MODE4 */
204 0x1bc 0x00040004 /* rgmii2_rd2 PIN_INPUT | MUX_MODE4 */
205 0x1c0 0x00040004 /* rgmii2_rd1 PIN_INPUT | MUX_MODE4 */
206 0x1c4 0x00040004 /* rgmii2_rd0 PIN_INPUT | MUX_MODE4 */
207 >;
208 };
209
210 davinci_mdio_default_pins: pinmux_davinci_mdio_default_pins {
211 pinctrl-single,pins = <
212 /* MDIO */
213 0x23c 0x30000 /* mdio_data PIN_OUTPUT_PULLUP | MUX_MODE0 */
214 0x240 0x70000 /* mdio_clk PIN_INPUT_PULLUP | MUX_MODE0 */
215 >;
216 };
217};
218
219&gmac {
220 status="okay";
221 pinctrl-names = "default";
222 pinctrl-0 = <&cpsw_default_pins>;
223};
224
225&davinci_mdio {
226 pinctrl-names = "default";
227 pinctrl-0 = <&davinci_mdio_default_pins>;
228};
229
230&cpsw_emac0 {
231 phy_id = <&davinci_mdio>, <2>;
232};
233
234&cpsw_emac1 {
235 phy_id = <&davinci_mdio>, <3>;
177}; 236};
178 237
179&i2c1 { 238&i2c1 {