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author | Misael Lopez Cruz | 2013-06-07 15:59:46 -0500 |
---|---|---|
committer | Misael Lopez Cruz | 2013-07-22 15:04:20 -0500 |
commit | a0d1af7abccce43ef3f1a5d3d585344367ecc89d (patch) | |
tree | 366d3bb7b42d3287a0f18deb322e125119d21719 | |
parent | e3884267635918122c953590c1516cfb276285ad (diff) | |
download | kernel-audio-a0d1af7abccce43ef3f1a5d3d585344367ecc89d.tar.gz kernel-audio-a0d1af7abccce43ef3f1a5d3d585344367ecc89d.tar.xz kernel-audio-a0d1af7abccce43ef3f1a5d3d585344367ecc89d.zip |
ARM: DRA7: clocks: Append _ck to atl_clkin* and ref_clkin*
Suffix 'ck' is missing for 'atl_clkin*' and 'ref_clkin*' clocks in
mcasp and timer parent clock names list.
Fix also a missing "_" in 'atl_clkin3_ck'.
Change-Id: I0d1ced5c61b08c63577872a38b16390f506c9cba
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/cclock7xx_data.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c index 7160e64bc4aa..861085b8f53e 100644 --- a/arch/arm/mach-omap2/cclock7xx_data.c +++ b/arch/arm/mach-omap2/cclock7xx_data.c | |||
@@ -52,7 +52,7 @@ DEFINE_CLK_FIXED_RATE(atl_clkin1_ck, CLK_IS_ROOT, 0, 0x0); | |||
52 | 52 | ||
53 | DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0); | 53 | DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0); |
54 | 54 | ||
55 | DEFINE_CLK_FIXED_RATE(atlclkin3_ck, CLK_IS_ROOT, 0, 0x0); | 55 | DEFINE_CLK_FIXED_RATE(atl_clkin3_ck, CLK_IS_ROOT, 0, 0x0); |
56 | 56 | ||
57 | DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0); | 57 | DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0); |
58 | 58 | ||
@@ -1558,9 +1558,9 @@ DEFINE_CLK_DIVIDER_TABLE(l3instr_ts_gclk_div, "wkupaon_iclk_mux", | |||
1558 | 1558 | ||
1559 | static const char *mcasp1_ahclkr_mux_parents[] = { | 1559 | static const char *mcasp1_ahclkr_mux_parents[] = { |
1560 | "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk", | 1560 | "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk", |
1561 | "atlclkin3", "atl_clkin2", "atl_clkin1", | 1561 | "atl_clkin3_ck", "atl_clkin2_ck", "atl_clkin1_ck", |
1562 | "atl_clkin0", "sys_clkin2", "ref_clkin0", | 1562 | "atl_clkin0_ck", "sys_clkin2", "ref_clkin0_ck", |
1563 | "ref_clkin1", "ref_clkin2", "ref_clkin3", | 1563 | "ref_clkin1_ck", "ref_clkin2_ck", "ref_clkin3_ck", |
1564 | "mlb_clk", "mlbp_clk", | 1564 | "mlb_clk", "mlbp_clk", |
1565 | }; | 1565 | }; |
1566 | 1566 | ||
@@ -1695,8 +1695,8 @@ DEFINE_CLK_DIVIDER(qspi_gfclk_div, "qspi_gfclk_mux", &qspi_gfclk_mux, 0x0, | |||
1695 | 1695 | ||
1696 | static const char *timer10_gfclk_mux_parents[] = { | 1696 | static const char *timer10_gfclk_mux_parents[] = { |
1697 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", | 1697 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", |
1698 | "ref_clkin0", "ref_clkin1", "ref_clkin2", | 1698 | "ref_clkin0_ck", "ref_clkin1_ck", "ref_clkin2_ck", |
1699 | "ref_clkin3", "abe_giclk_div", "video1_div_clk", | 1699 | "ref_clkin3_ck", "abe_giclk_div", "video1_div_clk", |
1700 | "video2_div_clk", "hdmi_div_clk", | 1700 | "video2_div_clk", "hdmi_div_clk", |
1701 | }; | 1701 | }; |
1702 | 1702 | ||
@@ -1742,8 +1742,8 @@ DEFINE_CLK_MUX(timer4_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, | |||
1742 | 1742 | ||
1743 | static const char *timer5_gfclk_mux_parents[] = { | 1743 | static const char *timer5_gfclk_mux_parents[] = { |
1744 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", | 1744 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", |
1745 | "ref_clkin0", "ref_clkin1", "ref_clkin2", | 1745 | "ref_clkin0_ck", "ref_clkin1_ck", "ref_clkin2_ck", |
1746 | "ref_clkin3", "abe_giclk_div", "video1_div_clk", | 1746 | "ref_clkin3_ck", "abe_giclk_div", "video1_div_clk", |
1747 | "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux", | 1747 | "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux", |
1748 | }; | 1748 | }; |
1749 | 1749 | ||
@@ -1831,7 +1831,7 @@ static struct omap_clk dra7xx_clks[] = { | |||
1831 | CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX), | 1831 | CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX), |
1832 | CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX), | 1832 | CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX), |
1833 | CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX), | 1833 | CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX), |
1834 | CLK(NULL, "atlclkin3_ck", &atlclkin3_ck, CK_7XX), | 1834 | CLK(NULL, "atl_clkin3_ck", &atl_clkin3_ck, CK_7XX), |
1835 | CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX), | 1835 | CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX), |
1836 | CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX), | 1836 | CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX), |
1837 | CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX), | 1837 | CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX), |