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author | Archit Taneja | 2013-06-05 00:46:53 -0500 |
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committer | Archit Taneja | 2013-06-05 02:14:31 -0500 |
commit | 7250753a7153133a0c3750f4a6f0670000bf4d8c (patch) | |
tree | ffac9103bac25e82e5ac9745ac379097e28c5e80 /drivers | |
parent | e51ff8ae127ff81eb1285908aa382a4d9daa1d23 (diff) | |
download | kernel-audio-7250753a7153133a0c3750f4a6f0670000bf4d8c.tar.gz kernel-audio-7250753a7153133a0c3750f4a6f0670000bf4d8c.tar.xz kernel-audio-7250753a7153133a0c3750f4a6f0670000bf4d8c.zip |
omapdss: DSS DPLLs: Ignore PLL_PWR_STATUS on DRA7
There is a Vayu bug(VAYU-BUG02893) which prevents the correct update of
PLL_PWR_STATUS when the power state of DPLL_VIDEO1/2 is changed. Currently, the
driver reports the error but still proceeds ahead. Modify the code such that we
don't read the buggy field at all and adds a small delay for the power state to
change.
Signed-off-by: Archit Taneja <archit@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/video/omap2/dss/dss_dpll.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/video/omap2/dss/dss_dpll.c b/drivers/video/omap2/dss/dss_dpll.c index 7fd69c87df25..121fe39d689b 100644 --- a/drivers/video/omap2/dss/dss_dpll.c +++ b/drivers/video/omap2/dss/dss_dpll.c | |||
@@ -352,11 +352,21 @@ static int dpll_power(enum dss_dpll dpll, int state) | |||
352 | /* PLL_PWR_CMD = enable both hsdiv and clkout*/ | 352 | /* PLL_PWR_CMD = enable both hsdiv and clkout*/ |
353 | REG_FLD_MOD(dpll, CLK_CTRL, state, 31, 30); | 353 | REG_FLD_MOD(dpll, CLK_CTRL, state, 31, 30); |
354 | 354 | ||
355 | /* PLL_PWR_STATUS: (NOTE: apparently buggy) */ | 355 | /* |
356 | * PLL_PWR_STATUS doesn't correctly reflect the power state set on | ||
357 | * DRA7xx. Ignore the reg field and add a small delay for the power | ||
358 | * state to change. | ||
359 | */ | ||
360 | if (omapdss_get_version() == OMAPDSS_VER_DRA7xx) { | ||
361 | msleep(1); | ||
362 | return 0; | ||
363 | } | ||
364 | |||
365 | /* PLL_PWR_STATUS */ | ||
356 | while (FLD_GET(dpll_read_reg(dpll, CLK_CTRL), 29, 28) != state) { | 366 | while (FLD_GET(dpll_read_reg(dpll, CLK_CTRL), 29, 28) != state) { |
357 | if (++t > 1000) { | 367 | if (++t > 1000) { |
358 | DSSERR("Failed to set DPLL power mode to %d\n", state); | 368 | DSSERR("Failed to set DPLL power mode to %d\n", state); |
359 | /* return -ENODEV; */ | 369 | return -ENODEV; |
360 | return 0; | 370 | return 0; |
361 | } | 371 | } |
362 | udelay(1); | 372 | udelay(1); |