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authorPraveen Rao2013-08-08 13:47:43 -0500
committerPraneeth Bajjuri2013-08-09 17:05:33 -0500
commite9d2d62aaf51514a2a84ef28262ef300b37df69a (patch)
tree8c8726240d2bffee981c1479f8002a43df3308d3 /samples/kdb/kdb_hello.c
parent6d90709163afd1f314ad688428bb929215f8e295 (diff)
HACK: ARM: DRA7XX: ETH: Use n_latch in pcf8575 to drive P10 for ETH0HEADmaster
Use n_latch to hack the pcf8575 driver to "drive P10" to not hold ETH0 in reset. Description: nETH_RST is a pin that controls the phy reset -> this was the core of the issue -> we have pcf8575 GPIO expander on i2c1 whose P10(ETH0) and P11(ETH1) hold or release the ETH from reset. On the very first write by Display Panel driver (which rightly control's it's own GPIO expander pin P15), all other pins are written as 0 -> since this is the first write(by panel), this is precisely when pcf8575 starts to drive the signal -> at this point the default pulls are overridden by pcf8575's pulls. As ETH driver does not drive it's pin, the ETH0_RST is driven low, holding Ethernet in reset. Nishanth Menon helped in isolatng this issue. REVISIT: This is a ethernet driver bug and has to be fixed properly post release. Change-Id: I45ddb1202761f052f8a8a04faf14b841da5af2ec Signed-off-by: Praveen Rao <prao@ti.com>
Diffstat (limited to 'samples/kdb/kdb_hello.c')
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