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* HACK: ARM: DRA7XX: ETH: Use n_latch in pcf8575 to drive P10 for ETH0HEADmasterPraveen Rao2013-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Use n_latch to hack the pcf8575 driver to "drive P10" to not hold ETH0 in reset. Description: nETH_RST is a pin that controls the phy reset -> this was the core of the issue -> we have pcf8575 GPIO expander on i2c1 whose P10(ETH0) and P11(ETH1) hold or release the ETH from reset. On the very first write by Display Panel driver (which rightly control's it's own GPIO expander pin P15), all other pins are written as 0 -> since this is the first write(by panel), this is precisely when pcf8575 starts to drive the signal -> at this point the default pulls are overridden by pcf8575's pulls. As ETH driver does not drive it's pin, the ETH0_RST is driven low, holding Ethernet in reset. Nishanth Menon helped in isolatng this issue. REVISIT: This is a ethernet driver bug and has to be fixed properly post release. Change-Id: I45ddb1202761f052f8a8a04faf14b841da5af2ec Signed-off-by: Praveen Rao <prao@ti.com>
* arm/dts: dra7xx: Enable CPSW and MDIO for dra7xx EVMPraveen Rao2013-08-091-0/+59
| | | | | | | | | | | | | | | Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and sleep states and enable them in board evm dts file. Change-Id: I5524a2d4c2713388ba59da75fa6e90b27c100fc1 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflict and rebased on 3.8 kernel. This patch is based on http://git.ti.com/cgit/cgit.cgi/~mugunthanvnm/ti-linux-kernel/mugunth-connectivity-linux-feature-tree.git/commit/?h=dra7-3.11-rc3-cpsw&id=8da845bd7fbab68b4899d5a6477e70a34748f6c6 ] Update the pinmux configuration for CPSW and MDIO by removing the macro definitons to match the 3.8 implementation. Signed-off-by: Praveen Rao <prao@ti.com>
* arm/dts: dra7xx: Add CPSW and MDIO module nodes for dra7xxMugunthan V N2013-08-091-1/+51
| | | | | | | | | | | | | | | | Add CPSW and MDIO related device tree data for DRA7XX and made as status disabled. Phy-id, pinmux for active and sleep state needs to be added in board dts files and enable the CPSW device. Change-Id: Ia8c6f8ec8eff0d66e0d05f4a6e1ce174a725b2fd Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [Resolved merge conflict and rebased to 3.8 kernel] Updated the CPSW and MDIO related device tree data with correct device address offset and also to remove marco defines which caused compilation error seen as below: Error: arch/arm/boot/dts/dra7.dtsi:701.22-23 syntax error FATAL ERROR: Unable to parse input tree Signed-off-by: Praveen Rao <prao@ti.com>
* arm: dra7xx: Add hwmod data for MDIO and CPSWMugunthan V N2013-08-091-0/+98
| | | | | | | | | | Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC Change-Id: I9652c4956025335b3cdf3831bbd87ce104a80f65 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Update the hwmod data for CPSW and MDIO to added addr space and irq info hwmod data. Signed-off-by: Praveen Rao <prao@ti.com>
* drivers: net: cpsw: Add support for new CPSW IP versionMugunthan V N2013-08-091-0/+3
| | | | | | | | | | | The new IP version has a minor changes and the offsets are same as the previous version, so adding new IP version support in the driver. Change-Id: I19274d09b25be8acc3db3cdd74346aa79989f46a Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> [Added change-id for gerrit] Signed-off-by: Praveen Rao <prao@ti.com>
* ARM: dts: dra7: Enable OPP_OD 1.5GhzPraneeth Bajjuri2013-08-091-0/+3
| | | | | | | | | | | | OPP_OD Can be enabled on trimmed and poly fixed DRA7xx samples. to identify poly-fixed trim samples: [dieID: 0x4AE0C20C], [FT_Rev bits 15:8] >= 5. This enables 1.5 Ghz for dra7xxx mpu. Change-Id: If92bff1889de54cf51bedde3ebe8f1c9b17a7657 Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* defconfig: omap2plus: input: Enable atmel_mxt_ts touch driverPraneeth Bajjuri2013-08-091-0/+1
| | | | | | | Enable Atmel MXT244 touch screen driver for dra7-evm Change-Id: I8332c0cd677fdfd0c83e5f9c7ebf6275a9db49c2 Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* ARM: dts: dra7-evm: Add DT entry for Atmel MXT244 touch driverSundar Raman2013-08-091-0/+65
| | | | | | | | | | | | This patch adds DT entry for atmel MXT244 touch driver (atmel_mxt_ts). The device is on i2c1 and with address 0x4a. Platform configuration data and interrupts data is added inside dra7-evm.dts file. Pinctrl for Wakeup2 irq pin, which is used for touchscreen interrupt, has also been updated Change-Id: Icfb2f9e9655febaa40e6f6b3b7334462eb8e056a Signed-off-by: Sundar Raman <a0393242@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
* Input: atmel_mxt_ts: Add device tree supportSundar Raman2013-08-092-5/+238
| | | | | | | | | | | | | | | Add device tree support for Atmel touch driver. All platform specific data is now read from dts files and parsed inside the driver. NOTE: Provision for supplying config data for controller is given from board specific dts file since the driver no longer configures these values for different firmware revisions, after this commit: 71749f5c66e797a39600dae9de58aab3858dc488 Change-Id: Ic88bc62246e2465d527410e6fef78b301d681628 Signed-off-by: Sundar Raman <sunds@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
* Input: atmel_mxt_ts: switch to using devm_kzallocNishanth Menon2013-08-091-3/+1
| | | | | | | | Using managed allocation helps us simplify our probe and cleanup. Change-Id: I239ddefb4a07c92c902f5460e6da7f0663a877c2 Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sundar Raman <sunds@ti.com>
* Input: atmel_mxt_ts: switch to using devm_request_threaded_irqNishanth Menon2013-08-091-8/+6
| | | | | | | | | Using managed request irq helps us simplify our probe and cleanup a lot. Change-Id: Ibe5a5b76b072e56414699798ea63ed8dd7f45c89 Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sundar Raman <sunds@ti.com>
* usb: dwc3: host: Change platform device ID for xhci-hcd to AUTOVivek Gautam2013-08-091-1/+1
| | | | | | | | | | | | | | | Multiple dwc3 controllers will try to allocate multiple xhci-hcd interfaces. Changing platform device IDs from NONE to AUTO to support such cases. upstream-status:: https//git.kernel.org/cgit/linux/kernel/git/torvalds/ linux.git/commit/?id=52758bcb7c12bede2a81849dee13f1edcd44e1c1 Change-Id: Iaaf38e258c28ead10cff51b993f378a6fc3f5679 Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
* usb: host: xhci: Enable XHCI_SPURIOUS_SUCCESS for all controllers with xhci 1.0George Cherian2013-08-092-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xhci controllers with hci_version > 0.96 gives spurious success events on short packet completion. During webcam capture the "ERROR Transfer event TRB DMA ptr not part of current TD" was observed. The same application works fine with synopsis controllers hci_version 0.96. The same Issue is seen with Intel Pantherpoint xhci controller. So enabling this quirk in xhci_gen_setup if controller verion is greater than 0.96. For xhci-pci move the quirk to much generic place xhci_gen_setup. Note from Sarah: The xHCI 1.0 spec changed how hardware handles short packets. The HW will notify SW of the TRB where the short packet occurred, and it will also give a successful status for the last TRB in a TD (the one with the IOC flag set). On the second successful status, that warning will be triggered in the driver. Software is now supposed to not assume the TD is not completed until it gets that last successful status. That means we have a slight race condition, although it should have little practical impact. This patch papers over that issue. It's on my long-term to-do list to fix this race condition, but it is a much more involved patch that will probably be too big for stable. This patch is needed for stable to avoid serious log spam. This patch should be backported to kernels as old as 3.0, that contain the commit ad808333d8201d53075a11bc8dd83b81f3d68f0b "Intel xhci: Ignore spurious successful event." The patch will have to be modified for kernels older than 3.2, since that kernel added the xhci_gen_setup function for xhci platform devices. The correct conflict resolution for kernels older than 3.2 is to set XHCI_SPURIOUS_SUCCESS in xhci_pci_quirks for all xHCI 1.0 hosts. upstream-status: http://marc.info/?l=linux-usb&m=137265657724242&w=2 Change-Id: I4f5b93a6031118facd971985e40c77280e53ffe3 Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> [backported to 3.8] Signed-off-by: Ravi Babu <ravibabu@ti.com>
* ASoC: davinci-mcasp: Mute transmit data during stopMisael Lopez Cruz2013-08-082-4/+19
| | | | | | | | | | | | | | | Reset of the state machine, serializer and frame sync generator can occur in the middle of a slot, making the transmit pin go to its inactive state. It can cause discontinuities that may lead to glitches. The discontinuities can be more abrupt for audio samples with negative values. Muting the transmit data by masking out all its bits can prevent this problem. A delay is required to ensure at least one slot uses the new bit mask, the worst case (longest slot) is for 8kHz, mono (125 us). Change-Id: I812ac674d1c9a3905086a966e0ec4795374f333a Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7: Set cpufreq transition latency valueRanganath Krishnan2013-08-061-0/+6
| | | | | | | | | | | | | | Without clock-latency initialization, default value of (2^32 -1) is taken. Because of the too long transition latency, ondemand governor fails and the cpufreq governor fallback to performance governor. With this change, ondemand governor can be enabled by default for DRA7. clock-latency value referenced from omap5 (TBD: to be instrumented and use the actual value at later point of time) Change-Id: I2fa2e53088ba7e7f8f8509a8005b81ee593b55a7 Signed-off-by: Ranganath Krishnan <ranganath@ti.com>
* ARM: dts: dra7-evm: Primary card as always-onMisael Lopez Cruz2013-08-051-0/+1
| | | | | | | | Power resources are not a concern in dra7-evm context so keeping primary card as always-on to reduce audio artifacts. Change-Id: I1ba906d8716922e63a8622acefbc2cea498875b6 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: DRA7: dra7-evm: Add support for always onMisael Lopez Cruz2013-08-052-0/+23
| | | | | | | | | | There are environments where power resources are not a concern, but having the best quality in terms of artifacts is more important. For those scenarios, allow keeping the analog codecs always on, set via DT. This is achieved by simply using a very high pmdown_time value. Change-Id: I91bda710096427a9d5ec4c998eea40efb87ff123 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7-evm: Add tlv320aic3x capture settle timeMisael Lopez Cruz2013-08-051-0/+1
| | | | | | | | Add a capture settle time to reduce the pop noise in capture path of DRA7EVM, the pop noise lasts around 30-40ms. Change-Id: Idde7aec70e95354f25544aad3429050630259cc0 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: tlv320aic3x: Add ADC settle timeMisael Lopez Cruz2013-08-053-3/+29
| | | | | | | | | | | | | | | | There are artifacts during capture route start (e.g. caused by bias or even ADC power-on itsef) that cannot be removed through DAPM or with CODEC's facilities. A settle time is added to account for these artifacts. -- similar to: commit: 07ca81d43d5c7ed7be2e164e0f85631c1938be30 Author: Gabriel M. Beddingfield <gabrbedd@ti.com> ASoC: twl6040: Let amics settle after biasing -- Change-Id: Iba12c014b8e088d2a4346a1cf34884be40959ac9 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: tlv320aic3x: Add output driver pop reduction controlsMisael Lopez Cruz2013-08-051-0/+14
| | | | | | | | | Output driver has two parameters that can be configured to reduce pop noise: power-on delay and ramp-up step time. Two new kcontrols have been added to set these parameters. Change-Id: Icb9963ce046adb81bf31997a037c404178e18f71 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: tlv320aic3x: Connect Line1R-LADC and Line1L-RADCMisael Lopez Cruz2013-08-051-0/+4
| | | | | | | | | 'Left Line1R Mux' and 'Right Line1L Mux' were not connected in the audio map of the CODEC, hence changing the kcontrols associated with them had no effect. Change-Id: I6060e6415e742e9145c2c17fe7e4d7b3fe7c1c1a Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7: Add McASP interruptsMisael Lopez Cruz2013-08-021-4/+4
| | | | | | | | Add interrupts information to McASP3 and McASP6 nodes. These IRQ numbers also need configured in the IRQ crossbar. Change-Id: Ic4f1409e9f54a4705ef45f727dfed5b2757ed96b Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: DRA7: dra7-evm: Remove crossbar hacksMisael Lopez Cruz2013-08-022-16/+0
| | | | | | | | Partially remove DMA crossbar hack done by "ASoC: DRA7: dra7-evm: HACK: Set McASP DMA reqs in sDMA crossbar". The sDMA reqs in DRA7xx hwmod are kept. Change-Id: I99ffe54e83a09b3003df5b07c5621565a1d9aed4 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: OMAP: omap2plus_defconfig: disable USB debug flagsVishal Mahaveer2013-07-221-4/+0
| | | | | | | Disable USB debug flags from omap2plus_defconfig Change-Id: Icfa01952faae6992d5bfc97ce8ae27f79f977e3c Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
* ARM: omap2plus_defconfig: Enable dra7-evm sound supportMisael Lopez Cruz2013-07-221-4/+15
| | | | | | | Enable ALSA and dra7-evm sound support as built-in features. Change-Id: I3d00f20e7aeeee3a6d298183969de21e32d264b8 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7-evm: Add HDMI sound nodeMisael Lopez Cruz2013-07-221-0/+7
| | | | | | | | Add HDMI audio node. Change-Id: I220e56b5a45716a7f7d6bd0b32df102f16746d16 Signed-off-by: Dandawate Saket <dsaket@ti.com> Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* OMAPDSS: HDMI: Fix GPA Channel Setting and Channel Allocation for 6-ChannelsAngela Stegmaier2013-07-222-5/+8
| | | | | | | | | | | | | | | Enable channels 0 to 5 in GPA configuration (GP_CONF1) for the 6 channels case. This fixes an issue where the Audio Sample Packet was carrying 8 channels instead of 6 channels. The new GPA configuration sets the sample_present.sp3 bit to 0, then 0x13 is not a valid channel allocation. So, the channel allocation is set to a valid value (0xb), when the number of channels is 6. Also a typo is fixed in the comments for the eight channel case. Change-Id: I3c987a4efdaf9f9594c99dc1fca1470b53a59355 Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
* OMAPDSS: OMAP5: HDMI: Audio InfoFrame DB1 field offsetsMisael Lopez Cruz2013-07-221-1/+3
| | | | | | | | | CHNL_COUNT is in bits 6:4 and CODING_TYPE in bits 3:0 of HDMI_CORE_FC_AUDICONF0 register, while in the CEA-861 definition DB1CC is in bits 2:0 and DB1CT in bits 7:4. Change-Id: Ifd6ca2c91209b7fcf31dfdc921707c0ad5c9378a Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: omap-hdmi-card: Remove redundant printMisael Lopez Cruz2013-07-221-2/+0
| | | | | | | | HDMI card name is already printed when card is registered in ALSA, no need to print it again. Change-Id: I4bbe1acc45ab647a6a28824f3cb86a14163ba054 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: DRA7: hwmod: Fix HDMI irq numberMisael Lopez Cruz2013-07-221-1/+1
| | | | | | | | HDMI_IRQ is connected to IRQ_CROSSBAR_96 in DRA7, previous IRQ number was for OMAP5. Change-Id: Iedff41b2e2dc253be7f6aa8a18c0c0d23a7f989d Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: DRA7: clocks: Fix HDMI sys_clk mux registerMisael Lopez Cruz2013-07-221-1/+1
| | | | | | | | HDMI sys_clk mux uses CM_CLKSEL_HDMI_PLL_SYS register for source selection. Change-Id: I3c762b2ff4e845978b69482ec3422dcbc736e49c Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: DRA7: dra7-evm: HACK: Set McASP DMA reqs in sDMA crossbarMisael Lopez Cruz2013-07-222-0/+31
| | | | | | | | | McASP3 and McASP6 don't have default DMA reqs assigned in sDMA crossbar. In the meantime, McASP3 TX/RX DMA reqs are reassigned to sDMA_78 and 79, and McASP6 TX/RX to sDMA_62 and 63. Change-Id: I079e181cfeccd12a121ea3f864bd8905609d09ad Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7-evm: Add sound card nodeMisael Lopez Cruz2013-07-221-0/+47
| | | | | | | | | | Add node for McASP-based sound card which consists of the media DAI link that connects McASP3 and tlv320aic3106. This DAI link in I2S mode with a bit clock of 5.6448 MHz that allows 44.1kHz, 16-bits/sample. Change-Id: I46aaa94a68c6b3c89069b9030edf96d57d2476ef Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7: Add ATL nodeMisael Lopez Cruz2013-07-221-0/+12
| | | | | | | | | | ATL1 and ATL2 are the only instances enabled. ATL1 is used to supply the audio clock for the 16-slots TDM DAI link, so it requires an output freq of 11.2896 MHz. ATL2 is used for the I2S DAI link and is configured to 5.6448 MHz. Change-Id: I4cf5ed86e75aa517e1ab3dbb3de8e9227013311b Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7: Add McASP nodesMisael Lopez Cruz2013-07-221-0/+28
| | | | | | | | | | | | | | McASP3 is configured in I2S mode with AXR0 as TX and AXR1 as RX. McASP6 is configured in TDM mode (uses same op-mode property value than I2S) with 8-slots, AXR0 is used for TX and AXR1 for RX. Interrupt property in both nodes is using McASP1's in the meantime since McASP3 and McASP6 don't have default interrupt lines and have to be assigned through IRQ crossbar. Change-Id: I766dcbea9190083c6fe0e01501104226d480a22f Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: dts: dra7-evm: Add audio pinctrlMisael Lopez Cruz2013-07-221-0/+28
| | | | | | | | | Add pinctrl entries for McASP3, McASP6 and ATL. McASP pins are configured so that McASPs are masters in their corresponding audio links. Change-Id: I507ad5941cf679a4afab98fcca7cbeba5fe5cad8 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: DRA7: dra7-evm: Add initial support for DRA7 EVMMisael Lopez Cruz2013-07-224-0/+387
| | | | | | | | | | | Add initial support for DRA7 EVM, it includes the media DAI link that connects McASP3 and tlv320aic3106 in I2S mode. DRA7xx is a high-performance, infotainment application device, based on enhanced OMAP architecture integrated on a 28-nm technology. Change-Id: I3be3e94e2f9c5736f236e965297d3cb9d646c7fc Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: DRA7: atl: Add initial support for Audio Tracking LogicMisael Lopez Cruz2013-07-224-0/+364
| | | | | | | | | Add initial version of Audio Tracking Logic (ATL) driver. ATL is used to synchronize the digital audio output to the baseband clock. ATL produces a timing signal at the top of the audio clock tree. Change-Id: I123ff440b8e478c12e28ff4db42d1196f0ae4f6b Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: DRA7: clocks: Append _ck to atl_clkin* and ref_clkin*Misael Lopez Cruz2013-07-221-9/+9
| | | | | | | | | | Suffix 'ck' is missing for 'atl_clkin*' and 'ref_clkin*' clocks in mcasp and timer parent clock names list. Fix also a missing "_" in 'atl_clkin3_ck'. Change-Id: I0d1ced5c61b08c63577872a38b16390f506c9cba Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ARM: DRA7: clock: Fix the wrong ABE PLL lock frequencyRajendra Nayak2013-07-221-1/+2
| | | | | | | | | The ABE PLL (used by ATL) was wrongly locked at twice the frequency. Fix it and also set the dpll_abe_m2x2_ck rate explicitely so that we have m2 set to 1. Change-Id: I5efc593c46ee7b31f06326b361a85f27dd3310ec Signed-off-by: Rajendra Nayak <rnayak@ti.com>
* ARM: DRA7: hwmod: Disable smart-idle for McASPMisael Lopez Cruz2013-07-221-0/+8
| | | | | | | | As per TRM, wakeup schema is not supported by McASP, so it's recommended to use no-idle after McASP is enabled, and smart-idle after it's disabled. Change-Id: Ia20eff9238b996dbcac4b534b4645ec93fd8bafb Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Add hw_rule for buffer_size when using AFIFOAngela Stegmaier2013-07-221-1/+80
| | | | | | | | | | | | The AFIFO threshold imposes a limiation on the buffer size. When the AFIFO is used, the buffer size (in samples) needs to be an integer multiple of the AFIFO threshold value (wnumevt, rnumevt). This patch adds a hw_rule to the McASP driver for version 4 of the McASP to account for the limitation on the buffer size. Change-Id: I3bd320130b10a55d3d84defd99572526ad6469fb Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
* ASoC: davinci-mcasp: Add support for using McASP DATA portAngela Stegmaier2013-07-222-4/+21
| | | | | | | | | | | | | | | By default the CFG port is used for data transfer. It is desireable to use the DATA port so that the AFIFO can be used on DRA7XX. To enable DATA port usage, during the probe a check for an IORESOURCE_MEM named "dat" is done. If the resource is found, the data port will be used. If it is not found, the driver will fall back to using the cfg port. Change-Id: I42c3cc04621354ef1fd7546f9feff003cf6b38ce Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
* ASoC: davinci-mcasp: HACK: Add MCASP_VERSION_4 supportMisael Lopez Cruz2013-07-225-52/+145
| | | | | | | | | | | | McASP IP found in DRA7xx devices is similar to the one described by VERSION_3 (TI81xx, AM33xx), except that a different DMA mechanism is used. A new version is introduced to use DMA4 instead (OMAP's). Long term plan is to keep McASP driver totally agnostic of the DMA module (sDMA or eDMA). Change-Id: I47a2fd117b3647a5ed6562cbaa00211cb95dea3a Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Add support for 1-channelMisael Lopez Cruz2013-07-221-2/+2
| | | | | | | | | McASP doesn't support 1-slot TDM mode needed for mono, however mono can still be achieved by using 2-slots (or more) and transferring data only in one slot. Change-Id: Ic8420cf2d6cc1ee9b9c163ab592cfa347a679340 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Pass pin inactive state via DTMisael Lopez Cruz2013-07-224-1/+36
| | | | | | | | | | | | | | | The state of transmit/receive pins during inactive slots can be controlled through DISMOD. Previously, the default state (Hi-Z) was used all the time, but that might not fit well for all applications. So, the inactive state is passed via DT: "tx-inactive-state" and "rx-inactive-state". The inactive states can actually be set per serializer, but for the sake of simplicity we only differentiate them by stream direction. Additionally, the DISMOD macro is also fixed as the argument part was incorrect. Change-Id: I0e099c29fde94dd59175c1017c098554c43d18fe Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Wait until TX AFIFO is not emptyMisael Lopez Cruz2013-07-221-2/+31
| | | | | | | | | Wait until TX AFIFO has at least one audio sample before TXBUF starts consuming data, otherwise XRUN can be hit immediately at the start of the stream. Change-Id: Ie94dcd16f7a00046eb043aec1ceee21ce6009fbc Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Fix receive right-rotation valueMisael Lopez Cruz2013-07-221-3/+8
| | | | | | | | | Receive right-rotation (RROT) for I2S/TDM falls in the MSB-first, left-aligned streams whose suggested rotation value is slot size - word size. Change-Id: I53ac6a0a9c02cf78cc4a2f37c34b6dbc4f9a0bcc Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Keep TX and RX format symmetricMisael Lopez Cruz2013-07-221-27/+17
| | | | | | | | | [TR]XFMT and [TR]XFMTCTL registers are set symmetrically in most part of the driver, no need to keep it stream direction dependent only in one place. Change-Id: I8bacf75c8e5147d086ea67ab8ea5400a6affba99 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
* ASoC: davinci-mcasp: Enable TX FSG for master modeMisael Lopez Cruz2013-07-221-1/+36
| | | | | | | | | | | | | McASP is configured by default in synchronous mode so the TX frame sync is also used for RX. If McASP is also in master mode (for FSYNC), the transmit FSG needs to be running to provide the frame sync needed for RX. In some cases, AFSR/ACLKR pins are not even used so AFSX/ACLKX pins have to be active for RX too, this requires TX clock dividers to be released from reset. Change-Id: Iff0b7b93ed2665b7da8219e435fece512c4551e8 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>