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/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,dra7xx";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
			operating-points = <
				/* kHz    uV */
				/* The OPP_HIGH Only for DVFS enabled Samples */
				/* OPP_OD need to be enabled only for Refreshed poly fixed Samples */
				/* dieID reg: 0x4AE0C20C FT_Rev bits[15:8] should be 5 or more to enable OPP_OD */
				1000000	1090000
				1176000	1210000
				1500000 1280000
				>;
				clocks = <&dpll_mpu_ck>;
				clock-names = "cpu";
				/*
				 * Transition latency reference from omap5.
				 * TBD: to be instrumented and use the actual
				 * value at later point of time
				 */
				clock-latency = <300000>;
			timer {
				compatible = "arm,armv7-timer";
				/*
				 * PPI secure/nonsecure IRQ,
				 * active low level-sensitive
				 */
				interrupts = <1 13 0x308>,
					     <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/*
				 * PPI secure/nonsecure IRQ,
				 * active low level-sensitive
				 */
				interrupts = <1 13 0x308>,
					     <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
		      <0x48212000 0x1000>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the SOC interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2";

		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

		dra7_pmx_core: pinmux@4a003400 {
			compatible = "pinctrl-single";
			reg = <0x4a003400 0x0464>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x3fffffff>;
		};

		dpll_mpu_ck: dpll_mpu_ck {
			#clock-cells = <0>;
			compatible = "ti,omap-clock";
		};

		dpll_gpu_m2_ck: dpll_gpu_m2_ck {
			#clock-cells = <0>;
			compatible = "ti,omap-clock";
		};

		dpll_core_h14x2_ck: dpll_core_h14x2_ck {
			#clock-cells = <0>;
			compatible = "ti,omap-clock";
		};

		dpll_per_h14x2_ck: dpll_per_h14x2_ck {
			#clock-cells = <0>;
			compatible = "ti,omap-clock";
		};

		gpu_core_gclk_mux: gpu_core_gclk_mux {
			#clock-cells = <0>;
			compatible = "ti,omap-clock";
		};

		gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
			#clock-cells = <0>;
			compatible = "ti,omap-clock";
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0 12 0x4>,
				     <0 13 0x4>,
				     <0 14 0x4>,
				     <0 15 0x4>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0 29 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0 35 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0 121 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0 105 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0 106 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap2-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0 37 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap2-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0 38 0x4>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap2-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0 39 0x4>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap2-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0 40 0x4>;
			ti,hwmods = "timer4";
		};

		timer5: timer@48820000 {
			compatible = "ti,omap2-timer";
			reg = <0x48820000 0x80>;
			interrupts = <0 41 0x4>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@48822000 {
			compatible = "ti,omap2-timer";
			reg = <0x48822000 0x80>;
			interrupts = <0 42 0x4>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@48824000 {
			compatible = "ti,omap2-timer";
			reg = <0x48824000 0x80>;
			interrupts = <0 43 0x4>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@48826000 {
			compatible = "ti,omap2-timer";
			reg = <0x48826000 0x80>;
			interrupts = <0 44 0x4>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0 45 0x4>;
			ti,hwmods = "timer9";
		};

		timer10: timer@48086000 {
			compatible = "ti,omap2-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0 46 0x4>;
			ti,hwmods = "timer10";
		};

		timer11: timer@48088000 {
			compatible = "ti,omap2-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0 47 0x4>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		wdt2: wdt@4ae14000 {
			compatible = "ti,omap4-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <0 80 0x4>;
			ti,hwmods = "wd_timer2";
		};

		omap_control_usb1: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a002370 0x4>;
			reg-names = "control_dev_conf", "phy_power_usb";
			ti,type = <2>;
		};

                omap_dwc31: omap_dwc3@48880000 {
                        compatible = "ti,dwc3";
                        ti,hwmods = "usb_otg_ss1";
                        reg = <0x48880000 0x1ff>;
                        interrupts = <0 77 4>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        utmi-mode = <2>;
                        ranges;
                        dwc3@48890000 {
                                compatible = "synopsys,dwc3";
                                reg = <0x48890000 0xcfff>;
                                interrupts = <0 76 4>;
                                usb-phy = <&usb2_phy1>, <&usb3_phy>;
                                tx-fifo-resize;
                                dr_mode = "peripheral";
				maximum-speed = "superspeed";
                        };
                };

		omap_control_usb2: omap-control-usb@4a002e74 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002e74 0x4>,
			      <0x4a0086c0 0x4>;
			reg-names = "ctrl_core_srcomp_north_side", "dummy_reg";
			ti,type = <3>;
		};

		omap_dwc32: omap_dwc3@488c0000 {
                        compatible = "ti,dwc3";
                        ti,hwmods = "usb_otg_ss2";
                        reg = <0x488c0000 0x1ff>;
                        interrupts = <0 92 4>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        utmi-mode = <1>;
                        ranges;
                        dwc3@488d0000 {
                                compatible = "synopsys,dwc3";
                                reg = <0x488d0000 0xcfff>;
                                interrupts = <0 78 4>;
                                usb-phy = <&usb2_phy2>;
                                tx-fifo-resize;
                                dr_mode = "host";
				maximum-speed = "highspeed";
                        };
                };

                ocp2scp {
                        compatible = "ti,omap-ocp2scp";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
                        ti,hwmods = "ocp2scp1";
			usb2_phy1: usb2_phy1@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb1>;
				wkupclk =  "usb_phy1_always_on_clk32k";
				optclk = "usb_otg_ss1_refclk960m";
			};

                        usb3_phy: usb3_phy@4a084400 {
                                compatible = "ti,omap-usb3";
                                reg = <0x4a084400 0x80>,
                                      <0x4a084800 0x64>,
                                      <0x4a084c00 0x40>;
                                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
                                ctrl-module = <&omap_control_usb1>;
				wkupclk =  "usb_phy1_always_on_clk32k";
				optclk = "usb_otg_ss1_refclk960m";
                        };

			usb2_phy2: usb2_phy2@4a085000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a085000 0x7c>;
				ctrl-module = <&omap_control_usb2>;
				wkupclk =  "usb_phy2_always_on_clk32k";
				optclk = "usb_otg_ss2_refclk960m";
			};

                };


		dmm: dmm@4e000000 {
			compatible = "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0 113 0x4>;
			ti,hwmods = "dmm";
		};

		gpu: gpu@0x56000000 {
			compatible = "ti,omap4-gpu";
			reg = <0x56000000 0xffff>;
			interrupts = <0 21 0x4>;
			ti,hwmods = "gpu";
			operating-points = <
				/* kHz    uV */
				425600  1090000
				500000  1210000
				532000  1280000
				>;
			clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>,
					<&dpll_gpu_m2_ck>, <&gpu_core_gclk_mux>,
					<&gpu_hyd_gclk_mux>;
			clock-names = "core", "per", "gpu", "gpu_core", "gpu_hyd";
		};

		bandgap {
			reg = <0x4a0021e0 0xc
				0x4a00232c 0xc
				0x4a002380 0x2c
				0x4a0023C0 0x3c
				0x4a002564 0x8
				0x4a002574 0x50>;
			compatible = "ti,dra752-bandgap";
			interrupts = <0 126 4>; /* talert */
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0 62 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0 60 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <0 83 0x4>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <0 86 0x4>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <0 94 0x4>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <0 96 0x4>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
		};

		avs_mpu: regulator-avs@0x4A003B18 {
			compatible = "ti,avsclass0";
			reg = <0x4A003B18 0x20>;
			efuse-settings = <1090000 8
			1210000 12
			1280000 16>;
			voltage-tolerance = <1>;
		};

		avs_core: regulator-avs@0x4A0025EC {
			compatible = "ti,avsclass0";
			reg = <0x4A0025EC 0x20>;
			efuse-settings = <1030000 8>;
		};

		avs_gpu: regulator-avs@0x4A003B00 {
			compatible = "ti,avsclass0";
			reg = <0x4A003B00 0x20>;
			efuse-settings = <1090000 8
			1210000 12
			1280000 16>;
			voltage-tolerance = <1>;
		};

		avs_dspeve: regulator-avs@0x4A0025D8 {
			compatible = "ti,avsclass0";
			reg = <0x4A0025D8 0x20>;
			efuse-settings = <1055000 8
			1150000 12
			1250000 16>;
		};

		avs_iva: regulator-avs@0x4A0025C4 {
			compatible = "ti,avsclass0";
			reg = <0x4A0025C4 0x20>;
			efuse-settings = <1055000 8
			1150000 12
			1250000 16>;
		};

		dss {
			compatible = "ti,omap4-dss";
			ti,hwmods = "dss_core";
			#address-cells = <1>;
			#size-cells = <0>;
			vdda_video-supply = <&ldoln_reg>;

			dispc {
				compatible = "ti,omap4-dispc";
				ti,hwmods = "dss_dispc";
			};

			dpi1: dpi@1 {
				compatible = "ti,dra7xx-dpi";
				reg = <0>;
				video-source = <0>;
			};

			dpi2: dpi@2 {
				compatible = "ti,dra7xx-dpi";
				reg = <1>;
				video-source = <2>;
			};

			dpi3: dpi@3 {
				compatible = "ti,dra7xx-dpi";
				reg = <2>;
				video-source = <3>;
			};

			hdmi: hdmi {
				compatible = "ti,omap4-hdmi", "simple-bus";
				ti,hwmods = "dss_hdmi";
				vdda_hdmi_dac-supply = <&ldo3_reg>;
				video-source = <1>;
			};
		};

		atl: atl@0x4843c000 {
			compatible = "ti,dra7-atl";
			reg = <0x4843c000 0x3ff>;
			ti,hwmods = "atl";
			ti,atclk1-freq = <11289600>;
			ti,atl1-bws-input = <3>;	/* McASP2 FSX */
			ti,atl1-aws-input = <15>;	/* McASP6 FSX */
			ti,atclk2-freq = <5644800>;
			ti,atl2-bws-input = <3>;	/* McASP2 FSX */
			ti,atl2-aws-input = <4>;	/* McASP3 FSX */
		};

		mcasp3: mcasp@48468000 {
			compatible = "ti,dra7-mcasp-audio";
			reg = <0x48468000 0x2000>;
			interrupts = <0 155 0x4>, /* AREVT */
				     <0 154 0x4>; /* TXEVT */
			ti,hwmods = "mcasp3";
			op-mode = <0>;		/* MCASP_IIS_MODE */
			tdm-slots = <2>;
			num-serializer = <4>;
			serial-dir = <1 2 0 0>;	/* 0:INACTIVE, 1:TX, 2:RX */
			ti,tx-inactive-mode = <2>; /* 0: Hi-Z, 2: Low, 3: High */
			ti,rx-inactive-mode = <2>; /* 0: Hi-Z, 2: Low, 3: High */
		};

		mcasp6: mcasp@48474000 {
			compatible = "ti,dra7-mcasp-audio";
			reg = <0x48474000 0x2000>;
			interrupts = <0 156 0x4>, /* AREVT */
				     <0 157 0x4>; /* TXEVT */
			ti,hwmods = "mcasp6";
			op-mode = <0>;		/* MCASP_IIS_MODE */
			tdm-slots = <8>;
			num-serializer = <4>;
			serial-dir = <1 2 0 0>;	/* 0:INACTIVE, 1:TX, 2:RX */
			ti,tx-inactive-mode = <2>; /* 0: Hi-Z, 2: Low, 3: High */
			ti,rx-inactive-mode = <2>; /* 0: Hi-Z, 2: Low, 3: High */
		};
	};
};