diff options
author | Praneeth Bajjuri | 2013-03-11 15:48:17 -0500 |
---|---|---|
committer | Praneeth Bajjuri | 2013-03-11 15:48:17 -0500 |
commit | 24628a77fb4fab35be1b6eb8f65681e8c599e847 (patch) | |
tree | 6593511b01102d942d0061a7a14084cab3468f93 /arch | |
parent | e7f415eadf62add0340ba59b4f6fcaa8c126da7f (diff) | |
download | kernel-common-24628a77fb4fab35be1b6eb8f65681e8c599e847.tar.gz kernel-common-24628a77fb4fab35be1b6eb8f65681e8c599e847.tar.xz kernel-common-24628a77fb4fab35be1b6eb8f65681e8c599e847.zip |
This reverts commit 6cd07e44352d89c799df8bb0a88a864b15c91c47.
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 3 | ||||
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 71 |
2 files changed, 15 insertions, 59 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 0ca0f5a7c84..3b2c40b5bfa 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h | |||
@@ -66,7 +66,6 @@ | |||
66 | #define L2X0_STNDBY_MODE_EN (1 << 0) | 66 | #define L2X0_STNDBY_MODE_EN (1 << 0) |
67 | 67 | ||
68 | /* Registers shifts and masks */ | 68 | /* Registers shifts and masks */ |
69 | #define L2X0_CACHE_ID_REV_MASK (0x3f) | ||
70 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) | 69 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) |
71 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) | 70 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) |
72 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) | 71 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) |
@@ -107,8 +106,6 @@ | |||
107 | 106 | ||
108 | #define L2X0_WAY_SIZE_SHIFT 3 | 107 | #define L2X0_WAY_SIZE_SHIFT 3 |
109 | 108 | ||
110 | #define REV_PL310_R2P0 4 | ||
111 | |||
112 | #ifndef __ASSEMBLY__ | 109 | #ifndef __ASSEMBLY__ |
113 | extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); | 110 | extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); |
114 | #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) | 111 | #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) |
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a2f0ff7ee71..c2f37390308 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -33,9 +33,6 @@ static void __iomem *l2x0_base; | |||
33 | static DEFINE_RAW_SPINLOCK(l2x0_lock); | 33 | static DEFINE_RAW_SPINLOCK(l2x0_lock); |
34 | static u32 l2x0_way_mask; /* Bitmask of active ways */ | 34 | static u32 l2x0_way_mask; /* Bitmask of active ways */ |
35 | static u32 l2x0_size; | 35 | static u32 l2x0_size; |
36 | static u32 l2x0_cache_id; | ||
37 | static unsigned int l2x0_sets; | ||
38 | static unsigned int l2x0_ways; | ||
39 | static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; | 36 | static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; |
40 | 37 | ||
41 | /* Aurora don't have the cache ID register available, so we have to | 38 | /* Aurora don't have the cache ID register available, so we have to |
@@ -52,13 +49,6 @@ struct l2x0_of_data { | |||
52 | 49 | ||
53 | static bool of_init = false; | 50 | static bool of_init = false; |
54 | 51 | ||
55 | static inline bool is_pl310_rev(int rev) | ||
56 | { | ||
57 | return (l2x0_cache_id & | ||
58 | (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) == | ||
59 | (L2X0_CACHE_ID_PART_L310 | rev); | ||
60 | } | ||
61 | |||
62 | static inline void cache_wait_way(void __iomem *reg, unsigned long mask) | 52 | static inline void cache_wait_way(void __iomem *reg, unsigned long mask) |
63 | { | 53 | { |
64 | /* wait for cache operation by line or way to complete */ | 54 | /* wait for cache operation by line or way to complete */ |
@@ -147,23 +137,6 @@ static void l2x0_cache_sync(void) | |||
147 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | 137 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
148 | } | 138 | } |
149 | 139 | ||
150 | #ifdef CONFIG_PL310_ERRATA_727915 | ||
151 | static void l2x0_for_each_set_way(void __iomem *reg) | ||
152 | { | ||
153 | int set; | ||
154 | int way; | ||
155 | unsigned long flags; | ||
156 | |||
157 | for (way = 0; way < l2x0_ways; way++) { | ||
158 | raw_spin_lock_irqsave(&l2x0_lock, flags); | ||
159 | for (set = 0; set < l2x0_sets; set++) | ||
160 | writel_relaxed((way << 28) | (set << 5), reg); | ||
161 | cache_sync(); | ||
162 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | ||
163 | } | ||
164 | } | ||
165 | #endif | ||
166 | |||
167 | static void __l2x0_flush_all(void) | 140 | static void __l2x0_flush_all(void) |
168 | { | 141 | { |
169 | debug_writel(0x03); | 142 | debug_writel(0x03); |
@@ -177,13 +150,6 @@ static void l2x0_flush_all(void) | |||
177 | { | 150 | { |
178 | unsigned long flags; | 151 | unsigned long flags; |
179 | 152 | ||
180 | #ifdef CONFIG_PL310_ERRATA_727915 | ||
181 | if (is_pl310_rev(REV_PL310_R2P0)) { | ||
182 | l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX); | ||
183 | return; | ||
184 | } | ||
185 | #endif | ||
186 | |||
187 | /* clean all ways */ | 153 | /* clean all ways */ |
188 | raw_spin_lock_irqsave(&l2x0_lock, flags); | 154 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
189 | __l2x0_flush_all(); | 155 | __l2x0_flush_all(); |
@@ -194,20 +160,11 @@ static void l2x0_clean_all(void) | |||
194 | { | 160 | { |
195 | unsigned long flags; | 161 | unsigned long flags; |
196 | 162 | ||
197 | #ifdef CONFIG_PL310_ERRATA_727915 | ||
198 | if (is_pl310_rev(REV_PL310_R2P0)) { | ||
199 | l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX); | ||
200 | return; | ||
201 | } | ||
202 | #endif | ||
203 | |||
204 | /* clean all ways */ | 163 | /* clean all ways */ |
205 | raw_spin_lock_irqsave(&l2x0_lock, flags); | 164 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
206 | debug_writel(0x03); | ||
207 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); | 165 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); |
208 | cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); | 166 | cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); |
209 | cache_sync(); | 167 | cache_sync(); |
210 | debug_writel(0x00); | ||
211 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | 168 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
212 | } | 169 | } |
213 | 170 | ||
@@ -366,27 +323,30 @@ static void l2x0_unlock(u32 cache_id) | |||
366 | void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | 323 | void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) |
367 | { | 324 | { |
368 | u32 aux; | 325 | u32 aux; |
326 | u32 cache_id; | ||
369 | u32 way_size = 0; | 327 | u32 way_size = 0; |
328 | int ways; | ||
370 | int way_size_shift = L2X0_WAY_SIZE_SHIFT; | 329 | int way_size_shift = L2X0_WAY_SIZE_SHIFT; |
371 | const char *type; | 330 | const char *type; |
372 | 331 | ||
373 | l2x0_base = base; | 332 | l2x0_base = base; |
374 | if (cache_id_part_number_from_dt) | 333 | if (cache_id_part_number_from_dt) |
375 | l2x0_cache_id = cache_id_part_number_from_dt; | 334 | cache_id = cache_id_part_number_from_dt; |
376 | else | 335 | else |
377 | l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); | 336 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID) |
337 | & L2X0_CACHE_ID_PART_MASK; | ||
378 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | 338 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
379 | 339 | ||
380 | aux &= aux_mask; | 340 | aux &= aux_mask; |
381 | aux |= aux_val; | 341 | aux |= aux_val; |
382 | 342 | ||
383 | /* Determine the number of ways */ | 343 | /* Determine the number of ways */ |
384 | switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) { | 344 | switch (cache_id) { |
385 | case L2X0_CACHE_ID_PART_L310: | 345 | case L2X0_CACHE_ID_PART_L310: |
386 | if (aux & (1 << 16)) | 346 | if (aux & (1 << 16)) |
387 | l2x0_ways = 16; | 347 | ways = 16; |
388 | else | 348 | else |
389 | l2x0_ways = 8; | 349 | ways = 8; |
390 | type = "L310"; | 350 | type = "L310"; |
391 | #ifdef CONFIG_PL310_ERRATA_753970 | 351 | #ifdef CONFIG_PL310_ERRATA_753970 |
392 | /* Unmapped register. */ | 352 | /* Unmapped register. */ |
@@ -396,7 +356,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
396 | outer_cache.set_debug = pl310_set_debug; | 356 | outer_cache.set_debug = pl310_set_debug; |
397 | break; | 357 | break; |
398 | case L2X0_CACHE_ID_PART_L210: | 358 | case L2X0_CACHE_ID_PART_L210: |
399 | l2x0_ways = (aux >> 13) & 0xf; | 359 | ways = (aux >> 13) & 0xf; |
400 | type = "L210"; | 360 | type = "L210"; |
401 | break; | 361 | break; |
402 | 362 | ||
@@ -409,21 +369,20 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
409 | break; | 369 | break; |
410 | default: | 370 | default: |
411 | /* Assume unknown chips have 8 ways */ | 371 | /* Assume unknown chips have 8 ways */ |
412 | l2x0_ways = 8; | 372 | ways = 8; |
413 | type = "L2x0 series"; | 373 | type = "L2x0 series"; |
414 | break; | 374 | break; |
415 | } | 375 | } |
416 | 376 | ||
417 | l2x0_way_mask = (1 << l2x0_ways) - 1; | 377 | l2x0_way_mask = (1 << ways) - 1; |
418 | 378 | ||
419 | /* | 379 | /* |
420 | * L2 cache Size = Way size * Number of ways | 380 | * L2 cache Size = Way size * Number of ways |
421 | */ | 381 | */ |
422 | way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; | 382 | way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; |
423 | way_size = SZ_1K << (way_size + way_size_shift); | 383 | way_size = 1 << (way_size + way_size_shift); |
424 | 384 | ||
425 | l2x0_size = l2x0_ways * way_size; | 385 | l2x0_size = ways * way_size * SZ_1K; |
426 | l2x0_sets = way_size / CACHE_LINE_SIZE; | ||
427 | 386 | ||
428 | /* | 387 | /* |
429 | * Check if l2x0 controller is already enabled. | 388 | * Check if l2x0 controller is already enabled. |
@@ -432,7 +391,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
432 | */ | 391 | */ |
433 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { | 392 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { |
434 | /* Make sure that I&D is not locked down when starting */ | 393 | /* Make sure that I&D is not locked down when starting */ |
435 | l2x0_unlock(l2x0_cache_id); | 394 | l2x0_unlock(cache_id); |
436 | 395 | ||
437 | /* l2x0 controller is disabled */ | 396 | /* l2x0 controller is disabled */ |
438 | writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); | 397 | writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); |
@@ -461,7 +420,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) | |||
461 | 420 | ||
462 | printk(KERN_INFO "%s cache controller enabled\n", type); | 421 | printk(KERN_INFO "%s cache controller enabled\n", type); |
463 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", | 422 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |
464 | l2x0_ways, l2x0_cache_id, aux, l2x0_size); | 423 | ways, cache_id, aux, l2x0_size); |
465 | } | 424 | } |
466 | 425 | ||
467 | #ifdef CONFIG_OF | 426 | #ifdef CONFIG_OF |