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authorPraneeth Bajjuri2017-02-27 17:38:20 -0600
committerPraneeth Bajjuri2017-02-27 17:38:20 -0600
commitc9973532271123545779b2340f7f068f55ff8387 (patch)
tree2fe3421875fc8c115f8100d79e5a831631779265
parentdcbd717d2b63dd4fbcff91cd7dd8937debb41781 (diff)
downloadkernel-omap-6AM.1.3-rvc-earlyboot.tar.gz
kernel-omap-6AM.1.3-rvc-earlyboot.tar.xz
kernel-omap-6AM.1.3-rvc-earlyboot.zip
earlyboot: reduce dts footprint6AM.1.3-rvc-earlyboot
temp: for benchmarking purpose, reduce dts footprint Change-Id: I8df671274c850aeac45a2ee3c4240d56140ff5c0 Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts595
-rw-r--r--arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi2
-rw-r--r--arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi2
3 files changed, 0 insertions, 599 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 388142161259..9d3b184c1cb9 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -33,20 +33,6 @@
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x0 0x99000000 0x0 0x4000000>;
39 reusable;
40 status = "okay";
41 };
42
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x0 0x9d000000 0x0 0x2000000>;
46 reusable;
47 status = "okay";
48 };
49
50 dsp2_cma_pool: dsp2_cma@9f000000 { 36 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool"; 37 compatible = "shared-dma-pool";
52 reg = <0x0 0x9f000000 0x0 0x800000>; 38 reg = <0x0 0x9f000000 0x0 0x800000>;
@@ -56,11 +42,7 @@
56 }; 42 };
57 43
58 aliases { 44 aliases {
59 display0 = &hdmi0;
60 display1 = &fpd_disp;
61 sound0 = &snd0; 45 sound0 = &snd0;
62 sound1 = &hdmi;
63 i2c7 = &disp_ser;
64 }; 46 };
65 47
66 evm_3v3_sd: fixedregulator-sd { 48 evm_3v3_sd: fixedregulator-sd {
@@ -155,137 +137,9 @@
155 }; 137 };
156 }; 138 };
157 139
158 leds {
159 compatible = "gpio-leds";
160 led@0 {
161 label = "dra7:usr1";
162 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
163 default-state = "off";
164 };
165
166 led@1 {
167 label = "dra7:usr2";
168 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
169 default-state = "off";
170 };
171
172 led@2 {
173 label = "dra7:usr3";
174 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
175 default-state = "off";
176 };
177
178 led@3 {
179 label = "dra7:usr4";
180 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
181 default-state = "off";
182 };
183 };
184
185 gpio_keys {
186 compatible = "gpio-keys";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 autorepeat;
190
191 USER1 {
192 label = "btnUser1";
193 linux,code = <BTN_0>;
194 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
195 };
196
197 USER2 {
198 label = "btnUser2";
199 linux,code = <BTN_1>;
200 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
201 };
202 };
203
204 hdmi0: connector@1 {
205 compatible = "hdmi-connector";
206 label = "hdmi";
207
208 type = "a";
209
210 port {
211 hdmi_connector_in: endpoint {
212 remote-endpoint = <&tpd12s015_out>;
213 };
214 };
215 };
216
217 tpd12s015: encoder@1 {
218 compatible = "ti,dra7evm-tpd12s015";
219
220 pinctrl-names = "i2c", "ddc";
221 pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
222 pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
223
224 ddc-i2c-bus = <&i2c2>;
225 mcasp-gpio = <&mcasp8>;
226
227 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
228 <&pcf_hdmi 5 0>, /* P5, LS OE */
229 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
230
231 ports {
232 #address-cells = <1>;
233 #size-cells = <0>;
234
235 port@0 {
236 reg = <0>;
237
238 tpd12s015_in: endpoint@0 {
239 remote-endpoint = <&hdmi_out>;
240 };
241 };
242
243 port@1 {
244 reg = <1>;
245
246 tpd12s015_out: endpoint@0 {
247 remote-endpoint = <&hdmi_connector_in>;
248 };
249 };
250 };
251 };
252}; 140};
253 141
254&dra7_pmx_core { 142&dra7_pmx_core {
255 dcan1_pins_default: dcan1_pins_default {
256 pinctrl-single,pins = <
257 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
258 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
259 >;
260 };
261
262 dcan1_pins_sleep: dcan1_pins_sleep {
263 pinctrl-single,pins = <
264 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
265 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
266 >;
267 };
268
269 hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
270 pinctrl-single,pins = <
271 /* this pin is used as a GPIO via mcasp */
272 0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
273 >;
274 };
275
276 hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
277 pinctrl-single,pins = <
278 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
279 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
280 >;
281 };
282
283 hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
284 pinctrl-single,pins = <
285 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
286 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
287 >;
288 };
289 143
290 mmc1_pins_default: pinmux_mmc1_default_pins { 144 mmc1_pins_default: pinmux_mmc1_default_pins {
291 pinctrl-single,pins = < 145 pinctrl-single,pins = <
@@ -424,49 +278,6 @@
424 >; 278 >;
425 }; 279 };
426 280
427 mmc4_pins_default: mmc4_pins_default {
428 pinctrl-single,pins = <
429 0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
430 0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
431 0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
432 0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
433 0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
434 0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
435 >;
436 };
437
438 mmc4_pins_hs: mmc4_pins_hs {
439 pinctrl-single,pins = <
440 0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
441 0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
442 0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
443 0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
444 0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
445 0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
446 >;
447 };
448
449 mmc4_pins_sdr12: mmc4_pins_sdr12 {
450 pinctrl-single,pins = <
451 0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
452 0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
453 0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
454 0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
455 0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
456 0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
457 >;
458 };
459
460 mmc4_pins_sdr25: mmc4_pins_sdr25 {
461 pinctrl-single,pins = <
462 0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
463 0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
464 0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
465 0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
466 0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
467 0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
468 >;
469 };
470}; 281};
471 282
472&dra7_iodelay_core { 283&dra7_iodelay_core {
@@ -662,93 +473,6 @@
662 >; 473 >;
663 }; 474 };
664 475
665 mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
666 pinctrl-single,pins = <
667 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
668 0x848 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
669 0x84c (A_DELAY(96) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
670 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
671 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
672 0x870 (A_DELAY(582) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
673 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
674 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
675 0x87c (A_DELAY(391) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
676 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
677 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
678 0x888 (A_DELAY(561) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
679 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
680 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
681 0x894 (A_DELAY(588) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
682 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
683 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
684 >;
685 };
686
687 mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
688 pinctrl-single,pins = <
689 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
690 0x848 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
691 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
692 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
693 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
694 0x870 (A_DELAY(785) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
695 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
696 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
697 0x87c (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
698 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
699 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
700 0x888 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
701 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
702 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
703 0x894 (A_DELAY(835) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
704 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
705 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
706 >;
707 };
708
709 mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
710 pinctrl-single,pins = <
711 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
712 0x848 (A_DELAY(2651) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
713 0x84c (A_DELAY(1572) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
714 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
715 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
716 0x870 (A_DELAY(1913) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
717 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
718 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
719 0x87c (A_DELAY(1721) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
720 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
721 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
722 0x888 (A_DELAY(1891) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
723 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
724 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
725 0x894 (A_DELAY(1919) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
726 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
727 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
728 >;
729 };
730
731 mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
732 pinctrl-single,pins = <
733 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
734 0x848 (A_DELAY(1147) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
735 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
736 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
737 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
738 0x870 (A_DELAY(2165) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
739 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
740 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
741 0x87c (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_RTSN_IN */
742 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
743 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
744 0x888 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_RXD_IN */
745 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
746 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
747 0x894 (A_DELAY(2172) | G_DELAY(44)) /* CFG_UART2_TXD_IN */
748 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
749 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
750 >;
751 };
752}; 476};
753 477
754&i2c1 { 478&i2c1 {
@@ -972,36 +696,6 @@ i2c_p3_exp: &i2c2 {
972 }; 696 };
973 }; 697 };
974 698
975 disp_ser: serializer@1b {
976 compatible = "ti,ds90uh925q";
977 reg = <0x1b>;
978
979 #address-cells = <1>;
980 #size-cells = <0>;
981 ranges = <0x2c 0x2c>,
982 <0x1c 0x1c>;
983
984 disp_des: deserializer@2c {
985 compatible = "ti,ds90uh928q";
986 reg = <0x2c>;
987 slave-mode;
988 };
989
990 /* TLC chip for LCD panel power and backlight */
991 fpd_disp: tlc59108@1c {
992 status = "disabled";
993 reg = <0x1c>;
994 compatible = "ti,tlc59108-fpddisp";
995 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
996 /* P0, SEL_GPMC_AD_VID_S0 */
997
998 port@lcd3 {
999 fpd_in: endpoint {
1000 remote-endpoint = <&dpi_out3>;
1001 };
1002 };
1003 };
1004 };
1005}; 699};
1006 700
1007&i2c3 { 701&i2c3 {
@@ -1009,13 +703,6 @@ i2c_p3_exp: &i2c2 {
1009 clock-frequency = <400000>; 703 clock-frequency = <400000>;
1010}; 704};
1011 705
1012&mcspi1 {
1013 status = "okay";
1014};
1015
1016&mcspi2 {
1017 status = "okay";
1018};
1019 706
1020&uart1 { 707&uart1 {
1021 status = "okay"; 708 status = "okay";
@@ -1023,14 +710,6 @@ i2c_p3_exp: &i2c2 {
1023 <&dra7_pmx_core 0x3e0>; 710 <&dra7_pmx_core 0x3e0>;
1024}; 711};
1025 712
1026&uart2 {
1027 status = "okay";
1028};
1029
1030&uart3 {
1031 status = "okay";
1032};
1033
1034&mmc1 { 713&mmc1 {
1035 status = "okay"; 714 status = "okay";
1036 vmmc-supply = <&evm_3v3_sd>; 715 vmmc-supply = <&evm_3v3_sd>;
@@ -1068,34 +747,6 @@ i2c_p3_exp: &i2c2 {
1068 pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>; 747 pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>;
1069}; 748};
1070 749
1071&mmc4 {
1072 status = "disabled";
1073 vmmc-supply = <&vmmcwl_fixed>;
1074 bus-width = <4>;
1075 cap-power-off-card;
1076 keep-power-in-suspend;
1077 ti,non-removable;
1078
1079 pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
1080 pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
1081 pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
1082 pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
1083 pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
1084 pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
1085 pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
1086 pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
1087 pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
1088
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 wlcore: wlcore@0 {
1092 compatible = "ti,wl1835";
1093 reg = <2>;
1094 interrupt-parent = <&gpio5>;
1095 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
1096 };
1097};
1098
1099&oppdm_mpu { 750&oppdm_mpu {
1100 vdd-supply = <&smps123_reg>; 751 vdd-supply = <&smps123_reg>;
1101}; 752};
@@ -1116,199 +767,11 @@ i2c_p3_exp: &i2c2 {
1116 vdd-supply = <&smps7_reg>; 767 vdd-supply = <&smps7_reg>;
1117}; 768};
1118 769
1119&pcie1_rc {
1120 status = "okay";
1121};
1122
1123&qspi {
1124 status = "okay";
1125
1126 spi-max-frequency = <76800000>;
1127 m25p80@0 {
1128 compatible = "s25fl256s1";
1129 spi-max-frequency = <76800000>;
1130 reg = <0>;
1131 spi-tx-bus-width = <1>;
1132 spi-rx-bus-width = <4>;
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135
1136 /* MTD partition table.
1137 * The ROM checks the first four physical blocks
1138 * for a valid file to boot and the flash here is
1139 * 64KiB block size.
1140 */
1141 partition@0 {
1142 label = "QSPI.SPL";
1143 reg = <0x00000000 0x000040000>;
1144 };
1145 partition@1 {
1146 label = "QSPI.u-boot";
1147 reg = <0x00040000 0x00100000>;
1148 };
1149 partition@2 {
1150 label = "QSPI.u-boot-spl-os";
1151 reg = <0x00140000 0x00080000>;
1152 };
1153 partition@3 {
1154 label = "QSPI.u-boot-env";
1155 reg = <0x001c0000 0x00010000>;
1156 };
1157 partition@4 {
1158 label = "QSPI.u-boot-env.backup1";
1159 reg = <0x001d0000 0x0010000>;
1160 };
1161 partition@5 {
1162 label = "QSPI.kernel";
1163 reg = <0x001e0000 0x0800000>;
1164 };
1165 partition@6 {
1166 label = "QSPI.file-system";
1167 reg = <0x009e0000 0x01620000>;
1168 };
1169 };
1170};
1171
1172&omap_dwc3_1 {
1173 extcon = <&extcon_usb1>;
1174};
1175
1176&omap_dwc3_2 {
1177 extcon = <&extcon_usb2>;
1178};
1179
1180&usb1 {
1181 dr_mode = "otg";
1182};
1183
1184&usb2 {
1185 dr_mode = "host";
1186};
1187
1188&elm {
1189 status = "okay";
1190};
1191
1192&gpmc {
1193 status = "okay";
1194 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
1195 nand@0,0 {
1196 compatible = "ti,omap2-nand";
1197 reg = <0 0 4>; /* device IO registers */
1198 interrupt-parent = <&gpmc>;
1199 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
1200 <1 IRQ_TYPE_NONE>; /* termcount */
1201 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
1202 ti,nand-ecc-opt = "bch8";
1203 ti,elm-id = <&elm>;
1204 nand-bus-width = <16>;
1205 gpmc,device-width = <2>;
1206 gpmc,sync-clk-ps = <0>;
1207 gpmc,cs-on-ns = <0>;
1208 gpmc,cs-rd-off-ns = <80>;
1209 gpmc,cs-wr-off-ns = <80>;
1210 gpmc,adv-on-ns = <0>;
1211 gpmc,adv-rd-off-ns = <60>;
1212 gpmc,adv-wr-off-ns = <60>;
1213 gpmc,we-on-ns = <10>;
1214 gpmc,we-off-ns = <50>;
1215 gpmc,oe-on-ns = <4>;
1216 gpmc,oe-off-ns = <40>;
1217 gpmc,access-ns = <40>;
1218 gpmc,wr-access-ns = <80>;
1219 gpmc,rd-cycle-ns = <80>;
1220 gpmc,wr-cycle-ns = <80>;
1221 gpmc,bus-turnaround-ns = <0>;
1222 gpmc,cycle2cycle-delay-ns = <0>;
1223 gpmc,clk-activation-ns = <0>;
1224 gpmc,wr-data-mux-bus-ns = <0>;
1225 /* MTD partition table */
1226 /* All SPL-* partitions are sized to minimal length
1227 * which can be independently programmable. For
1228 * NAND flash this is equal to size of erase-block */
1229 #address-cells = <1>;
1230 #size-cells = <1>;
1231 partition@0 {
1232 label = "NAND.SPL";
1233 reg = <0x00000000 0x000020000>;
1234 };
1235 partition@1 {
1236 label = "NAND.SPL.backup1";
1237 reg = <0x00020000 0x00020000>;
1238 };
1239 partition@2 {
1240 label = "NAND.SPL.backup2";
1241 reg = <0x00040000 0x00020000>;
1242 };
1243 partition@3 {
1244 label = "NAND.SPL.backup3";
1245 reg = <0x00060000 0x00020000>;
1246 };
1247 partition@4 {
1248 label = "NAND.u-boot-spl-os";
1249 reg = <0x00080000 0x00040000>;
1250 };
1251 partition@5 {
1252 label = "NAND.u-boot";
1253 reg = <0x000c0000 0x00100000>;
1254 };
1255 partition@6 {
1256 label = "NAND.u-boot-env";
1257 reg = <0x001c0000 0x00020000>;
1258 };
1259 partition@7 {
1260 label = "NAND.u-boot-env.backup1";
1261 reg = <0x001e0000 0x00020000>;
1262 };
1263 partition@8 {
1264 label = "NAND.kernel";
1265 reg = <0x00200000 0x00800000>;
1266 };
1267 partition@9 {
1268 label = "NAND.file-system";
1269 reg = <0x00a00000 0x0f600000>;
1270 };
1271 };
1272};
1273
1274&usb2_phy1 {
1275 phy-supply = <&ldousb_reg>;
1276};
1277
1278&usb2_phy2 {
1279 phy-supply = <&ldousb_reg>;
1280};
1281
1282&gpio7 { 770&gpio7 {
1283 ti,no-reset-on-init; 771 ti,no-reset-on-init;
1284 ti,no-idle-on-init; 772 ti,no-idle-on-init;
1285}; 773};
1286 774
1287&mac {
1288 status = "okay";
1289 dual_emac;
1290};
1291
1292&cpsw_emac0 {
1293 phy_id = <&davinci_mdio>, <2>;
1294 phy-mode = "rgmii";
1295 dual_emac_res_vlan = <1>;
1296};
1297
1298&cpsw_emac1 {
1299 phy_id = <&davinci_mdio>, <3>;
1300 phy-mode = "rgmii";
1301 dual_emac_res_vlan = <2>;
1302};
1303
1304&dcan1 {
1305 status = "ok";
1306 pinctrl-names = "default", "sleep", "active";
1307 pinctrl-0 = <&dcan1_pins_sleep>;
1308 pinctrl-1 = <&dcan1_pins_sleep>;
1309 pinctrl-2 = <&dcan1_pins_default>;
1310};
1311
1312&atl { 775&atl {
1313 assigned-clocks = <&abe_dpll_sys_clk_mux>, 776 assigned-clocks = <&abe_dpll_sys_clk_mux>,
1314 <&atl_gfclk_mux>, 777 <&atl_gfclk_mux>,
@@ -1346,11 +809,6 @@ i2c_p3_exp: &i2c2 {
1346 rx-num-evt = <32>; 809 rx-num-evt = <32>;
1347}; 810};
1348 811
1349&mcasp8 {
1350 /* not used for audio. only the AXR2 pin is used as GPIO */
1351 status = "okay";
1352};
1353
1354&mailbox5 { 812&mailbox5 {
1355 status = "okay"; 813 status = "okay";
1356 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 814 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
@@ -1375,10 +833,6 @@ i2c_p3_exp: &i2c2 {
1375 status = "okay"; 833 status = "okay";
1376}; 834};
1377 835
1378&mmu1_dsp1 {
1379 status = "okay";
1380};
1381
1382&mmu0_dsp2 { 836&mmu0_dsp2 {
1383 status = "okay"; 837 status = "okay";
1384}; 838};
@@ -1387,10 +841,6 @@ i2c_p3_exp: &i2c2 {
1387 status = "okay"; 841 status = "okay";
1388}; 842};
1389 843
1390&mmu_ipu1 {
1391 status = "okay";
1392};
1393
1394&mmu_ipu2 { 844&mmu_ipu2 {
1395 status = "okay"; 845 status = "okay";
1396}; 846};
@@ -1403,22 +853,6 @@ i2c_p3_exp: &i2c2 {
1403 watchdog-timers = <&timer4>, <&timer9>; 853 watchdog-timers = <&timer4>, <&timer9>;
1404}; 854};
1405 855
1406&ipu1 {
1407 status = "okay";
1408 memory-region = <&ipu1_cma_pool>;
1409 mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
1410 timers = <&timer11>;
1411 watchdog-timers = <&timer7>, <&timer8>;
1412};
1413
1414&dsp1 {
1415 status = "okay";
1416 memory-region = <&dsp1_cma_pool>;
1417 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
1418 timers = <&timer5>;
1419 watchdog-timers = <&timer10>;
1420};
1421
1422&dsp2 { 856&dsp2 {
1423 status = "okay"; 857 status = "okay";
1424 memory-region = <&dsp2_cma_pool>; 858 memory-region = <&dsp2_cma_pool>;
@@ -1431,35 +865,6 @@ i2c_p3_exp: &i2c2 {
1431 865
1432 vdda_video-supply = <&ldoln_reg>; 866 vdda_video-supply = <&ldoln_reg>;
1433 867
1434 ports {
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1437 status = "disabled";
1438
1439 port@lcd3 {
1440 reg = <2>;
1441
1442 dpi_out3: endpoint {
1443 remote-endpoint = <&fpd_in>;
1444 data-lines = <24>;
1445 };
1446 };
1447 };
1448};
1449
1450&bb2d {
1451 status = "okay";
1452};
1453
1454&hdmi {
1455 status = "ok";
1456 vdda-supply = <&ldo3_reg>;
1457
1458 port {
1459 hdmi_out: endpoint {
1460 remote-endpoint = <&tpd12s015_in>;
1461 };
1462 };
1463}; 868};
1464 869
1465&vip1 { 870&vip1 {
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
index 97939eef7b94..e254dccd13a3 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
@@ -11,8 +11,6 @@
11/ { 11/ {
12 aliases { 12 aliases {
13 display0 = &tlc59108; 13 display0 = &tlc59108;
14 display1 = &hdmi0;
15 display2 = &fpd_disp;
16 }; 14 };
17 15
18 backlight { 16 backlight {
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
index 219e4f953797..66c3e3ec03aa 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
@@ -9,8 +9,6 @@
9/ { 9/ {
10 aliases { 10 aliases {
11 display0 = &lcd; 11 display0 = &lcd;
12 display1 = &hdmi0;
13 display2 = &fpd_disp;
14 }; 12 };
15 13
16 lcd_bl: backlight { 14 lcd_bl: backlight {
generated by cgit v1.2.3 (git 2.39.2)