diff options
author | Venkateswara Rao Mandela | 2017-02-11 03:28:00 -0600 |
---|---|---|
committer | Praneeth Bajjuri | 2017-08-28 14:45:28 -0500 |
commit | 132bd80f0fea7fb228fb956f1a35d5af8a7bf879 (patch) | |
tree | 4f94be333c6e3ab8f99d7cd80b7032205a9341a1 | |
parent | fbcd300a81997dbdd71a40468551edbaa8fa0d2a (diff) | |
download | kernel-omap-132bd80f0fea7fb228fb956f1a35d5af8a7bf879.tar.gz kernel-omap-132bd80f0fea7fb228fb956f1a35d5af8a7bf879.tar.xz kernel-omap-132bd80f0fea7fb228fb956f1a35d5af8a7bf879.zip |
OMAPDSS: Work around to check that dispc channel is enabled from A15
Fix warnings caused by DSS driver checking the DSS registers instead
of internal data structures. Checking DSS registers works fine when
DSS is controlled by A15. When DSS control is shared with another core
e.g. M4, there is a mismatch between the DSS driver state and the
register values causing a few warnings.
This commit adds a check based on driver internal state to some
control flow paths to remove the warnings.
Change-Id: Idc9227df525ed138a1a5d18d3d49619427f97551
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Buddy Liong <a0270631@ti.com>
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_crtc.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_drv.h | 2 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index f841edf14bac..ef4f49803966 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c | |||
@@ -158,11 +158,13 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |||
158 | int ret; | 158 | int ret; |
159 | 159 | ||
160 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { | 160 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { |
161 | priv->channel_status[channel] = true; | ||
161 | priv->dispc_ops->mgr_enable(channel, enable); | 162 | priv->dispc_ops->mgr_enable(channel, enable); |
162 | return; | 163 | return; |
163 | } | 164 | } |
164 | 165 | ||
165 | if (priv->dispc_ops->mgr_is_enabled(channel) == enable) | 166 | if (priv->channel_status[omap_crtc->channel] && |
167 | priv->dispc_ops->mgr_is_enabled(omap_crtc->channel)) | ||
166 | return; | 168 | return; |
167 | 169 | ||
168 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { | 170 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
@@ -194,6 +196,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) | |||
194 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | 196 | wait = omap_irq_wait_init(dev, vsync_irq, 2); |
195 | } | 197 | } |
196 | 198 | ||
199 | priv->channel_status[channel] = true; | ||
197 | priv->dispc_ops->mgr_enable(channel, enable); | 200 | priv->dispc_ops->mgr_enable(channel, enable); |
198 | 201 | ||
199 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | 202 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); |
@@ -505,7 +508,8 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, | |||
505 | priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length); | 508 | priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length); |
506 | } | 509 | } |
507 | 510 | ||
508 | if (priv->dispc_ops->mgr_is_enabled(omap_crtc->channel)) { | 511 | if (priv->channel_status[omap_crtc->channel] && |
512 | priv->dispc_ops->mgr_is_enabled(omap_crtc->channel)) { | ||
509 | 513 | ||
510 | DBG("%s: GO", omap_crtc->name); | 514 | DBG("%s: GO", omap_crtc->name); |
511 | 515 | ||
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 5c516d2ee8f3..6ebe480e7038 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h | |||
@@ -90,6 +90,8 @@ struct omap_drm_private { | |||
90 | 90 | ||
91 | struct workqueue_struct *wq; | 91 | struct workqueue_struct *wq; |
92 | 92 | ||
93 | unsigned int channel_status[8]; | ||
94 | |||
93 | /* lock for obj_list below */ | 95 | /* lock for obj_list below */ |
94 | spinlock_t list_lock; | 96 | spinlock_t list_lock; |
95 | 97 | ||