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authorSekhar Nori2017-08-23 10:22:22 -0500
committerJean-Jacques Hiblot2017-08-24 08:39:20 -0500
commit9d06eec9f0055b001e2f4cdcd5e207753883a175 (patch)
tree83bc69c79d3bc896b497015ffbb8af0b949676e0
parent5ff61a1fd2844e094f9e9d37892d67235bf36112 (diff)
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ARM: dts: dra76-evm: shift to using common IOdelay data
Now that we have a device-tree include file with common MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree file to using that. Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
-rw-r--r--arch/arm/boot/dts/dra76-evm.dts41
1 files changed, 1 insertions, 40 deletions
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index f0c7666649c1..873783edce71 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -9,6 +9,7 @@
9 9
10#include "dra76x.dtsi" 10#include "dra76x.dtsi"
11#include "dra7-evm-common.dtsi" 11#include "dra7-evm-common.dtsi"
12#include "dra76x-mmc-iodelay.dtsi"
12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/net/ti-dp83867.h>
13 14
14/ { 15/ {
@@ -134,46 +135,6 @@
134 }; 135 };
135}; 136};
136 137
137&dra7_pmx_core {
138 mmc1_pins_default: mmc1_pins_default {
139 pinctrl-single,pins = <
140 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
141 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
142 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
143 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
144 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
145 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
146 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
147 >;
148 };
149
150 mmc2_pins_default: mmc2_pins_default {
151 pinctrl-single,pins = <
152 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
153 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
154 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
155 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
156 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
157 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
158 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
159 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
160 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
161 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
162 >;
163 };
164
165 mmc4_pins_default: mmc4_pins_default {
166 pinctrl-single,pins = <
167 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
168 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
169 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
170 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
171 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
172 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
173 >;
174 };
175};
176
177&i2c1 { 138&i2c1 {
178 status = "okay"; 139 status = "okay";
179 clock-frequency = <400000>; 140 clock-frequency = <400000>;