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authorStephane Eranian2015-12-03 16:33:17 -0600
committerGreg Kroah-Hartman2017-08-24 19:02:36 -0500
commitce1b98a30571b1022d6ce86d9876a7a7dbf9aed5 (patch)
tree8d54d3a4c5ac099b5a320f38df2410103b2bd0cd
parentb4cf49024cf412a94121e61f8056636c557ead98 (diff)
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perf/x86: Fix LBR related crashes on Intel Atom
commit 6fc2e83077b05a061afe9b24f2fdff7a0434eb67 upstream. This patches fixes the LBR kernel crashes on Intel Atom. The kernel was assuming that if the CPU supports 64-bit format LBR, then it has an LBR_SELECT MSR. Atom uses 64-bit LBR format but does not have LBR_SELECT. That was causing NULL pointer dereferences in a couple of places. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: kan.liang@intel.com Fixes: 96f3eda67fcf ("perf/x86/intel: Fix static checker warning in lbr enable") Link: http://lkml.kernel.org/r/1449182000-31524-2-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Denys Zagorui <dzagorui@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_lbr.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 8900400230c6..2cdae69d7e0b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -153,7 +153,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
153 */ 153 */
154 if (cpuc->lbr_sel) 154 if (cpuc->lbr_sel)
155 lbr_select = cpuc->lbr_sel->config; 155 lbr_select = cpuc->lbr_sel->config;
156 if (!pmi) 156 if (!pmi && cpuc->lbr_sel)
157 wrmsrl(MSR_LBR_SELECT, lbr_select); 157 wrmsrl(MSR_LBR_SELECT, lbr_select);
158 158
159 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 159 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
@@ -432,8 +432,10 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
432 int out = 0; 432 int out = 0;
433 int num = x86_pmu.lbr_nr; 433 int num = x86_pmu.lbr_nr;
434 434
435 if (cpuc->lbr_sel->config & LBR_CALL_STACK) 435 if (cpuc->lbr_sel) {
436 num = tos; 436 if (cpuc->lbr_sel->config & LBR_CALL_STACK)
437 num = tos;
438 }
437 439
438 for (i = 0; i < num; i++) { 440 for (i = 0; i < num; i++) {
439 unsigned long lbr_idx = (tos - i) & mask; 441 unsigned long lbr_idx = (tos - i) & mask;