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authorTomi Valkeinen2018-02-05 09:54:17 -0600
committerJean-Jacques Hiblot2018-02-19 05:09:43 -0600
commitfdd1391eb0aba35cd119154aa44cdf4d5e4d4ee6 (patch)
treec8a1a033872e5078778d23e74a60eb5bc75db8d3
parente1821ed52a9522f29e5fd98983e9b9f0f45adf74 (diff)
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drm/omap: cleanup color space conversion
commit 3c75f993b65f46e3aea99b9c51866d0b7335092b ti-linux-4.9.y The setup code for color space conversion is a bit messy. This patch cleans it up. For some reason the TRM uses values in YCrCb order, which is also used in the current driver, whereas everywhere else it's YCbCr (which also matches YUV order). This patch changes the tables to use the common order to avoid confusion. The tables are split into separate lines, and comments added for clarity. WB color conversion registers are similar but different than non-WB, but the same function was used to write both. It worked fine because the coef table was adjusted accordingly, but that was rather confusing. This patch adds a separate function to write the WB values so that the coef table can be written in an understandable way. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c59
1 files changed, 44 insertions, 15 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 0be137b5e958..7ac170e9c360 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -294,11 +294,6 @@ static const struct {
294 }, 294 },
295}; 295};
296 296
297struct color_conv_coef {
298 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
299 int full_range;
300};
301
302static unsigned long dispc_fclk_rate(void); 297static unsigned long dispc_fclk_rate(void);
303static unsigned long dispc_core_clk_rate(void); 298static unsigned long dispc_core_clk_rate(void);
304static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 299static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
@@ -741,9 +736,18 @@ static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
741 } 736 }
742} 737}
743 738
739struct csc_coef_yuv2rgb {
740 int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr;
741 bool full_range;
742};
743
744struct csc_coef_rgb2yuv {
745 int yr, yg, yb, cbr, cbg, cbb, crr, crg, crb;
746 bool full_range;
747};
744 748
745static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, 749static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
746 const struct color_conv_coef *ct) 750 const struct csc_coef_yuv2rgb *ct)
747{ 751{
748#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 752#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
749 753
@@ -753,7 +757,24 @@ static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
753 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 757 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
754 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 758 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
755 759
756 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 760 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), !!ct->full_range, 11, 11);
761
762#undef CVAL
763}
764
765static void dispc_wb_write_color_conv_coef(const struct csc_coef_rgb2yuv *ct)
766{
767 const enum omap_plane plane = OMAP_DSS_WB;
768
769#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
770
771 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr));
772 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb));
773 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg));
774 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr));
775 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb));
776
777 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), !!ct->full_range, 11, 11);
757 778
758#undef CVAL 779#undef CVAL
759} 780}
@@ -762,20 +783,28 @@ static void dispc_setup_color_conv_coef(void)
762{ 783{
763 int i; 784 int i;
764 int num_ovl = dss_feat_get_num_ovls(); 785 int num_ovl = dss_feat_get_num_ovls();
765 const struct color_conv_coef ctbl_bt601_5_ovl = { 786
766 /* YUV -> RGB */ 787 /* YUV -> RGB, ITU-R BT.601, limited range */
767 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, 788 const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = {
789 298, 0, 409, /* ry, rcb, rcr */
790 298, -100, -208, /* gy, gcb, gcr */
791 298, 516, 0, /* by, bcb, bcr */
792 false, /* limited range */
768 }; 793 };
769 const struct color_conv_coef ctbl_bt601_5_wb = { 794
770 /* RGB -> YUV */ 795 /* RGB -> YUV, ITU-R BT.601, limited range */
771 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, 796 const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = {
797 66, 129, 25, /* yr, yg, yb */
798 -38, -74, 112, /* cbr, cbg, cbb */
799 112, -94, -18, /* crr, crg, crb */
800 false, /* limited range */
772 }; 801 };
773 802
774 for (i = 1; i < num_ovl; i++) 803 for (i = 1; i < num_ovl; i++)
775 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); 804 dispc_ovl_write_color_conv_coef(i, &coefs_yuv2rgb_bt601_lim);
776 805
777 if (dispc.feat->has_writeback) 806 if (dispc.feat->has_writeback)
778 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 807 dispc_wb_write_color_conv_coef(&coefs_rgb2yuv_bt601_lim);
779} 808}
780 809
781static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) 810static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)