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authorLinus Torvalds2012-01-10 19:39:40 -0600
committerLinus Torvalds2012-01-10 19:39:40 -0600
commit06792c4dde2ad143928cc95c1ba218c6269c494b (patch)
tree92bdd4631612c9e3d8e5f6f06839f75c5473300a
parent4690dfa8cd66c37fbe99bb8cd5baa86102110776 (diff)
parent166c0eaedfc3157dc1394c27e827add19f05fb27 (diff)
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Merge tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
* tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: (29 commits) C6X: replace tick_nohz_stop/restart_sched_tick calls C6X: add register_cpu call C6X: deal with memblock API changes C6X: fix timer64 initialization C6X: fix layout of EMIFA registers C6X: MAINTAINERS C6X: DSCR - Device State Configuration Registers C6X: EMIF - External Memory Interface C6X: general SoC support C6X: library code C6X: headers C6X: ptrace support C6X: loadable module support C6X: cache control C6X: clocks C6X: build infrastructure C6X: syscalls C6X: interrupt handling C6X: time management C6X: signal management ...
-rw-r--r--Documentation/devicetree/bindings/c6x/clocks.txt40
-rw-r--r--Documentation/devicetree/bindings/c6x/dscr.txt127
-rw-r--r--Documentation/devicetree/bindings/c6x/emifa.txt62
-rw-r--r--Documentation/devicetree/bindings/c6x/interrupt.txt104
-rw-r--r--Documentation/devicetree/bindings/c6x/soc.txt28
-rw-r--r--Documentation/devicetree/bindings/c6x/timer64.txt26
-rw-r--r--MAINTAINERS8
-rw-r--r--arch/c6x/Kconfig174
-rw-r--r--arch/c6x/Makefile60
-rw-r--r--arch/c6x/boot/Makefile30
-rw-r--r--arch/c6x/boot/dts/dsk6455.dts62
-rw-r--r--arch/c6x/boot/dts/evmc6457.dts48
-rw-r--r--arch/c6x/boot/dts/evmc6472.dts73
-rw-r--r--arch/c6x/boot/dts/evmc6474.dts58
-rw-r--r--arch/c6x/boot/dts/tms320c6455.dtsi96
-rw-r--r--arch/c6x/boot/dts/tms320c6457.dtsi68
-rw-r--r--arch/c6x/boot/dts/tms320c6472.dtsi134
-rw-r--r--arch/c6x/boot/dts/tms320c6474.dtsi89
-rw-r--r--arch/c6x/boot/linked_dtb.S2
-rw-r--r--arch/c6x/configs/dsk6455_defconfig44
-rw-r--r--arch/c6x/configs/evmc6457_defconfig41
-rw-r--r--arch/c6x/configs/evmc6472_defconfig42
-rw-r--r--arch/c6x/configs/evmc6474_defconfig42
-rw-r--r--arch/c6x/include/asm/Kbuild54
-rw-r--r--arch/c6x/include/asm/asm-offsets.h1
-rw-r--r--arch/c6x/include/asm/bitops.h105
-rw-r--r--arch/c6x/include/asm/byteorder.h12
-rw-r--r--arch/c6x/include/asm/cache.h90
-rw-r--r--arch/c6x/include/asm/cacheflush.h65
-rw-r--r--arch/c6x/include/asm/checksum.h34
-rw-r--r--arch/c6x/include/asm/clkdev.h22
-rw-r--r--arch/c6x/include/asm/clock.h148
-rw-r--r--arch/c6x/include/asm/delay.h67
-rw-r--r--arch/c6x/include/asm/dma-mapping.h91
-rw-r--r--arch/c6x/include/asm/dscr.h34
-rw-r--r--arch/c6x/include/asm/elf.h113
-rw-r--r--arch/c6x/include/asm/ftrace.h6
-rw-r--r--arch/c6x/include/asm/hardirq.h20
-rw-r--r--arch/c6x/include/asm/irq.h302
-rw-r--r--arch/c6x/include/asm/irqflags.h72
-rw-r--r--arch/c6x/include/asm/linkage.h30
-rw-r--r--arch/c6x/include/asm/megamod-pic.h9
-rw-r--r--arch/c6x/include/asm/mmu.h18
-rw-r--r--arch/c6x/include/asm/module.h33
-rw-r--r--arch/c6x/include/asm/mutex.h6
-rw-r--r--arch/c6x/include/asm/page.h11
-rw-r--r--arch/c6x/include/asm/pgtable.h81
-rw-r--r--arch/c6x/include/asm/processor.h132
-rw-r--r--arch/c6x/include/asm/procinfo.h28
-rw-r--r--arch/c6x/include/asm/prom.h1
-rw-r--r--arch/c6x/include/asm/ptrace.h174
-rw-r--r--arch/c6x/include/asm/sections.h12
-rw-r--r--arch/c6x/include/asm/setup.h32
-rw-r--r--arch/c6x/include/asm/sigcontext.h80
-rw-r--r--arch/c6x/include/asm/signal.h17
-rw-r--r--arch/c6x/include/asm/soc.h35
-rw-r--r--arch/c6x/include/asm/string.h21
-rw-r--r--arch/c6x/include/asm/swab.h54
-rw-r--r--arch/c6x/include/asm/syscall.h123
-rw-r--r--arch/c6x/include/asm/syscalls.h55
-rw-r--r--arch/c6x/include/asm/system.h168
-rw-r--r--arch/c6x/include/asm/thread_info.h121
-rw-r--r--arch/c6x/include/asm/timer64.h6
-rw-r--r--arch/c6x/include/asm/timex.h33
-rw-r--r--arch/c6x/include/asm/tlb.h8
-rw-r--r--arch/c6x/include/asm/traps.h36
-rw-r--r--arch/c6x/include/asm/uaccess.h107
-rw-r--r--arch/c6x/include/asm/unaligned.h170
-rw-r--r--arch/c6x/include/asm/unistd.h26
-rw-r--r--arch/c6x/kernel/Makefile12
-rw-r--r--arch/c6x/kernel/asm-offsets.c123
-rw-r--r--arch/c6x/kernel/c6x_ksyms.c66
-rw-r--r--arch/c6x/kernel/devicetree.c53
-rw-r--r--arch/c6x/kernel/dma.c153
-rw-r--r--arch/c6x/kernel/entry.S803
-rw-r--r--arch/c6x/kernel/head.S84
-rw-r--r--arch/c6x/kernel/irq.c728
-rw-r--r--arch/c6x/kernel/module.c123
-rw-r--r--arch/c6x/kernel/process.c265
-rw-r--r--arch/c6x/kernel/ptrace.c187
-rw-r--r--arch/c6x/kernel/setup.c510
-rw-r--r--arch/c6x/kernel/signal.c377
-rw-r--r--arch/c6x/kernel/soc.c91
-rw-r--r--arch/c6x/kernel/switch_to.S74
-rw-r--r--arch/c6x/kernel/sys_c6x.c74
-rw-r--r--arch/c6x/kernel/time.c65
-rw-r--r--arch/c6x/kernel/traps.c423
-rw-r--r--arch/c6x/kernel/vectors.S81
-rw-r--r--arch/c6x/kernel/vmlinux.lds.S162
-rw-r--r--arch/c6x/lib/Makefile7
-rw-r--r--arch/c6x/lib/checksum.c36
-rw-r--r--arch/c6x/lib/csum_64plus.S419
-rw-r--r--arch/c6x/lib/divi.S53
-rw-r--r--arch/c6x/lib/divremi.S46
-rw-r--r--arch/c6x/lib/divremu.S87
-rw-r--r--arch/c6x/lib/divu.S98
-rw-r--r--arch/c6x/lib/llshl.S37
-rw-r--r--arch/c6x/lib/llshr.S38
-rw-r--r--arch/c6x/lib/llshru.S38
-rw-r--r--arch/c6x/lib/memcpy_64plus.S46
-rw-r--r--arch/c6x/lib/mpyll.S49
-rw-r--r--arch/c6x/lib/negll.S31
-rw-r--r--arch/c6x/lib/pop_rts.S32
-rw-r--r--arch/c6x/lib/push_rts.S31
-rw-r--r--arch/c6x/lib/remi.S64
-rw-r--r--arch/c6x/lib/remu.S82
-rw-r--r--arch/c6x/lib/strasgi.S89
-rw-r--r--arch/c6x/lib/strasgi_64plus.S39
-rw-r--r--arch/c6x/mm/Makefile5
-rw-r--r--arch/c6x/mm/dma-coherent.c143
-rw-r--r--arch/c6x/mm/init.c113
-rw-r--r--arch/c6x/platforms/Kconfig16
-rw-r--r--arch/c6x/platforms/Makefile12
-rw-r--r--arch/c6x/platforms/cache.c445
-rw-r--r--arch/c6x/platforms/dscr.c598
-rw-r--r--arch/c6x/platforms/emif.c87
-rw-r--r--arch/c6x/platforms/megamod-pic.c349
-rw-r--r--arch/c6x/platforms/platform.c17
-rw-r--r--arch/c6x/platforms/pll.c444
-rw-r--r--arch/c6x/platforms/plldata.c404
-rw-r--r--arch/c6x/platforms/timer64.c244
-rw-r--r--include/asm-generic/io.h2
-rw-r--r--include/asm-generic/page.h10
-rw-r--r--include/asm-generic/uaccess.h7
-rw-r--r--include/linux/elf-em.h1
125 files changed, 12989 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt
new file mode 100644
index 000000000000..a04f5fd30122
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/clocks.txt
@@ -0,0 +1,40 @@
1C6X PLL Clock Controllers
2-------------------------
3
4This is a first-cut support for the SoC clock controllers. This is still
5under development and will probably change as the common device tree
6clock support is added to the kernel.
7
8Required properties:
9
10- compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
12 in the driver. One of:
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
17
18- reg: base address and size of register area
19- clock-frequency: input clock frequency in hz
20
21
22Optional properties:
23
24- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
25
26- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
27
28- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
29
30Example:
31
32 clock-controller@29a0000 {
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
34 reg = <0x029a0000 0x200>;
35 clock-frequency = <25000000>;
36
37 ti,c64x+pll-bypass-delay = <200>;
38 ti,c64x+pll-reset-delay = <12000>;
39 ti,c64x+pll-lock-delay = <80000>;
40 };
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt
new file mode 100644
index 000000000000..d847758f2b20
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/dscr.txt
@@ -0,0 +1,127 @@
1Device State Configuration Registers
2------------------------------------
3
4TI C6X SoCs contain a region of miscellaneous registers which provide various
5function for SoC control or status. Details vary considerably among from SoC
6to SoC with no two being alike.
7
8In general, the Device State Configuraion Registers (DSCR) will provide one or
9more configuration registers often protected by a lock register where one or
10more key values must be written to a lock register in order to unlock the
11configuration register for writes. These configuration register may be used to
12enable (and disable in some cases) SoC pin drivers, select peripheral clock
13sources (internal or pin), etc. In some cases, a configuration register is
14write once or the individual bits are write once. In addition to device config,
15the DSCR block may provide registers which which are used to reset peripherals,
16provide device ID information, provide ethernet MAC addresses, as well as other
17miscellaneous functions.
18
19For device state control (enable/disable), each device control is assigned an
20id which is used by individual device drivers to control the state as needed.
21
22Required properties:
23
24- compatible: must be "ti,c64x+dscr"
25- reg: register area base and size
26
27Optional properties:
28
29 NOTE: These are optional in that not all SoCs will have all properties. For
30 SoCs which do support a given property, leaving the property out of the
31 device tree will result in reduced functionality or possibly driver
32 failure.
33
34- ti,dscr-devstat
35 offset of the devstat register
36
37- ti,dscr-silicon-rev
38 offset, start bit, and bitsize of silicon revision field
39
40- ti,dscr-rmii-resets
41 offset and bitmask of RMII reset field. May have multiple tuples if more
42 than one ethernet port is available.
43
44- ti,dscr-locked-regs
45 possibly multiple tuples describing registers which are write protected by
46 a lock register. Each tuple consists of the register offset, lock register
47 offsset, and the key value used to unlock the register.
48
49- ti,dscr-kick-regs
50 offset and key values of two "kick" registers used to write protect other
51 registers in DSCR. On SoCs using kick registers, the first key must be
52 written to the first kick register and the second key must be written to
53 the second register before other registers in the area are write-enabled.
54
55- ti,dscr-mac-fuse-regs
56 MAC addresses are contained in two registers. Each element of a MAC address
57 is contained in a single byte. This property has two tuples. Each tuple has
58 a register offset and four cells representing bytes in the register from
59 most significant to least. The value of these four cells is the MAC byte
60 index (1-6) of the byte within the register. A value of 0 means the byte
61 is unused in the MAC address.
62
63- ti,dscr-devstate-ctl-regs
64 This property describes the bitfields used to control the state of devices.
65 Each tuple describes a range of identical bitfields used to control one or
66 more devices (one bitfield per device). The layout of each tuple is:
67
68 start_id num_ids reg enable disable start_bit nbits
69
70 Where:
71 start_id is device id for the first device control in the range
72 num_ids is the number of device controls in the range
73 reg is the offset of the register holding the control bits
74 enable is the value to enable a device
75 disable is the value to disable a device (0xffffffff if cannot disable)
76 start_bit is the bit number of the first bit in the range
77 nbits is the number of bits per device control
78
79- ti,dscr-devstate-stat-regs
80 This property describes the bitfields used to provide device state status
81 for device states controlled by the DSCR. Each tuple describes a range of
82 identical bitfields used to provide status for one or more devices (one
83 bitfield per device). The layout of each tuple is:
84
85 start_id num_ids reg enable disable start_bit nbits
86
87 Where:
88 start_id is device id for the first device status in the range
89 num_ids is the number of devices covered by the range
90 reg is the offset of the register holding the status bits
91 enable is the value indicating device is enabled
92 disable is the value indicating device is disabled
93 start_bit is the bit number of the first bit in the range
94 nbits is the number of bits per device status
95
96- ti,dscr-privperm
97 Offset and default value for register used to set access privilege for
98 some SoC devices.
99
100
101Example:
102
103 device-state-config-regs@2a80000 {
104 compatible = "ti,c64x+dscr";
105 reg = <0x02a80000 0x41000>;
106
107 ti,dscr-devstat = <0>;
108 ti,dscr-silicon-rev = <8 28 0xf>;
109 ti,dscr-rmii-resets = <0x40020 0x00040000>;
110
111 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
112 ti,dscr-devstate-ctl-regs =
113 <0 12 0x40008 1 0 0 2
114 12 1 0x40008 3 0 30 2
115 13 2 0x4002c 1 0xffffffff 0 1>;
116 ti,dscr-devstate-stat-regs =
117 <0 10 0x40014 1 0 0 3
118 10 2 0x40018 1 0 0 3>;
119
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
121 0x704 5 6 0 0>;
122
123 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
124
125 ti,dscr-kick-regs = <0x38 0x83E70B13
126 0x3c 0x95A4F1E0>;
127 };
diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt
new file mode 100644
index 000000000000..0ff6e9b9a13f
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/emifa.txt
@@ -0,0 +1,62 @@
1External Memory Interface
2-------------------------
3
4The emifa node describes a simple external bus controller found on some C6X
5SoCs. This interface provides external busses with a number of chip selects.
6
7Required properties:
8
9- compatible: must be "ti,c64x+emifa", "simple-bus"
10- reg: register area base and size
11- #address-cells: must be 2 (chip-select + offset)
12- #size-cells: must be 1
13- ranges: mapping from EMIFA space to parent space
14
15
16Optional properties:
17
18- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
19
20- ti,emifa-burst-priority:
21 Number of memory transfers after which the EMIF will elevate the priority
22 of the oldest command in the command FIFO. Setting this field to 255
23 disables this feature, thereby allowing old commands to stay in the FIFO
24 indefinitely.
25
26- ti,emifa-ce-config:
27 Configuration values for each of the supported chip selects.
28
29Example:
30
31 emifa@70000000 {
32 compatible = "ti,c64x+emifa", "simple-bus";
33 #address-cells = <2>;
34 #size-cells = <1>;
35 reg = <0x70000000 0x100>;
36 ranges = <0x2 0x0 0xa0000000 0x00000008
37 0x3 0x0 0xb0000000 0x00400000
38 0x4 0x0 0xc0000000 0x10000000
39 0x5 0x0 0xD0000000 0x10000000>;
40
41 ti,dscr-dev-enable = <13>;
42 ti,emifa-burst-priority = <255>;
43 ti,emifa-ce-config = <0x00240120
44 0x00240120
45 0x00240122
46 0x00240122>;
47
48 flash@3,0 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "cfi-flash";
52 reg = <0x3 0x0 0x400000>;
53 bank-width = <1>;
54 device-width = <1>;
55 partition@0 {
56 reg = <0x0 0x400000>;
57 label = "NOR";
58 };
59 };
60 };
61
62This shows a flash chip attached to chip select 3.
diff --git a/Documentation/devicetree/bindings/c6x/interrupt.txt b/Documentation/devicetree/bindings/c6x/interrupt.txt
new file mode 100644
index 000000000000..42bb796cc4ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/interrupt.txt
@@ -0,0 +1,104 @@
1C6X Interrupt Chips
2-------------------
3
4* C64X+ Core Interrupt Controller
5
6 The core interrupt controller provides 16 prioritized interrupts to the
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
9 sources coming from outside the core.
10
11 Required properties:
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
15
16 Interrupt Specifier Definition
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
19 4 is highest priority and 15 is lowest priority.
20
21 Example
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 compatible = "ti,c64x+core-pic";
27 };
28
29
30
31* C64x+ Megamodule Interrupt Controller
32
33 The megamodule PIC consists of four interrupt mupliplexers each of which
34 combine up to 32 interrupt inputs into a single interrupt output which
35 may be cascaded into the core interrupt controller. The megamodule PIC
36 has a total of 12 outputs cascading into the core interrupt controller.
37 One for each core interrupt priority level. In addition to the combined
38 interrupt sources, individual megamodule interrupts may be cascaded to
39 the core interrupt controller. When an individual interrupt is cascaded,
40 it is no longer handled through a megamodule interrupt combiner and is
41 considered to have the core interrupt controller as the parent.
42
43 Required properties:
44 --------------------
45 - compatible: "ti,c64x+megamod-pic"
46 - interrupt-controller
47 - #interrupt-cells: <1>
48 - reg: base address and size of register area
49 - interrupt-parent: must be core interrupt controller
50 - interrupts: This should have four cells; one for each interrupt combiner.
51 The cells contain the core priority interrupt to which the
52 corresponding combiner output is wired.
53
54 Optional properties:
55 --------------------
56 - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
57 priority interrupts. The first cell corresponds to
58 core priority 4 and the last cell corresponds to
59 core priority 15. The value of each cell is the
60 megamodule interrupt source which is MUXed to
61 the core interrupt corresponding to the cell
62 position. Allowed values are 4 - 127. Mapping for
63 interrupts 0 - 3 (combined interrupt sources) are
64 ignored.
65
66 Interrupt Specifier Definition
67 ------------------------------
68 Single cell specifying the megamodule interrupt source (4-127). Note that
69 interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
70 use the core interrupt controller as their parent and the specifier will
71 be the core priority level, not the megamodule interrupt number.
72
73 Examples
74 --------
75 megamod_pic: interrupt-controller@1800000 {
76 compatible = "ti,c64x+megamod-pic";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x1800000 0x1000>;
80 interrupt-parent = <&core_pic>;
81 interrupts = < 12 13 14 15 >;
82 };
83
84 This is a minimal example where all individual interrupts go through a
85 combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
86 to interrupt 13, etc.
87
88
89 megamod_pic: interrupt-controller@1800000 {
90 compatible = "ti,c64x+megamod-pic";
91 interrupt-controller;
92 #interrupt-cells = <1>;
93 reg = <0x1800000 0x1000>;
94 interrupt-parent = <&core_pic>;
95 interrupts = < 12 13 14 15 >;
96 ti,c64x+megamod-pic-mux = < 0 0 0 0
97 32 0 0 0
98 0 0 0 0 >;
99 };
100
101 This the same as the first example except that megamodule interrupt 32 is
102 mapped directly to core priority interrupt 8. The node using this interrupt
103 must set the core controller as its interrupt parent and use 8 in the
104 interrupt specifier value.
diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt
new file mode 100644
index 000000000000..b1e4973b5769
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/soc.txt
@@ -0,0 +1,28 @@
1C6X System-on-Chip
2------------------
3
4Required properties:
5
6- compatible: "simple-bus"
7- #address-cells: must be 1
8- #size-cells: must be 1
9- ranges
10
11Optional properties:
12
13- model: specific SoC model
14
15- nodes for IP blocks within SoC
16
17
18Example:
19
20 soc {
21 compatible = "simple-bus";
22 model = "tms320c6455";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 ...
28 };
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
new file mode 100644
index 000000000000..95911fe70224
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/timer64.txt
@@ -0,0 +1,26 @@
1Timer64
2-------
3
4The timer64 node describes C6X event timers.
5
6Required properties:
7
8- compatible: must be "ti,c64x+timer64"
9- reg: base address and size of register region
10- interrupt-parent: interrupt controller
11- interrupts: interrupt id
12
13Optional properties:
14
15- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
16
17- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
18
19Example:
20 timer0: timer@25e0000 {
21 compatible = "ti,c64x+timer64";
22 ti,core-mask = < 0x01 >;
23 reg = <0x25e0000 0x40>;
24 interrupt-parent = <&megamod_pic>;
25 interrupts = < 16 >;
26 };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0460f6550e4b..311b0c405572 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1645,6 +1645,14 @@ T: git git://git.alsa-project.org/alsa-kernel.git
1645S: Maintained 1645S: Maintained
1646F: sound/pci/oxygen/ 1646F: sound/pci/oxygen/
1647 1647
1648C6X ARCHITECTURE
1649M: Mark Salter <msalter@redhat.com>
1650M: Aurelien Jacquiot <a-jacquiot@ti.com>
1651L: linux-c6x-dev@linux-c6x.org
1652W: http://www.linux-c6x.org/wiki/index.php/Main_Page
1653S: Maintained
1654F: arch/c6x/
1655
1648CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS 1656CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
1649M: David Howells <dhowells@redhat.com> 1657M: David Howells <dhowells@redhat.com>
1650L: linux-cachefs@redhat.com 1658L: linux-cachefs@redhat.com
diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig
new file mode 100644
index 000000000000..26e67f0f0051
--- /dev/null
+++ b/arch/c6x/Kconfig
@@ -0,0 +1,174 @@
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6config TMS320C6X
7 def_bool y
8 select CLKDEV_LOOKUP
9 select GENERIC_IRQ_SHOW
10 select HAVE_ARCH_TRACEHOOK
11 select HAVE_DMA_API_DEBUG
12 select HAVE_GENERIC_HARDIRQS
13 select HAVE_MEMBLOCK
14 select HAVE_SPARSE_IRQ
15 select OF
16 select OF_EARLY_FLATTREE
17
18config MMU
19 def_bool n
20
21config ZONE_DMA
22 def_bool y
23
24config FPU
25 def_bool n
26
27config HIGHMEM
28 def_bool n
29
30config NUMA
31 def_bool n
32
33config RWSEM_GENERIC_SPINLOCK
34 def_bool y
35
36config RWSEM_XCHGADD_ALGORITHM
37 def_bool n
38
39config GENERIC_CALIBRATE_DELAY
40 def_bool y
41
42config GENERIC_HWEIGHT
43 def_bool y
44
45config GENERIC_CLOCKEVENTS
46 def_bool y
47
48config GENERIC_CLOCKEVENTS_BROADCAST
49 bool
50
51config GENERIC_BUG
52 def_bool y
53
54config COMMON_CLKDEV
55 def_bool y
56
57config C6X_BIG_KERNEL
58 bool "Build a big kernel"
59 help
60 The C6X function call instruction has a limited range of +/- 2MiB.
61 This is sufficient for most kernels, but some kernel configurations
62 with lots of compiled-in functionality may require a larger range
63 for function calls. Use this option to have the compiler generate
64 function calls with 32-bit range. This will make the kernel both
65 larger and slower.
66
67 If unsure, say N.
68
69source "init/Kconfig"
70
71# Use the generic interrupt handling code in kernel/irq/
72
73source "kernel/Kconfig.freezer"
74
75config CMDLINE_BOOL
76 bool "Default bootloader kernel arguments"
77
78config CMDLINE
79 string "Kernel command line"
80 depends on CMDLINE_BOOL
81 default "console=ttyS0,57600"
82 help
83 On some architectures there is currently no way for the boot loader
84 to pass arguments to the kernel. For these architectures, you should
85 supply some command-line options at build time by entering them
86 here.
87
88config CMDLINE_FORCE
89 bool "Force default kernel command string"
90 depends on CMDLINE_BOOL
91 default n
92 help
93 Set this to have arguments from the default kernel command string
94 override those passed by the boot loader.
95
96config CPU_BIG_ENDIAN
97 bool "Build big-endian kernel"
98 default n
99 help
100 Say Y if you plan on running a kernel in big-endian mode.
101 Note that your board must be properly built and your board
102 port must properly enable any big-endian related features
103 of your chipset/board/processor.
104
105config FORCE_MAX_ZONEORDER
106 int "Maximum zone order"
107 default "13"
108 help
109 The kernel memory allocator divides physically contiguous memory
110 blocks into "zones", where each zone is a power of two number of
111 pages. This option selects the largest power of two that the kernel
112 keeps in the memory allocator. If you need to allocate very large
113 blocks of physically contiguous memory, then you may need to
114 increase this value.
115
116 This config option is actually maximum order plus one. For example,
117 a value of 11 means that the largest free memory block is 2^10 pages.
118
119menu "Processor type and features"
120
121source "arch/c6x/platforms/Kconfig"
122
123config TMS320C6X_CACHES_ON
124 bool "L2 cache support"
125 default y
126
127config KERNEL_RAM_BASE_ADDRESS
128 hex "Virtual address of memory base"
129 default 0xe0000000 if SOC_TMS320C6455
130 default 0xe0000000 if SOC_TMS320C6457
131 default 0xe0000000 if SOC_TMS320C6472
132 default 0x80000000
133
134source "mm/Kconfig"
135
136source "kernel/Kconfig.preempt"
137
138source "kernel/Kconfig.hz"
139source "kernel/time/Kconfig"
140
141endmenu
142
143menu "Executable file formats"
144
145source "fs/Kconfig.binfmt"
146
147endmenu
148
149source "net/Kconfig"
150
151source "drivers/Kconfig"
152
153source "fs/Kconfig"
154
155source "security/Kconfig"
156
157source "crypto/Kconfig"
158
159source "lib/Kconfig"
160
161menu "Kernel hacking"
162
163source "lib/Kconfig.debug"
164
165config ACCESS_CHECK
166 bool "Check the user pointer address"
167 default y
168 help
169 Usually the pointer transfer from user space is checked to see if its
170 address is in the kernel space.
171
172 Say N here to disable that check to improve the performance.
173
174endmenu
diff --git a/arch/c6x/Makefile b/arch/c6x/Makefile
new file mode 100644
index 000000000000..1d08dd070277
--- /dev/null
+++ b/arch/c6x/Makefile
@@ -0,0 +1,60 @@
1#
2# linux/arch/c6x/Makefile
3#
4# This file is subject to the terms and conditions of the GNU General Public
5# License. See the file "COPYING" in the main directory of this archive
6# for more details.
7#
8
9cflags-y += -mno-dsbt -msdata=none
10
11cflags-$(CONFIG_C6X_BIG_KERNEL) += -mlong-calls
12
13CFLAGS_MODULE += -mlong-calls -mno-dsbt -msdata=none
14
15CHECKFLAGS +=
16
17KBUILD_CFLAGS += $(cflags-y)
18KBUILD_AFLAGS += $(cflags-y)
19
20ifdef CONFIG_CPU_BIG_ENDIAN
21KBUILD_CFLAGS += -mbig-endian
22KBUILD_AFLAGS += -mbig-endian
23LINKFLAGS += -mbig-endian
24KBUILD_LDFLAGS += -mbig-endian
25LDFLAGS += -EB
26endif
27
28head-y := arch/c6x/kernel/head.o
29core-y += arch/c6x/kernel/ arch/c6x/mm/ arch/c6x/platforms/
30libs-y += arch/c6x/lib/
31
32# Default to vmlinux.bin, override when needed
33all: vmlinux.bin
34
35boot := arch/$(ARCH)/boot
36
37# Are we making a dtbImage.<boardname> target? If so, crack out the boardname
38DTB:=$(subst dtbImage.,,$(filter dtbImage.%, $(MAKECMDGOALS)))
39export DTB
40
41ifneq ($(DTB),)
42core-y += $(boot)/
43endif
44
45# With make 3.82 we cannot mix normal and wildcard targets
46
47vmlinux.bin: vmlinux
48 $(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
49
50dtbImage.%: vmlinux
51 $(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
52
53archclean:
54 $(Q)$(MAKE) $(clean)=$(boot)
55
56define archhelp
57 @echo ' vmlinux.bin - Binary kernel image (arch/$(ARCH)/boot/vmlinux.bin)'
58 @echo ' dtbImage.<dt> - ELF image with $(arch)/boot/dts/<dt>.dts linked in'
59 @echo ' - stripped elf with fdt blob'
60endef
diff --git a/arch/c6x/boot/Makefile b/arch/c6x/boot/Makefile
new file mode 100644
index 000000000000..ecca820e6041
--- /dev/null
+++ b/arch/c6x/boot/Makefile
@@ -0,0 +1,30 @@
1#
2# Makefile for bootable kernel images
3#
4
5OBJCOPYFLAGS_vmlinux.bin := -O binary
6$(obj)/vmlinux.bin: vmlinux FORCE
7 $(call if_changed,objcopy)
8
9DTC_FLAGS ?= -p 1024
10
11ifneq ($(DTB),)
12obj-y += linked_dtb.o
13endif
14
15$(obj)/%.dtb: $(src)/dts/%.dts FORCE
16 $(call cmd,dtc)
17
18quiet_cmd_cp = CP $< $@$2
19 cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
20
21# Generate builtin.dtb from $(DTB).dtb
22$(obj)/builtin.dtb: $(obj)/$(DTB).dtb
23 $(call if_changed,cp)
24
25$(obj)/linked_dtb.o: $(obj)/builtin.dtb
26
27$(obj)/dtbImage.%: vmlinux
28 $(call if_changed,objcopy)
29
30clean-files := $(obj)/*.dtb
diff --git a/arch/c6x/boot/dts/dsk6455.dts b/arch/c6x/boot/dts/dsk6455.dts
new file mode 100644
index 000000000000..2b71f800618d
--- /dev/null
+++ b/arch/c6x/boot/dts/dsk6455.dts
@@ -0,0 +1,62 @@
1/*
2 * arch/c6x/boot/dts/dsk6455.dts
3 *
4 * DSK6455 Evaluation Platform For TMS320C6455
5 * Copyright (C) 2011 Texas Instruments Incorporated
6 *
7 * Author: Mark Salter <msalter@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 */
15
16/dts-v1/;
17
18/include/ "tms320c6455.dtsi"
19
20/ {
21 model = "Spectrum Digital DSK6455";
22 compatible = "spectrum-digital,dsk6455";
23
24 chosen {
25 bootargs = "root=/dev/nfs ip=dhcp rw";
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0xE0000000 0x08000000>;
31 };
32
33 soc {
34 megamod_pic: interrupt-controller@1800000 {
35 interrupts = < 12 13 14 15 >;
36 };
37
38 emifa@70000000 {
39 flash@3,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x3 0x0 0x400000>;
44 bank-width = <1>;
45 device-width = <1>;
46 partition@0 {
47 reg = <0x0 0x400000>;
48 label = "NOR";
49 };
50 };
51 };
52
53 timer1: timer@2980000 {
54 interrupt-parent = <&megamod_pic>;
55 interrupts = < 69 >;
56 };
57
58 clock-controller@029a0000 {
59 clock-frequency = <50000000>;
60 };
61 };
62};
diff --git a/arch/c6x/boot/dts/evmc6457.dts b/arch/c6x/boot/dts/evmc6457.dts
new file mode 100644
index 000000000000..0301eb9a8ff8
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6457.dts
@@ -0,0 +1,48 @@
1/*
2 * arch/c6x/boot/dts/evmc6457.dts
3 *
4 * EVMC6457 Evaluation Platform For TMS320C6457
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6457.dtsi"
20
21/ {
22 model = "eInfochips EVMC6457";
23 compatible = "einfochips,evmc6457";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0xE0000000 0x10000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer0: timer@2940000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 67 >;
42 };
43
44 clock-controller@29a0000 {
45 clock-frequency = <60000000>;
46 };
47 };
48};
diff --git a/arch/c6x/boot/dts/evmc6472.dts b/arch/c6x/boot/dts/evmc6472.dts
new file mode 100644
index 000000000000..3e207b449a93
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6472.dts
@@ -0,0 +1,73 @@
1/*
2 * arch/c6x/boot/dts/evmc6472.dts
3 *
4 * EVMC6472 Evaluation Platform For TMS320C6472
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6472.dtsi"
20
21/ {
22 model = "eInfochips EVMC6472";
23 compatible = "einfochips,evmc6472";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0xE0000000 0x10000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer0: timer@25e0000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 16 >;
42 };
43
44 timer1: timer@25f0000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 16 >;
47 };
48
49 timer2: timer@2600000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 16 >;
52 };
53
54 timer3: timer@2610000 {
55 interrupt-parent = <&megamod_pic>;
56 interrupts = < 16 >;
57 };
58
59 timer4: timer@2620000 {
60 interrupt-parent = <&megamod_pic>;
61 interrupts = < 16 >;
62 };
63
64 timer5: timer@2630000 {
65 interrupt-parent = <&megamod_pic>;
66 interrupts = < 16 >;
67 };
68
69 clock-controller@29a0000 {
70 clock-frequency = <25000000>;
71 };
72 };
73};
diff --git a/arch/c6x/boot/dts/evmc6474.dts b/arch/c6x/boot/dts/evmc6474.dts
new file mode 100644
index 000000000000..4dc291292bc4
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6474.dts
@@ -0,0 +1,58 @@
1/*
2 * arch/c6x/boot/dts/evmc6474.dts
3 *
4 * EVMC6474 Evaluation Platform For TMS320C6474
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6474.dtsi"
20
21/ {
22 model = "Spectrum Digital EVMC6474";
23 compatible = "spectrum-digital,evmc6474";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x80000000 0x08000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer3: timer@2940000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 39 >;
42 };
43
44 timer4: timer@2950000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 41 >;
47 };
48
49 timer5: timer@2960000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 43 >;
52 };
53
54 clock-controller@29a0000 {
55 clock-frequency = <50000000>;
56 };
57 };
58};
diff --git a/arch/c6x/boot/dts/tms320c6455.dtsi b/arch/c6x/boot/dts/tms320c6455.dtsi
new file mode 100644
index 000000000000..a804ec1e018b
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6455.dtsi
@@ -0,0 +1,96 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 model = "ti,c64x+";
13 reg = <0>;
14 };
15 };
16
17 soc {
18 compatible = "simple-bus";
19 model = "tms320c6455";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 compatible = "ti,c64x+core-pic";
28 };
29
30 /*
31 * Megamodule interrupt controller
32 */
33 megamod_pic: interrupt-controller@1800000 {
34 compatible = "ti,c64x+megamod-pic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x1800000 0x1000>;
38 interrupt-parent = <&core_pic>;
39 };
40
41 cache-controller@1840000 {
42 compatible = "ti,c64x+cache";
43 reg = <0x01840000 0x8400>;
44 };
45
46 emifa@70000000 {
47 compatible = "ti,c64x+emifa", "simple-bus";
48 #address-cells = <2>;
49 #size-cells = <1>;
50 reg = <0x70000000 0x100>;
51 ranges = <0x2 0x0 0xa0000000 0x00000008
52 0x3 0x0 0xb0000000 0x00400000
53 0x4 0x0 0xc0000000 0x10000000
54 0x5 0x0 0xD0000000 0x10000000>;
55
56 ti,dscr-dev-enable = <13>;
57 ti,emifa-burst-priority = <255>;
58 ti,emifa-ce-config = <0x00240120
59 0x00240120
60 0x00240122
61 0x00240122>;
62 };
63
64 timer1: timer@2980000 {
65 compatible = "ti,c64x+timer64";
66 reg = <0x2980000 0x40>;
67 ti,dscr-dev-enable = <4>;
68 };
69
70 clock-controller@029a0000 {
71 compatible = "ti,c6455-pll", "ti,c64x+pll";
72 reg = <0x029a0000 0x200>;
73 ti,c64x+pll-bypass-delay = <1440>;
74 ti,c64x+pll-reset-delay = <15360>;
75 ti,c64x+pll-lock-delay = <24000>;
76 };
77
78 device-state-config-regs@2a80000 {
79 compatible = "ti,c64x+dscr";
80 reg = <0x02a80000 0x41000>;
81
82 ti,dscr-devstat = <0>;
83 ti,dscr-silicon-rev = <8 28 0xf>;
84 ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
85
86 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
87 ti,dscr-devstate-ctl-regs =
88 <0 12 0x40008 1 0 0 2
89 12 1 0x40008 3 0 30 2
90 13 2 0x4002c 1 0xffffffff 0 1>;
91 ti,dscr-devstate-stat-regs =
92 <0 10 0x40014 1 0 0 3
93 10 2 0x40018 1 0 0 3>;
94 };
95 };
96};
diff --git a/arch/c6x/boot/dts/tms320c6457.dtsi b/arch/c6x/boot/dts/tms320c6457.dtsi
new file mode 100644
index 000000000000..35f40709a719
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6457.dtsi
@@ -0,0 +1,68 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 model = "ti,c64x+";
13 reg = <0>;
14 };
15 };
16
17 soc {
18 compatible = "simple-bus";
19 model = "tms320c6457";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 compatible = "ti,c64x+core-pic";
28 };
29
30 megamod_pic: interrupt-controller@1800000 {
31 compatible = "ti,c64x+megamod-pic";
32 interrupt-controller;
33 #interrupt-cells = <1>;
34 interrupt-parent = <&core_pic>;
35 reg = <0x1800000 0x1000>;
36 };
37
38 cache-controller@1840000 {
39 compatible = "ti,c64x+cache";
40 reg = <0x01840000 0x8400>;
41 };
42
43 device-state-controller@2880800 {
44 compatible = "ti,c64x+dscr";
45 reg = <0x02880800 0x400>;
46
47 ti,dscr-devstat = <0x20>;
48 ti,dscr-silicon-rev = <0x18 28 0xf>;
49 ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
50 0x118 0 0 1 2>;
51 ti,dscr-kick-regs = <0x38 0x83E70B13
52 0x3c 0x95A4F1E0>;
53 };
54
55 timer0: timer@2940000 {
56 compatible = "ti,c64x+timer64";
57 reg = <0x2940000 0x40>;
58 };
59
60 clock-controller@29a0000 {
61 compatible = "ti,c6457-pll", "ti,c64x+pll";
62 reg = <0x029a0000 0x200>;
63 ti,c64x+pll-bypass-delay = <300>;
64 ti,c64x+pll-reset-delay = <24000>;
65 ti,c64x+pll-lock-delay = <50000>;
66 };
67 };
68};
diff --git a/arch/c6x/boot/dts/tms320c6472.dtsi b/arch/c6x/boot/dts/tms320c6472.dtsi
new file mode 100644
index 000000000000..b488aaec65c0
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6472.dtsi
@@ -0,0 +1,134 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 cpu@3 {
26 device_type = "cpu";
27 reg = <3>;
28 model = "ti,c64x+";
29 };
30 cpu@4 {
31 device_type = "cpu";
32 reg = <4>;
33 model = "ti,c64x+";
34 };
35 cpu@5 {
36 device_type = "cpu";
37 reg = <5>;
38 model = "ti,c64x+";
39 };
40 };
41
42 soc {
43 compatible = "simple-bus";
44 model = "tms320c6472";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 core_pic: interrupt-controller {
50 compatible = "ti,c64x+core-pic";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 };
54
55 megamod_pic: interrupt-controller@1800000 {
56 compatible = "ti,c64x+megamod-pic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x1800000 0x1000>;
60 interrupt-parent = <&core_pic>;
61 };
62
63 cache-controller@1840000 {
64 compatible = "ti,c64x+cache";
65 reg = <0x01840000 0x8400>;
66 };
67
68 timer0: timer@25e0000 {
69 compatible = "ti,c64x+timer64";
70 ti,core-mask = < 0x01 >;
71 reg = <0x25e0000 0x40>;
72 };
73
74 timer1: timer@25f0000 {
75 compatible = "ti,c64x+timer64";
76 ti,core-mask = < 0x02 >;
77 reg = <0x25f0000 0x40>;
78 };
79
80 timer2: timer@2600000 {
81 compatible = "ti,c64x+timer64";
82 ti,core-mask = < 0x04 >;
83 reg = <0x2600000 0x40>;
84 };
85
86 timer3: timer@2610000 {
87 compatible = "ti,c64x+timer64";
88 ti,core-mask = < 0x08 >;
89 reg = <0x2610000 0x40>;
90 };
91
92 timer4: timer@2620000 {
93 compatible = "ti,c64x+timer64";
94 ti,core-mask = < 0x10 >;
95 reg = <0x2620000 0x40>;
96 };
97
98 timer5: timer@2630000 {
99 compatible = "ti,c64x+timer64";
100 ti,core-mask = < 0x20 >;
101 reg = <0x2630000 0x40>;
102 };
103
104 clock-controller@29a0000 {
105 compatible = "ti,c6472-pll", "ti,c64x+pll";
106 reg = <0x029a0000 0x200>;
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
110 };
111
112 device-state-controller@2a80000 {
113 compatible = "ti,c64x+dscr";
114 reg = <0x02a80000 0x1000>;
115
116 ti,dscr-devstat = <0>;
117 ti,dscr-silicon-rev = <0x70c 16 0xff>;
118
119 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
120 0x704 5 6 0 0>;
121
122 ti,dscr-rmii-resets = <0x208 1
123 0x20c 1>;
124
125 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
126 0x40c 0x420 0xbea7
127 0x41c 0x420 0xbea7>;
128
129 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
130
131 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
132 };
133 };
134};
diff --git a/arch/c6x/boot/dts/tms320c6474.dtsi b/arch/c6x/boot/dts/tms320c6474.dtsi
new file mode 100644
index 000000000000..cc601bf348a1
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6474.dtsi
@@ -0,0 +1,89 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 };
26
27 soc {
28 compatible = "simple-bus";
29 model = "tms320c6474";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 ranges;
33
34 core_pic: interrupt-controller {
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 compatible = "ti,c64x+core-pic";
38 };
39
40 megamod_pic: interrupt-controller@1800000 {
41 compatible = "ti,c64x+megamod-pic";
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 reg = <0x1800000 0x1000>;
45 interrupt-parent = <&core_pic>;
46 };
47
48 cache-controller@1840000 {
49 compatible = "ti,c64x+cache";
50 reg = <0x01840000 0x8400>;
51 };
52
53 timer3: timer@2940000 {
54 compatible = "ti,c64x+timer64";
55 ti,core-mask = < 0x04 >;
56 reg = <0x2940000 0x40>;
57 };
58
59 timer4: timer@2950000 {
60 compatible = "ti,c64x+timer64";
61 ti,core-mask = < 0x02 >;
62 reg = <0x2950000 0x40>;
63 };
64
65 timer5: timer@2960000 {
66 compatible = "ti,c64x+timer64";
67 ti,core-mask = < 0x01 >;
68 reg = <0x2960000 0x40>;
69 };
70
71 device-state-controller@2880800 {
72 compatible = "ti,c64x+dscr";
73 reg = <0x02880800 0x400>;
74
75 ti,dscr-devstat = <0x004>;
76 ti,dscr-silicon-rev = <0x014 28 0xf>;
77 ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
78 0x38 0 0 1 2>;
79 };
80
81 clock-controller@29a0000 {
82 compatible = "ti,c6474-pll", "ti,c64x+pll";
83 reg = <0x029a0000 0x200>;
84 ti,c64x+pll-bypass-delay = <120>;
85 ti,c64x+pll-reset-delay = <30000>;
86 ti,c64x+pll-lock-delay = <60000>;
87 };
88 };
89};
diff --git a/arch/c6x/boot/linked_dtb.S b/arch/c6x/boot/linked_dtb.S
new file mode 100644
index 000000000000..57a4454eaec3
--- /dev/null
+++ b/arch/c6x/boot/linked_dtb.S
@@ -0,0 +1,2 @@
1.section __fdt_blob,"a"
2.incbin "arch/c6x/boot/builtin.dtb"
diff --git a/arch/c6x/configs/dsk6455_defconfig b/arch/c6x/configs/dsk6455_defconfig
new file mode 100644
index 000000000000..4663487c67a1
--- /dev/null
+++ b/arch/c6x/configs/dsk6455_defconfig
@@ -0,0 +1,44 @@
1CONFIG_SOC_TMS320C6455=y
2CONFIG_EXPERIMENTAL=y
3# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_NAMESPACES=y
8# CONFIG_UTS_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_EXPERT=y
14# CONFIG_FUTEX is not set
15# CONFIG_SLUB_DEBUG is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_CMDLINE_BOOL=y
21CONFIG_CMDLINE=""
22CONFIG_NO_HZ=y
23CONFIG_HIGH_RES_TIMERS=y
24CONFIG_BLK_DEV_LOOP=y
25CONFIG_BLK_DEV_RAM=y
26CONFIG_BLK_DEV_RAM_COUNT=2
27CONFIG_BLK_DEV_RAM_SIZE=17000
28CONFIG_MISC_DEVICES=y
29# CONFIG_INPUT is not set
30# CONFIG_SERIO is not set
31# CONFIG_VT is not set
32# CONFIG_HW_RANDOM is not set
33# CONFIG_HWMON is not set
34# CONFIG_USB_SUPPORT is not set
35# CONFIG_IOMMU_SUPPORT is not set
36# CONFIG_MISC_FILESYSTEMS is not set
37CONFIG_CRC16=y
38# CONFIG_ENABLE_MUST_CHECK is not set
39# CONFIG_SCHED_DEBUG is not set
40# CONFIG_DEBUG_BUGVERBOSE is not set
41CONFIG_MTD=y
42CONFIG_MTD_CFI=y
43CONFIG_MTD_CFI_AMDSTD=y
44CONFIG_MTD_PHYSMAP_OF=y
diff --git a/arch/c6x/configs/evmc6457_defconfig b/arch/c6x/configs/evmc6457_defconfig
new file mode 100644
index 000000000000..bba40e195ec4
--- /dev/null
+++ b/arch/c6x/configs/evmc6457_defconfig
@@ -0,0 +1,41 @@
1CONFIG_SOC_TMS320C6457=y
2CONFIG_EXPERIMENTAL=y
3# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_NAMESPACES=y
8# CONFIG_UTS_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_EXPERT=y
14# CONFIG_FUTEX is not set
15# CONFIG_SLUB_DEBUG is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_CMDLINE_BOOL=y
21CONFIG_CMDLINE=""
22CONFIG_BOARD_EVM6457=y
23CONFIG_NO_HZ=y
24CONFIG_HIGH_RES_TIMERS=y
25CONFIG_BLK_DEV_LOOP=y
26CONFIG_BLK_DEV_RAM=y
27CONFIG_BLK_DEV_RAM_COUNT=2
28CONFIG_BLK_DEV_RAM_SIZE=17000
29CONFIG_MISC_DEVICES=y
30# CONFIG_INPUT is not set
31# CONFIG_SERIO is not set
32# CONFIG_VT is not set
33# CONFIG_HW_RANDOM is not set
34# CONFIG_HWMON is not set
35# CONFIG_USB_SUPPORT is not set
36# CONFIG_IOMMU_SUPPORT is not set
37# CONFIG_MISC_FILESYSTEMS is not set
38CONFIG_CRC16=y
39# CONFIG_ENABLE_MUST_CHECK is not set
40# CONFIG_SCHED_DEBUG is not set
41# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/configs/evmc6472_defconfig b/arch/c6x/configs/evmc6472_defconfig
new file mode 100644
index 000000000000..8c46155f6d31
--- /dev/null
+++ b/arch/c6x/configs/evmc6472_defconfig
@@ -0,0 +1,42 @@
1CONFIG_SOC_TMS320C6472=y
2CONFIG_EXPERIMENTAL=y
3# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_NAMESPACES=y
8# CONFIG_UTS_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_EXPERT=y
14# CONFIG_FUTEX is not set
15# CONFIG_SLUB_DEBUG is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_CMDLINE_BOOL=y
21CONFIG_CMDLINE=""
22# CONFIG_CMDLINE_FORCE is not set
23CONFIG_BOARD_EVM6472=y
24CONFIG_NO_HZ=y
25CONFIG_HIGH_RES_TIMERS=y
26CONFIG_BLK_DEV_LOOP=y
27CONFIG_BLK_DEV_RAM=y
28CONFIG_BLK_DEV_RAM_COUNT=2
29CONFIG_BLK_DEV_RAM_SIZE=17000
30CONFIG_MISC_DEVICES=y
31# CONFIG_INPUT is not set
32# CONFIG_SERIO is not set
33# CONFIG_VT is not set
34# CONFIG_HW_RANDOM is not set
35# CONFIG_HWMON is not set
36# CONFIG_USB_SUPPORT is not set
37# CONFIG_IOMMU_SUPPORT is not set
38# CONFIG_MISC_FILESYSTEMS is not set
39CONFIG_CRC16=y
40# CONFIG_ENABLE_MUST_CHECK is not set
41# CONFIG_SCHED_DEBUG is not set
42# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/configs/evmc6474_defconfig b/arch/c6x/configs/evmc6474_defconfig
new file mode 100644
index 000000000000..15533f632313
--- /dev/null
+++ b/arch/c6x/configs/evmc6474_defconfig
@@ -0,0 +1,42 @@
1CONFIG_SOC_TMS320C6474=y
2CONFIG_EXPERIMENTAL=y
3# CONFIG_LOCALVERSION_AUTO is not set
4CONFIG_SYSVIPC=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_NAMESPACES=y
8# CONFIG_UTS_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_EXPERT=y
14# CONFIG_FUTEX is not set
15# CONFIG_SLUB_DEBUG is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_CMDLINE_BOOL=y
21CONFIG_CMDLINE=""
22# CONFIG_CMDLINE_FORCE is not set
23CONFIG_BOARD_EVM6474=y
24CONFIG_NO_HZ=y
25CONFIG_HIGH_RES_TIMERS=y
26CONFIG_BLK_DEV_LOOP=y
27CONFIG_BLK_DEV_RAM=y
28CONFIG_BLK_DEV_RAM_COUNT=2
29CONFIG_BLK_DEV_RAM_SIZE=17000
30CONFIG_MISC_DEVICES=y
31# CONFIG_INPUT is not set
32# CONFIG_SERIO is not set
33# CONFIG_VT is not set
34# CONFIG_HW_RANDOM is not set
35# CONFIG_HWMON is not set
36# CONFIG_USB_SUPPORT is not set
37# CONFIG_IOMMU_SUPPORT is not set
38# CONFIG_MISC_FILESYSTEMS is not set
39CONFIG_CRC16=y
40# CONFIG_ENABLE_MUST_CHECK is not set
41# CONFIG_SCHED_DEBUG is not set
42# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild
new file mode 100644
index 000000000000..13dcf78adf91
--- /dev/null
+++ b/arch/c6x/include/asm/Kbuild
@@ -0,0 +1,54 @@
1include include/asm-generic/Kbuild.asm
2
3generic-y += atomic.h
4generic-y += auxvec.h
5generic-y += bitsperlong.h
6generic-y += bug.h
7generic-y += bugs.h
8generic-y += cputime.h
9generic-y += current.h
10generic-y += device.h
11generic-y += div64.h
12generic-y += dma.h
13generic-y += emergency-restart.h
14generic-y += errno.h
15generic-y += fb.h
16generic-y += fcntl.h
17generic-y += futex.h
18generic-y += hw_irq.h
19generic-y += io.h
20generic-y += ioctl.h
21generic-y += ioctls.h
22generic-y += ipcbuf.h
23generic-y += irq_regs.h
24generic-y += kdebug.h
25generic-y += kmap_types.h
26generic-y += local.h
27generic-y += mman.h
28generic-y += mmu_context.h
29generic-y += msgbuf.h
30generic-y += param.h
31generic-y += pci.h
32generic-y += percpu.h
33generic-y += pgalloc.h
34generic-y += poll.h
35generic-y += posix_types.h
36generic-y += resource.h
37generic-y += scatterlist.h
38generic-y += segment.h
39generic-y += sembuf.h
40generic-y += shmbuf.h
41generic-y += shmparam.h
42generic-y += siginfo.h
43generic-y += socket.h
44generic-y += sockios.h
45generic-y += stat.h
46generic-y += statfs.h
47generic-y += termbits.h
48generic-y += termios.h
49generic-y += tlbflush.h
50generic-y += topology.h
51generic-y += types.h
52generic-y += ucontext.h
53generic-y += user.h
54generic-y += vga.h
diff --git a/arch/c6x/include/asm/asm-offsets.h b/arch/c6x/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/c6x/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/c6x/include/asm/bitops.h b/arch/c6x/include/asm/bitops.h
new file mode 100644
index 000000000000..39ab7e874d96
--- /dev/null
+++ b/arch/c6x/include/asm/bitops.h
@@ -0,0 +1,105 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_BITOPS_H
12#define _ASM_C6X_BITOPS_H
13
14#ifdef __KERNEL__
15
16#include <linux/bitops.h>
17
18#include <asm/system.h>
19#include <asm/byteorder.h>
20
21/*
22 * clear_bit() doesn't provide any barrier for the compiler.
23 */
24#define smp_mb__before_clear_bit() barrier()
25#define smp_mb__after_clear_bit() barrier()
26
27/*
28 * We are lucky, DSP is perfect for bitops: do it in 3 cycles
29 */
30
31/**
32 * __ffs - find first bit in word.
33 * @word: The word to search
34 *
35 * Undefined if no bit exists, so code should check against 0 first.
36 * Note __ffs(0) = undef, __ffs(1) = 0, __ffs(0x80000000) = 31.
37 *
38 */
39static inline unsigned long __ffs(unsigned long x)
40{
41 asm (" bitr .M1 %0,%0\n"
42 " nop\n"
43 " lmbd .L1 1,%0,%0\n"
44 : "+a"(x));
45
46 return x;
47}
48
49/*
50 * ffz - find first zero in word.
51 * @word: The word to search
52 *
53 * Undefined if no zero exists, so code should check against ~0UL first.
54 */
55#define ffz(x) __ffs(~(x))
56
57/**
58 * fls - find last (most-significant) bit set
59 * @x: the word to search
60 *
61 * This is defined the same way as ffs.
62 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
63 */
64static inline int fls(int x)
65{
66 if (!x)
67 return 0;
68
69 asm (" lmbd .L1 1,%0,%0\n" : "+a"(x));
70
71 return 32 - x;
72}
73
74/**
75 * ffs - find first bit set
76 * @x: the word to search
77 *
78 * This is defined the same way as
79 * the libc and compiler builtin ffs routines, therefore
80 * differs in spirit from the above ffz (man ffs).
81 * Note ffs(0) = 0, ffs(1) = 1, ffs(0x80000000) = 32.
82 */
83static inline int ffs(int x)
84{
85 if (!x)
86 return 0;
87
88 return __ffs(x) + 1;
89}
90
91#include <asm-generic/bitops/__fls.h>
92#include <asm-generic/bitops/fls64.h>
93#include <asm-generic/bitops/find.h>
94
95#include <asm-generic/bitops/sched.h>
96#include <asm-generic/bitops/hweight.h>
97#include <asm-generic/bitops/lock.h>
98
99#include <asm-generic/bitops/atomic.h>
100#include <asm-generic/bitops/non-atomic.h>
101#include <asm-generic/bitops/le.h>
102#include <asm-generic/bitops/ext2-atomic.h>
103
104#endif /* __KERNEL__ */
105#endif /* _ASM_C6X_BITOPS_H */
diff --git a/arch/c6x/include/asm/byteorder.h b/arch/c6x/include/asm/byteorder.h
new file mode 100644
index 000000000000..166038db342b
--- /dev/null
+++ b/arch/c6x/include/asm/byteorder.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_C6X_BYTEORDER_H
2#define _ASM_C6X_BYTEORDER_H
3
4#include <asm/types.h>
5
6#ifdef _BIG_ENDIAN
7#include <linux/byteorder/big_endian.h>
8#else /* _BIG_ENDIAN */
9#include <linux/byteorder/little_endian.h>
10#endif /* _BIG_ENDIAN */
11
12#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
new file mode 100644
index 000000000000..6d521d96d941
--- /dev/null
+++ b/arch/c6x/include/asm/cache.h
@@ -0,0 +1,90 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_CACHE_H
12#define _ASM_C6X_CACHE_H
13
14#include <linux/irqflags.h>
15
16/*
17 * Cache line size
18 */
19#define L1D_CACHE_BYTES 64
20#define L1P_CACHE_BYTES 32
21#define L2_CACHE_BYTES 128
22
23/*
24 * L2 used as cache
25 */
26#define L2MODE_SIZE L2MODE_256K_CACHE
27
28/*
29 * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
30 * the L2 line size
31 */
32#define L1_CACHE_BYTES L2_CACHE_BYTES
33
34#define L2_CACHE_ALIGN_LOW(x) \
35 (((x) & ~(L2_CACHE_BYTES - 1)))
36#define L2_CACHE_ALIGN_UP(x) \
37 (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
38#define L2_CACHE_ALIGN_CNT(x) \
39 (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
40
41#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
42#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
43
44/*
45 * This is the granularity of hardware cacheability control.
46 */
47#define CACHEABILITY_ALIGN 0x01000000
48
49/*
50 * Align a physical address to MAR regions
51 */
52#define CACHE_REGION_START(v) \
53 (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
54#define CACHE_REGION_END(v) \
55 (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
56
57extern void __init c6x_cache_init(void);
58
59extern void enable_caching(unsigned long start, unsigned long end);
60extern void disable_caching(unsigned long start, unsigned long end);
61
62extern void L1_cache_off(void);
63extern void L1_cache_on(void);
64
65extern void L1P_cache_global_invalidate(void);
66extern void L1D_cache_global_invalidate(void);
67extern void L1D_cache_global_writeback(void);
68extern void L1D_cache_global_writeback_invalidate(void);
69extern void L2_cache_set_mode(unsigned int mode);
70extern void L2_cache_global_writeback_invalidate(void);
71extern void L2_cache_global_writeback(void);
72
73extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
74extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
75extern void L1D_cache_block_writeback_invalidate(unsigned int start,
76 unsigned int end);
77extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
78extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
79extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
80extern void L2_cache_block_writeback_invalidate(unsigned int start,
81 unsigned int end);
82extern void L2_cache_block_invalidate_nowait(unsigned int start,
83 unsigned int end);
84extern void L2_cache_block_writeback_nowait(unsigned int start,
85 unsigned int end);
86
87extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
88 unsigned int end);
89
90#endif /* _ASM_C6X_CACHE_H */
diff --git a/arch/c6x/include/asm/cacheflush.h b/arch/c6x/include/asm/cacheflush.h
new file mode 100644
index 000000000000..df5db90dbe56
--- /dev/null
+++ b/arch/c6x/include/asm/cacheflush.h
@@ -0,0 +1,65 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_CACHEFLUSH_H
12#define _ASM_C6X_CACHEFLUSH_H
13
14#include <linux/spinlock.h>
15
16#include <asm/setup.h>
17#include <asm/cache.h>
18#include <asm/mman.h>
19#include <asm/page.h>
20#include <asm/string.h>
21
22/*
23 * virtually-indexed cache management (our cache is physically indexed)
24 */
25#define flush_cache_all() do {} while (0)
26#define flush_cache_mm(mm) do {} while (0)
27#define flush_cache_dup_mm(mm) do {} while (0)
28#define flush_cache_range(mm, start, end) do {} while (0)
29#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
30#define flush_cache_vmap(start, end) do {} while (0)
31#define flush_cache_vunmap(start, end) do {} while (0)
32#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
33#define flush_dcache_page(page) do {} while (0)
34#define flush_dcache_mmap_lock(mapping) do {} while (0)
35#define flush_dcache_mmap_unlock(mapping) do {} while (0)
36
37/*
38 * physically-indexed cache management
39 */
40#define flush_icache_range(s, e) \
41do { \
42 L1D_cache_block_writeback((s), (e)); \
43 L1P_cache_block_invalidate((s), (e)); \
44} while (0)
45
46#define flush_icache_page(vma, page) \
47do { \
48 if ((vma)->vm_flags & PROT_EXEC) \
49 L1D_cache_block_writeback_invalidate(page_address(page), \
50 (unsigned long) page_address(page) + PAGE_SIZE)); \
51 L1P_cache_block_invalidate(page_address(page), \
52 (unsigned long) page_address(page) + PAGE_SIZE)); \
53} while (0)
54
55
56#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
57do { \
58 memcpy(dst, src, len); \
59 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
60} while (0)
61
62#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
63 memcpy(dst, src, len)
64
65#endif /* _ASM_C6X_CACHEFLUSH_H */
diff --git a/arch/c6x/include/asm/checksum.h b/arch/c6x/include/asm/checksum.h
new file mode 100644
index 000000000000..7246816d6e4d
--- /dev/null
+++ b/arch/c6x/include/asm/checksum.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated
3 * Author: Mark Salter <msalter@redhat.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#ifndef _ASM_C6X_CHECKSUM_H
10#define _ASM_C6X_CHECKSUM_H
11
12static inline __wsum
13csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
14 unsigned short proto, __wsum sum)
15{
16 unsigned long long tmp;
17
18 asm ("add .d1 %1,%5,%1\n"
19 "|| addu .l1 %3,%4,%0\n"
20 "addu .l1 %2,%0,%0\n"
21#ifndef CONFIG_CPU_BIG_ENDIAN
22 "|| shl .s1 %1,8,%1\n"
23#endif
24 "addu .l1 %1,%0,%0\n"
25 "add .l1 %P0,%p0,%2\n"
26 : "=&a"(tmp), "+a"(len), "+a"(sum)
27 : "a" (saddr), "a" (daddr), "a" (proto));
28 return sum;
29}
30#define csum_tcpudp_nofold csum_tcpudp_nofold
31
32#include <asm-generic/checksum.h>
33
34#endif /* _ASM_C6X_CHECKSUM_H */
diff --git a/arch/c6x/include/asm/clkdev.h b/arch/c6x/include/asm/clkdev.h
new file mode 100644
index 000000000000..76a070b1c2e5
--- /dev/null
+++ b/arch/c6x/include/asm/clkdev.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_CLKDEV_H
2#define _ASM_CLKDEV_H
3
4#include <linux/slab.h>
5
6struct clk;
7
8static inline int __clk_get(struct clk *clk)
9{
10 return 1;
11}
12
13static inline void __clk_put(struct clk *clk)
14{
15}
16
17static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
18{
19 return kzalloc(size, GFP_KERNEL);
20}
21
22#endif /* _ASM_CLKDEV_H */
diff --git a/arch/c6x/include/asm/clock.h b/arch/c6x/include/asm/clock.h
new file mode 100644
index 000000000000..bcf42b2b4b1e
--- /dev/null
+++ b/arch/c6x/include/asm/clock.h
@@ -0,0 +1,148 @@
1/*
2 * TI C64X clock definitions
3 *
4 * Copyright (C) 2010, 2011 Texas Instruments.
5 * Contributed by: Mark Salter <msalter@redhat.com>
6 *
7 * Copied heavily from arm/mach-davinci/clock.h, so:
8 *
9 * Copyright (C) 2006-2007 Texas Instruments.
10 * Copyright (C) 2008-2009 Deep Root Systems, LLC
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#ifndef _ASM_C6X_CLOCK_H
18#define _ASM_C6X_CLOCK_H
19
20#ifndef __ASSEMBLER__
21
22#include <linux/list.h>
23
24/* PLL/Reset register offsets */
25#define PLLCTL 0x100
26#define PLLM 0x110
27#define PLLPRE 0x114
28#define PLLDIV1 0x118
29#define PLLDIV2 0x11c
30#define PLLDIV3 0x120
31#define PLLPOST 0x128
32#define PLLCMD 0x138
33#define PLLSTAT 0x13c
34#define PLLALNCTL 0x140
35#define PLLDCHANGE 0x144
36#define PLLCKEN 0x148
37#define PLLCKSTAT 0x14c
38#define PLLSYSTAT 0x150
39#define PLLDIV4 0x160
40#define PLLDIV5 0x164
41#define PLLDIV6 0x168
42#define PLLDIV7 0x16c
43#define PLLDIV8 0x170
44#define PLLDIV9 0x174
45#define PLLDIV10 0x178
46#define PLLDIV11 0x17c
47#define PLLDIV12 0x180
48#define PLLDIV13 0x184
49#define PLLDIV14 0x188
50#define PLLDIV15 0x18c
51#define PLLDIV16 0x190
52
53/* PLLM register bits */
54#define PLLM_PLLM_MASK 0xff
55#define PLLM_VAL(x) ((x) - 1)
56
57/* PREDIV register bits */
58#define PLLPREDIV_EN BIT(15)
59#define PLLPREDIV_VAL(x) ((x) - 1)
60
61/* PLLCTL register bits */
62#define PLLCTL_PLLEN BIT(0)
63#define PLLCTL_PLLPWRDN BIT(1)
64#define PLLCTL_PLLRST BIT(3)
65#define PLLCTL_PLLDIS BIT(4)
66#define PLLCTL_PLLENSRC BIT(5)
67#define PLLCTL_CLKMODE BIT(8)
68
69/* PLLCMD register bits */
70#define PLLCMD_GOSTAT BIT(0)
71
72/* PLLSTAT register bits */
73#define PLLSTAT_GOSTAT BIT(0)
74
75/* PLLDIV register bits */
76#define PLLDIV_EN BIT(15)
77#define PLLDIV_RATIO_MASK 0x1f
78#define PLLDIV_RATIO(x) ((x) - 1)
79
80struct pll_data;
81
82struct clk {
83 struct list_head node;
84 struct module *owner;
85 const char *name;
86 unsigned long rate;
87 int usecount;
88 u32 flags;
89 struct clk *parent;
90 struct list_head children; /* list of children */
91 struct list_head childnode; /* parent's child list node */
92 struct pll_data *pll_data;
93 u32 div;
94 unsigned long (*recalc) (struct clk *);
95 int (*set_rate) (struct clk *clk, unsigned long rate);
96 int (*round_rate) (struct clk *clk, unsigned long rate);
97};
98
99/* Clock flags: SoC-specific flags start at BIT(16) */
100#define ALWAYS_ENABLED BIT(1)
101#define CLK_PLL BIT(2) /* PLL-derived clock */
102#define PRE_PLL BIT(3) /* source is before PLL mult/div */
103#define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
104#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */
105
106#define MAX_PLL_SYSCLKS 16
107
108struct pll_data {
109 void __iomem *base;
110 u32 num;
111 u32 flags;
112 u32 input_rate;
113 u32 bypass_delay; /* in loops */
114 u32 reset_delay; /* in loops */
115 u32 lock_delay; /* in loops */
116 struct clk sysclks[MAX_PLL_SYSCLKS + 1];
117};
118
119/* pll_data flag bit */
120#define PLL_HAS_PRE BIT(0)
121#define PLL_HAS_MUL BIT(1)
122#define PLL_HAS_POST BIT(2)
123
124#define CLK(dev, con, ck) \
125 { \
126 .dev_id = dev, \
127 .con_id = con, \
128 .clk = ck, \
129 } \
130
131extern void c6x_clks_init(struct clk_lookup *clocks);
132extern int clk_register(struct clk *clk);
133extern void clk_unregister(struct clk *clk);
134extern void c64x_setup_clocks(void);
135
136extern struct pll_data c6x_soc_pll1;
137
138extern struct clk clkin1;
139extern struct clk c6x_core_clk;
140extern struct clk c6x_i2c_clk;
141extern struct clk c6x_watchdog_clk;
142extern struct clk c6x_mcbsp1_clk;
143extern struct clk c6x_mcbsp2_clk;
144extern struct clk c6x_mdio_clk;
145
146#endif
147
148#endif /* _ASM_C6X_CLOCK_H */
diff --git a/arch/c6x/include/asm/delay.h b/arch/c6x/include/asm/delay.h
new file mode 100644
index 000000000000..f314c2e9eb54
--- /dev/null
+++ b/arch/c6x/include/asm/delay.h
@@ -0,0 +1,67 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_DELAY_H
12#define _ASM_C6X_DELAY_H
13
14#include <linux/kernel.h>
15
16extern unsigned int ticks_per_ns_scaled;
17
18static inline void __delay(unsigned long loops)
19{
20 uint32_t tmp;
21
22 /* 6 cycles per loop */
23 asm volatile (" mv .s1 %0,%1\n"
24 "0: [%1] b .s1 0b\n"
25 " add .l1 -6,%0,%0\n"
26 " cmplt .l1 1,%0,%1\n"
27 " nop 3\n"
28 : "+a"(loops), "=A"(tmp));
29}
30
31static inline void _c6x_tickdelay(unsigned int x)
32{
33 uint32_t cnt, endcnt;
34
35 asm volatile (" mvc .s2 TSCL,%0\n"
36 " add .s2x %0,%1,%2\n"
37 " || mvk .l2 1,B0\n"
38 "0: [B0] b .s2 0b\n"
39 " mvc .s2 TSCL,%0\n"
40 " sub .s2 %0,%2,%0\n"
41 " cmpgt .l2 0,%0,B0\n"
42 " nop 2\n"
43 : "=b"(cnt), "+a"(x), "=b"(endcnt) : : "B0");
44}
45
46/* use scaled math to avoid slow division */
47#define C6X_NDELAY_SCALE 10
48
49static inline void _ndelay(unsigned int n)
50{
51 _c6x_tickdelay((ticks_per_ns_scaled * n) >> C6X_NDELAY_SCALE);
52}
53
54static inline void _udelay(unsigned int n)
55{
56 while (n >= 10) {
57 _ndelay(10000);
58 n -= 10;
59 }
60 while (n-- > 0)
61 _ndelay(1000);
62}
63
64#define udelay(x) _udelay((unsigned int)(x))
65#define ndelay(x) _ndelay((unsigned int)(x))
66
67#endif /* _ASM_C6X_DELAY_H */
diff --git a/arch/c6x/include/asm/dma-mapping.h b/arch/c6x/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..03579fd99dba
--- /dev/null
+++ b/arch/c6x/include/asm/dma-mapping.h
@@ -0,0 +1,91 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot <aurelien.jacquiot@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#ifndef _ASM_C6X_DMA_MAPPING_H
13#define _ASM_C6X_DMA_MAPPING_H
14
15#include <linux/dma-debug.h>
16#include <asm-generic/dma-coherent.h>
17
18#define dma_supported(d, m) 1
19
20static inline int dma_set_mask(struct device *dev, u64 dma_mask)
21{
22 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
23 return -EIO;
24
25 *dev->dma_mask = dma_mask;
26
27 return 0;
28}
29
30/*
31 * DMA errors are defined by all-bits-set in the DMA address.
32 */
33static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
34{
35 return dma_addr == ~0;
36}
37
38extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
39 size_t size, enum dma_data_direction dir);
40
41extern void dma_unmap_single(struct device *dev, dma_addr_t handle,
42 size_t size, enum dma_data_direction dir);
43
44extern int dma_map_sg(struct device *dev, struct scatterlist *sglist,
45 int nents, enum dma_data_direction direction);
46
47extern void dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
48 int nents, enum dma_data_direction direction);
49
50static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
51 unsigned long offset, size_t size,
52 enum dma_data_direction dir)
53{
54 dma_addr_t handle;
55
56 handle = dma_map_single(dev, page_address(page) + offset, size, dir);
57
58 debug_dma_map_page(dev, page, offset, size, dir, handle, false);
59
60 return handle;
61}
62
63static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
64 size_t size, enum dma_data_direction dir)
65{
66 dma_unmap_single(dev, handle, size, dir);
67
68 debug_dma_unmap_page(dev, handle, size, dir, false);
69}
70
71extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
72 size_t size, enum dma_data_direction dir);
73
74extern void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
75 size_t size,
76 enum dma_data_direction dir);
77
78extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
79 int nents, enum dma_data_direction dir);
80
81extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
82 int nents, enum dma_data_direction dir);
83
84extern void coherent_mem_init(u32 start, u32 size);
85extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
86extern void dma_free_coherent(struct device *, size_t, void *, dma_addr_t);
87
88#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent((d), (s), (h), (f))
89#define dma_free_noncoherent(d, s, v, h) dma_free_coherent((d), (s), (v), (h))
90
91#endif /* _ASM_C6X_DMA_MAPPING_H */
diff --git a/arch/c6x/include/asm/dscr.h b/arch/c6x/include/asm/dscr.h
new file mode 100644
index 000000000000..561ba8332042
--- /dev/null
+++ b/arch/c6x/include/asm/dscr.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated
3 * Author: Mark Salter <msalter@redhat.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10#ifndef _ASM_C6X_DSCR_H
11#define _ASM_C6X_DSCR_H
12
13enum dscr_devstate_t {
14 DSCR_DEVSTATE_ENABLED,
15 DSCR_DEVSTATE_DISABLED,
16};
17
18/*
19 * Set the device state of the device with the given ID.
20 *
21 * Individual drivers should use this to enable or disable the
22 * hardware device. The devid used to identify the device being
23 * controlled should be a property in the device's tree node.
24 */
25extern void dscr_set_devstate(int devid, enum dscr_devstate_t state);
26
27/*
28 * Assert or de-assert an RMII reset.
29 */
30extern void dscr_rmii_reset(int id, int assert);
31
32extern void dscr_probe(void);
33
34#endif /* _ASM_C6X_DSCR_H */
diff --git a/arch/c6x/include/asm/elf.h b/arch/c6x/include/asm/elf.h
new file mode 100644
index 000000000000..d57865ba2c44
--- /dev/null
+++ b/arch/c6x/include/asm/elf.h
@@ -0,0 +1,113 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_ELF_H
12#define _ASM_C6X_ELF_H
13
14/*
15 * ELF register definitions..
16 */
17#include <asm/ptrace.h>
18
19typedef unsigned long elf_greg_t;
20typedef unsigned long elf_fpreg_t;
21
22#define ELF_NGREG 58
23#define ELF_NFPREG 1
24
25typedef elf_greg_t elf_gregset_t[ELF_NGREG];
26typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
27
28/*
29 * This is used to ensure we don't load something for the wrong architecture.
30 */
31#define elf_check_arch(x) ((x)->e_machine == EM_TI_C6000)
32
33#define elf_check_const_displacement(x) (1)
34
35/*
36 * These are used to set parameters in the core dumps.
37 */
38#ifdef __LITTLE_ENDIAN__
39#define ELF_DATA ELFDATA2LSB
40#else
41#define ELF_DATA ELFDATA2MSB
42#endif
43
44#define ELF_CLASS ELFCLASS32
45#define ELF_ARCH EM_TI_C6000
46
47/* Nothing for now. Need to setup DP... */
48#define ELF_PLAT_INIT(_r)
49
50#define USE_ELF_CORE_DUMP
51#define ELF_EXEC_PAGESIZE 4096
52
53#define ELF_CORE_COPY_REGS(_dest, _regs) \
54 memcpy((char *) &_dest, (char *) _regs, \
55 sizeof(struct pt_regs));
56
57/* This yields a mask that user programs can use to figure out what
58 instruction set this cpu supports. */
59
60#define ELF_HWCAP (0)
61
62/* This yields a string that ld.so will use to load implementation
63 specific libraries for optimization. This is more specific in
64 intent than poking at uname or /proc/cpuinfo. */
65
66#define ELF_PLATFORM (NULL)
67
68#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
69
70/* C6X specific section types */
71#define SHT_C6000_UNWIND 0x70000001
72#define SHT_C6000_PREEMPTMAP 0x70000002
73#define SHT_C6000_ATTRIBUTES 0x70000003
74
75/* C6X specific DT_ tags */
76#define DT_C6000_DSBT_BASE 0x70000000
77#define DT_C6000_DSBT_SIZE 0x70000001
78#define DT_C6000_PREEMPTMAP 0x70000002
79#define DT_C6000_DSBT_INDEX 0x70000003
80
81/* C6X specific relocs */
82#define R_C6000_NONE 0
83#define R_C6000_ABS32 1
84#define R_C6000_ABS16 2
85#define R_C6000_ABS8 3
86#define R_C6000_PCR_S21 4
87#define R_C6000_PCR_S12 5
88#define R_C6000_PCR_S10 6
89#define R_C6000_PCR_S7 7
90#define R_C6000_ABS_S16 8
91#define R_C6000_ABS_L16 9
92#define R_C6000_ABS_H16 10
93#define R_C6000_SBR_U15_B 11
94#define R_C6000_SBR_U15_H 12
95#define R_C6000_SBR_U15_W 13
96#define R_C6000_SBR_S16 14
97#define R_C6000_SBR_L16_B 15
98#define R_C6000_SBR_L16_H 16
99#define R_C6000_SBR_L16_W 17
100#define R_C6000_SBR_H16_B 18
101#define R_C6000_SBR_H16_H 19
102#define R_C6000_SBR_H16_W 20
103#define R_C6000_SBR_GOT_U15_W 21
104#define R_C6000_SBR_GOT_L16_W 22
105#define R_C6000_SBR_GOT_H16_W 23
106#define R_C6000_DSBT_INDEX 24
107#define R_C6000_PREL31 25
108#define R_C6000_COPY 26
109#define R_C6000_ALIGN 253
110#define R_C6000_FPHEAD 254
111#define R_C6000_NOCMP 255
112
113#endif /*_ASM_C6X_ELF_H */
diff --git a/arch/c6x/include/asm/ftrace.h b/arch/c6x/include/asm/ftrace.h
new file mode 100644
index 000000000000..3701958d3d1c
--- /dev/null
+++ b/arch/c6x/include/asm/ftrace.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_C6X_FTRACE_H
2#define _ASM_C6X_FTRACE_H
3
4/* empty */
5
6#endif /* _ASM_C6X_FTRACE_H */
diff --git a/arch/c6x/include/asm/hardirq.h b/arch/c6x/include/asm/hardirq.h
new file mode 100644
index 000000000000..9621954f98f4
--- /dev/null
+++ b/arch/c6x/include/asm/hardirq.h
@@ -0,0 +1,20 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _ASM_C6X_HARDIRQ_H
13#define _ASM_C6X_HARDIRQ_H
14
15extern void ack_bad_irq(int irq);
16#define ack_bad_irq ack_bad_irq
17
18#include <asm-generic/hardirq.h>
19
20#endif /* _ASM_C6X_HARDIRQ_H */
diff --git a/arch/c6x/include/asm/irq.h b/arch/c6x/include/asm/irq.h
new file mode 100644
index 000000000000..a6ae3c9d9c40
--- /dev/null
+++ b/arch/c6x/include/asm/irq.h
@@ -0,0 +1,302 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * Large parts taken directly from powerpc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef _ASM_C6X_IRQ_H
14#define _ASM_C6X_IRQ_H
15
16#include <linux/threads.h>
17#include <linux/list.h>
18#include <linux/radix-tree.h>
19#include <asm/percpu.h>
20
21#define irq_canonicalize(irq) (irq)
22
23/*
24 * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
25 * are reserved. The remaining 12 vectors are used to route SoC interrupts.
26 * These interrupt vectors are prioritized with IRQ 4 having the highest
27 * priority and IRQ 15 having the lowest.
28 *
29 * The C64x+ megamodule provides a PIC which combines SoC IRQ sources into a
30 * single core IRQ vector. There are four combined sources, each of which
31 * feed into one of the 12 general interrupt vectors. The remaining 8 vectors
32 * can each route a single SoC interrupt directly.
33 */
34#define NR_PRIORITY_IRQS 16
35
36#define NR_IRQS_LEGACY NR_PRIORITY_IRQS
37
38/* Total number of virq in the platform */
39#define NR_IRQS 256
40
41/* This number is used when no interrupt has been assigned */
42#define NO_IRQ 0
43
44/* This type is the placeholder for a hardware interrupt number. It has to
45 * be big enough to enclose whatever representation is used by a given
46 * platform.
47 */
48typedef unsigned long irq_hw_number_t;
49
50/* Interrupt controller "host" data structure. This could be defined as a
51 * irq domain controller. That is, it handles the mapping between hardware
52 * and virtual interrupt numbers for a given interrupt domain. The host
53 * structure is generally created by the PIC code for a given PIC instance
54 * (though a host can cover more than one PIC if they have a flat number
55 * model). It's the host callbacks that are responsible for setting the
56 * irq_chip on a given irq_desc after it's been mapped.
57 *
58 * The host code and data structures are fairly agnostic to the fact that
59 * we use an open firmware device-tree. We do have references to struct
60 * device_node in two places: in irq_find_host() to find the host matching
61 * a given interrupt controller node, and of course as an argument to its
62 * counterpart host->ops->match() callback. However, those are treated as
63 * generic pointers by the core and the fact that it's actually a device-node
64 * pointer is purely a convention between callers and implementation. This
65 * code could thus be used on other architectures by replacing those two
66 * by some sort of arch-specific void * "token" used to identify interrupt
67 * controllers.
68 */
69struct irq_host;
70struct radix_tree_root;
71struct device_node;
72
73/* Functions below are provided by the host and called whenever a new mapping
74 * is created or an old mapping is disposed. The host can then proceed to
75 * whatever internal data structures management is required. It also needs
76 * to setup the irq_desc when returning from map().
77 */
78struct irq_host_ops {
79 /* Match an interrupt controller device node to a host, returns
80 * 1 on a match
81 */
82 int (*match)(struct irq_host *h, struct device_node *node);
83
84 /* Create or update a mapping between a virtual irq number and a hw
85 * irq number. This is called only once for a given mapping.
86 */
87 int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
88
89 /* Dispose of such a mapping */
90 void (*unmap)(struct irq_host *h, unsigned int virq);
91
92 /* Translate device-tree interrupt specifier from raw format coming
93 * from the firmware to a irq_hw_number_t (interrupt line number) and
94 * type (sense) that can be passed to set_irq_type(). In the absence
95 * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
96 * will return the hw number in the first cell and IRQ_TYPE_NONE for
97 * the type (which amount to keeping whatever default value the
98 * interrupt controller has for that line)
99 */
100 int (*xlate)(struct irq_host *h, struct device_node *ctrler,
101 const u32 *intspec, unsigned int intsize,
102 irq_hw_number_t *out_hwirq, unsigned int *out_type);
103};
104
105struct irq_host {
106 struct list_head link;
107
108 /* type of reverse mapping technique */
109 unsigned int revmap_type;
110#define IRQ_HOST_MAP_PRIORITY 0 /* core priority irqs, get irqs 1..15 */
111#define IRQ_HOST_MAP_NOMAP 1 /* no fast reverse mapping */
112#define IRQ_HOST_MAP_LINEAR 2 /* linear map of interrupts */
113#define IRQ_HOST_MAP_TREE 3 /* radix tree */
114 union {
115 struct {
116 unsigned int size;
117 unsigned int *revmap;
118 } linear;
119 struct radix_tree_root tree;
120 } revmap_data;
121 struct irq_host_ops *ops;
122 void *host_data;
123 irq_hw_number_t inval_irq;
124
125 /* Optional device node pointer */
126 struct device_node *of_node;
127};
128
129struct irq_data;
130extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
131extern irq_hw_number_t virq_to_hw(unsigned int virq);
132extern bool virq_is_host(unsigned int virq, struct irq_host *host);
133
134/**
135 * irq_alloc_host - Allocate a new irq_host data structure
136 * @of_node: optional device-tree node of the interrupt controller
137 * @revmap_type: type of reverse mapping to use
138 * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
139 * @ops: map/unmap host callbacks
140 * @inval_irq: provide a hw number in that host space that is always invalid
141 *
142 * Allocates and initialize and irq_host structure. Note that in the case of
143 * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
144 * for all legacy interrupts except 0 (which is always the invalid irq for
145 * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
146 * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
147 * later during boot automatically (the reverse mapping will use the slow path
148 * until that happens).
149 */
150extern struct irq_host *irq_alloc_host(struct device_node *of_node,
151 unsigned int revmap_type,
152 unsigned int revmap_arg,
153 struct irq_host_ops *ops,
154 irq_hw_number_t inval_irq);
155
156
157/**
158 * irq_find_host - Locates a host for a given device node
159 * @node: device-tree node of the interrupt controller
160 */
161extern struct irq_host *irq_find_host(struct device_node *node);
162
163
164/**
165 * irq_set_default_host - Set a "default" host
166 * @host: default host pointer
167 *
168 * For convenience, it's possible to set a "default" host that will be used
169 * whenever NULL is passed to irq_create_mapping(). It makes life easier for
170 * platforms that want to manipulate a few hard coded interrupt numbers that
171 * aren't properly represented in the device-tree.
172 */
173extern void irq_set_default_host(struct irq_host *host);
174
175
176/**
177 * irq_set_virq_count - Set the maximum number of virt irqs
178 * @count: number of linux virtual irqs, capped with NR_IRQS
179 *
180 * This is mainly for use by platforms like iSeries who want to program
181 * the virtual irq number in the controller to avoid the reverse mapping
182 */
183extern void irq_set_virq_count(unsigned int count);
184
185
186/**
187 * irq_create_mapping - Map a hardware interrupt into linux virq space
188 * @host: host owning this hardware interrupt or NULL for default host
189 * @hwirq: hardware irq number in that host space
190 *
191 * Only one mapping per hardware interrupt is permitted. Returns a linux
192 * virq number.
193 * If the sense/trigger is to be specified, set_irq_type() should be called
194 * on the number returned from that call.
195 */
196extern unsigned int irq_create_mapping(struct irq_host *host,
197 irq_hw_number_t hwirq);
198
199
200/**
201 * irq_dispose_mapping - Unmap an interrupt
202 * @virq: linux virq number of the interrupt to unmap
203 */
204extern void irq_dispose_mapping(unsigned int virq);
205
206/**
207 * irq_find_mapping - Find a linux virq from an hw irq number.
208 * @host: host owning this hardware interrupt
209 * @hwirq: hardware irq number in that host space
210 *
211 * This is a slow path, for use by generic code. It's expected that an
212 * irq controller implementation directly calls the appropriate low level
213 * mapping function.
214 */
215extern unsigned int irq_find_mapping(struct irq_host *host,
216 irq_hw_number_t hwirq);
217
218/**
219 * irq_create_direct_mapping - Allocate a virq for direct mapping
220 * @host: host to allocate the virq for or NULL for default host
221 *
222 * This routine is used for irq controllers which can choose the hardware
223 * interrupt numbers they generate. In such a case it's simplest to use
224 * the linux virq as the hardware interrupt number.
225 */
226extern unsigned int irq_create_direct_mapping(struct irq_host *host);
227
228/**
229 * irq_radix_revmap_insert - Insert a hw irq to linux virq number mapping.
230 * @host: host owning this hardware interrupt
231 * @virq: linux irq number
232 * @hwirq: hardware irq number in that host space
233 *
234 * This is for use by irq controllers that use a radix tree reverse
235 * mapping for fast lookup.
236 */
237extern void irq_radix_revmap_insert(struct irq_host *host, unsigned int virq,
238 irq_hw_number_t hwirq);
239
240/**
241 * irq_radix_revmap_lookup - Find a linux virq from a hw irq number.
242 * @host: host owning this hardware interrupt
243 * @hwirq: hardware irq number in that host space
244 *
245 * This is a fast path, for use by irq controller code that uses radix tree
246 * revmaps
247 */
248extern unsigned int irq_radix_revmap_lookup(struct irq_host *host,
249 irq_hw_number_t hwirq);
250
251/**
252 * irq_linear_revmap - Find a linux virq from a hw irq number.
253 * @host: host owning this hardware interrupt
254 * @hwirq: hardware irq number in that host space
255 *
256 * This is a fast path, for use by irq controller code that uses linear
257 * revmaps. It does fallback to the slow path if the revmap doesn't exist
258 * yet and will create the revmap entry with appropriate locking
259 */
260
261extern unsigned int irq_linear_revmap(struct irq_host *host,
262 irq_hw_number_t hwirq);
263
264
265
266/**
267 * irq_alloc_virt - Allocate virtual irq numbers
268 * @host: host owning these new virtual irqs
269 * @count: number of consecutive numbers to allocate
270 * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
271 *
272 * This is a low level function that is used internally by irq_create_mapping()
273 * and that can be used by some irq controllers implementations for things
274 * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
275 */
276extern unsigned int irq_alloc_virt(struct irq_host *host,
277 unsigned int count,
278 unsigned int hint);
279
280/**
281 * irq_free_virt - Free virtual irq numbers
282 * @virq: virtual irq number of the first interrupt to free
283 * @count: number of interrupts to free
284 *
285 * This function is the opposite of irq_alloc_virt. It will not clear reverse
286 * maps, this should be done previously by unmap'ing the interrupt. In fact,
287 * all interrupts covered by the range being freed should have been unmapped
288 * prior to calling this.
289 */
290extern void irq_free_virt(unsigned int virq, unsigned int count);
291
292extern void __init init_pic_c64xplus(void);
293
294extern void init_IRQ(void);
295
296struct pt_regs;
297
298extern asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs);
299
300extern unsigned long irq_err_count;
301
302#endif /* _ASM_C6X_IRQ_H */
diff --git a/arch/c6x/include/asm/irqflags.h b/arch/c6x/include/asm/irqflags.h
new file mode 100644
index 000000000000..cf78e09e18c3
--- /dev/null
+++ b/arch/c6x/include/asm/irqflags.h
@@ -0,0 +1,72 @@
1/*
2 * C6X IRQ flag handling
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated
5 * Written by Mark Salter (msalter@redhat.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public Licence
9 * as published by the Free Software Foundation; either version
10 * 2 of the Licence, or (at your option) any later version.
11 */
12
13#ifndef _ASM_IRQFLAGS_H
14#define _ASM_IRQFLAGS_H
15
16#ifndef __ASSEMBLY__
17
18/* read interrupt enabled status */
19static inline unsigned long arch_local_save_flags(void)
20{
21 unsigned long flags;
22
23 asm volatile (" mvc .s2 CSR,%0\n" : "=b"(flags));
24 return flags;
25}
26
27/* set interrupt enabled status */
28static inline void arch_local_irq_restore(unsigned long flags)
29{
30 asm volatile (" mvc .s2 %0,CSR\n" : : "b"(flags));
31}
32
33/* unconditionally enable interrupts */
34static inline void arch_local_irq_enable(void)
35{
36 unsigned long flags = arch_local_save_flags();
37 flags |= 1;
38 arch_local_irq_restore(flags);
39}
40
41/* unconditionally disable interrupts */
42static inline void arch_local_irq_disable(void)
43{
44 unsigned long flags = arch_local_save_flags();
45 flags &= ~1;
46 arch_local_irq_restore(flags);
47}
48
49/* get status and disable interrupts */
50static inline unsigned long arch_local_irq_save(void)
51{
52 unsigned long flags;
53
54 flags = arch_local_save_flags();
55 arch_local_irq_restore(flags & ~1);
56 return flags;
57}
58
59/* test flags */
60static inline int arch_irqs_disabled_flags(unsigned long flags)
61{
62 return (flags & 1) == 0;
63}
64
65/* test hardware interrupt enable bit */
66static inline int arch_irqs_disabled(void)
67{
68 return arch_irqs_disabled_flags(arch_local_save_flags());
69}
70
71#endif /* __ASSEMBLY__ */
72#endif /* __ASM_IRQFLAGS_H */
diff --git a/arch/c6x/include/asm/linkage.h b/arch/c6x/include/asm/linkage.h
new file mode 100644
index 000000000000..376925c47d57
--- /dev/null
+++ b/arch/c6x/include/asm/linkage.h
@@ -0,0 +1,30 @@
1#ifndef _ASM_C6X_LINKAGE_H
2#define _ASM_C6X_LINKAGE_H
3
4#ifdef __ASSEMBLER__
5
6#define __ALIGN .align 2
7#define __ALIGN_STR ".align 2"
8
9#ifndef __DSBT__
10#define ENTRY(name) \
11 .global name @ \
12 __ALIGN @ \
13name:
14#else
15#define ENTRY(name) \
16 .global name @ \
17 .hidden name @ \
18 __ALIGN @ \
19name:
20#endif
21
22#define ENDPROC(name) \
23 .type name, @function @ \
24 .size name, . - name
25
26#endif
27
28#include <asm-generic/linkage.h>
29
30#endif /* _ASM_C6X_LINKAGE_H */
diff --git a/arch/c6x/include/asm/megamod-pic.h b/arch/c6x/include/asm/megamod-pic.h
new file mode 100644
index 000000000000..eca0a8678034
--- /dev/null
+++ b/arch/c6x/include/asm/megamod-pic.h
@@ -0,0 +1,9 @@
1#ifndef _C6X_MEGAMOD_PIC_H
2#define _C6X_MEGAMOD_PIC_H
3
4#ifdef __KERNEL__
5
6extern void __init megamod_pic_init(void);
7
8#endif /* __KERNEL__ */
9#endif /* _C6X_MEGAMOD_PIC_H */
diff --git a/arch/c6x/include/asm/mmu.h b/arch/c6x/include/asm/mmu.h
new file mode 100644
index 000000000000..41592bf16067
--- /dev/null
+++ b/arch/c6x/include/asm/mmu.h
@@ -0,0 +1,18 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_MMU_H
12#define _ASM_C6X_MMU_H
13
14typedef struct {
15 unsigned long end_brk;
16} mm_context_t;
17
18#endif /* _ASM_C6X_MMU_H */
diff --git a/arch/c6x/include/asm/module.h b/arch/c6x/include/asm/module.h
new file mode 100644
index 000000000000..a453f9744f42
--- /dev/null
+++ b/arch/c6x/include/asm/module.h
@@ -0,0 +1,33 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * Updated for 2.6.34 by: Mark Salter (msalter@redhat.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef _ASM_C6X_MODULE_H
14#define _ASM_C6X_MODULE_H
15
16#define Elf_Shdr Elf32_Shdr
17#define Elf_Sym Elf32_Sym
18#define Elf_Ehdr Elf32_Ehdr
19#define Elf_Addr Elf32_Addr
20#define Elf_Word Elf32_Word
21
22/*
23 * This file contains the C6x architecture specific module code.
24 */
25struct mod_arch_specific {
26};
27
28struct loaded_sections {
29 unsigned int new_vaddr;
30 unsigned int loaded;
31};
32
33#endif /* _ASM_C6X_MODULE_H */
diff --git a/arch/c6x/include/asm/mutex.h b/arch/c6x/include/asm/mutex.h
new file mode 100644
index 000000000000..7a7248e0462d
--- /dev/null
+++ b/arch/c6x/include/asm/mutex.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_C6X_MUTEX_H
2#define _ASM_C6X_MUTEX_H
3
4#include <asm-generic/mutex-null.h>
5
6#endif /* _ASM_C6X_MUTEX_H */
diff --git a/arch/c6x/include/asm/page.h b/arch/c6x/include/asm/page.h
new file mode 100644
index 000000000000..d18e2b0c7aea
--- /dev/null
+++ b/arch/c6x/include/asm/page.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_C6X_PAGE_H
2#define _ASM_C6X_PAGE_H
3
4#define VM_DATA_DEFAULT_FLAGS \
5 (VM_READ | VM_WRITE | \
6 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
7 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
8
9#include <asm-generic/page.h>
10
11#endif /* _ASM_C6X_PAGE_H */
diff --git a/arch/c6x/include/asm/pgtable.h b/arch/c6x/include/asm/pgtable.h
new file mode 100644
index 000000000000..68c8af4f1f97
--- /dev/null
+++ b/arch/c6x/include/asm/pgtable.h
@@ -0,0 +1,81 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_PGTABLE_H
12#define _ASM_C6X_PGTABLE_H
13
14#include <asm-generic/4level-fixup.h>
15
16#include <asm/setup.h>
17#include <asm/page.h>
18
19/*
20 * All 32bit addresses are effectively valid for vmalloc...
21 * Sort of meaningless for non-VM targets.
22 */
23#define VMALLOC_START 0
24#define VMALLOC_END 0xffffffff
25
26#define pgd_present(pgd) (1)
27#define pgd_none(pgd) (0)
28#define pgd_bad(pgd) (0)
29#define pgd_clear(pgdp)
30#define kern_addr_valid(addr) (1)
31
32#define pmd_offset(a, b) ((void *)0)
33#define pmd_none(x) (!pmd_val(x))
34#define pmd_present(x) (pmd_val(x))
35#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
36#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
37
38#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
39#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
40#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
41#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
42#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
43#define pgprot_noncached(prot) (prot)
44
45extern void paging_init(void);
46
47#define __swp_type(x) (0)
48#define __swp_offset(x) (0)
49#define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
50#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
51#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
52
53static inline int pte_file(pte_t pte)
54{
55 return 0;
56}
57
58#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
59#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
60
61/*
62 * ZERO_PAGE is a global shared page that is always zero: used
63 * for zero-mapped memory areas etc..
64 */
65#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
66extern unsigned long empty_zero_page;
67
68#define swapper_pg_dir ((pgd_t *) 0)
69
70/*
71 * No page table caches to initialise
72 */
73#define pgtable_cache_init() do { } while (0)
74#define io_remap_pfn_range remap_pfn_range
75
76#define io_remap_page_range(vma, vaddr, paddr, size, prot) \
77 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
78
79#include <asm-generic/pgtable.h>
80
81#endif /* _ASM_C6X_PGTABLE_H */
diff --git a/arch/c6x/include/asm/processor.h b/arch/c6x/include/asm/processor.h
new file mode 100644
index 000000000000..8154c4ee8c9c
--- /dev/null
+++ b/arch/c6x/include/asm/processor.h
@@ -0,0 +1,132 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * Updated for 2.6.34: Mark Salter <msalter@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef _ASM_C6X_PROCESSOR_H
14#define _ASM_C6X_PROCESSOR_H
15
16#include <asm/ptrace.h>
17#include <asm/page.h>
18#include <asm/current.h>
19
20/*
21 * Default implementation of macro that returns current
22 * instruction pointer ("program counter").
23 */
24#define current_text_addr() \
25({ \
26 void *__pc; \
27 asm("mvc .S2 pce1,%0\n" : "=b"(__pc)); \
28 __pc; \
29})
30
31/*
32 * User space process size. This is mostly meaningless for NOMMU
33 * but some C6X processors may have RAM addresses up to 0xFFFFFFFF.
34 * Since calls like mmap() can return an address or an error, we
35 * have to allow room for error returns when code does something
36 * like:
37 *
38 * addr = do_mmap(...)
39 * if ((unsigned long)addr >= TASK_SIZE)
40 * ... its an error code, not an address ...
41 *
42 * Here, we allow for 4096 error codes which means we really can't
43 * use the last 4K page on systems with RAM extending all the way
44 * to the end of the 32-bit address space.
45 */
46#define TASK_SIZE 0xFFFFF000
47
48/*
49 * This decides where the kernel will search for a free chunk of vm
50 * space during mmap's. We won't be using it
51 */
52#define TASK_UNMAPPED_BASE 0
53
54struct thread_struct {
55 unsigned long long b15_14;
56 unsigned long long a15_14;
57 unsigned long long b13_12;
58 unsigned long long a13_12;
59 unsigned long long b11_10;
60 unsigned long long a11_10;
61 unsigned long long ricl_icl;
62 unsigned long usp; /* user stack pointer */
63 unsigned long pc; /* kernel pc */
64 unsigned long wchan;
65};
66
67#define INIT_THREAD \
68{ \
69 .usp = 0, \
70 .wchan = 0, \
71}
72
73#define INIT_MMAP { \
74 &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \
75 NULL, NULL }
76
77#define task_pt_regs(task) \
78 ((struct pt_regs *)(THREAD_START_SP + task_stack_page(task)) - 1)
79
80#define alloc_kernel_stack() __get_free_page(GFP_KERNEL)
81#define free_kernel_stack(page) free_page((page))
82
83
84/* Forward declaration, a strange C thing */
85struct task_struct;
86
87extern void start_thread(struct pt_regs *regs, unsigned int pc,
88 unsigned long usp);
89
90/* Free all resources held by a thread. */
91static inline void release_thread(struct task_struct *dead_task)
92{
93}
94
95/* Prepare to copy thread state - unlazy all lazy status */
96#define prepare_to_copy(tsk) do { } while (0)
97
98extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
99
100#define copy_segments(tsk, mm) do { } while (0)
101#define release_segments(mm) do { } while (0)
102
103/*
104 * saved PC of a blocked thread.
105 */
106#define thread_saved_pc(tsk) (task_pt_regs(tsk)->pc)
107
108/*
109 * saved kernel SP and DP of a blocked thread.
110 */
111#ifdef _BIG_ENDIAN
112#define thread_saved_ksp(tsk) \
113 (*(unsigned long *)&(tsk)->thread.b15_14)
114#define thread_saved_dp(tsk) \
115 (*(((unsigned long *)&(tsk)->thread.b15_14) + 1))
116#else
117#define thread_saved_ksp(tsk) \
118 (*(((unsigned long *)&(tsk)->thread.b15_14) + 1))
119#define thread_saved_dp(tsk) \
120 (*(unsigned long *)&(tsk)->thread.b15_14)
121#endif
122
123extern unsigned long get_wchan(struct task_struct *p);
124
125#define KSTK_EIP(tsk) (task_pt_regs(task)->pc)
126#define KSTK_ESP(tsk) (task_pt_regs(task)->sp)
127
128#define cpu_relax() do { } while (0)
129
130extern const struct seq_operations cpuinfo_op;
131
132#endif /* ASM_C6X_PROCESSOR_H */
diff --git a/arch/c6x/include/asm/procinfo.h b/arch/c6x/include/asm/procinfo.h
new file mode 100644
index 000000000000..c139d1e71f87
--- /dev/null
+++ b/arch/c6x/include/asm/procinfo.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2010 Texas Instruments Incorporated
3 * Author: Mark Salter (msalter@redhat.com)
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASM_C6X_PROCINFO_H
11#define _ASM_C6X_PROCINFO_H
12
13#ifdef __KERNEL__
14
15struct proc_info_list {
16 unsigned int cpu_val;
17 unsigned int cpu_mask;
18 const char *arch_name;
19 const char *elf_name;
20 unsigned int elf_hwcap;
21};
22
23#else /* __KERNEL__ */
24#include <asm/elf.h>
25#warning "Please include asm/elf.h instead"
26#endif /* __KERNEL__ */
27
28#endif /* _ASM_C6X_PROCINFO_H */
diff --git a/arch/c6x/include/asm/prom.h b/arch/c6x/include/asm/prom.h
new file mode 100644
index 000000000000..b4ec95f07518
--- /dev/null
+++ b/arch/c6x/include/asm/prom.h
@@ -0,0 +1 @@
/* dummy prom.h; here to make linux/of.h's #includes happy */
diff --git a/arch/c6x/include/asm/ptrace.h b/arch/c6x/include/asm/ptrace.h
new file mode 100644
index 000000000000..21e8d7931fe7
--- /dev/null
+++ b/arch/c6x/include/asm/ptrace.h
@@ -0,0 +1,174 @@
1/*
2 * Copyright (C) 2004, 2006, 2009, 2010 Texas Instruments Incorporated
3 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
4 *
5 * Updated for 2.6.34: Mark Salter <msalter@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_PTRACE_H
12#define _ASM_C6X_PTRACE_H
13
14#define BKPT_OPCODE 0x56454314 /* illegal opcode */
15
16#ifdef _BIG_ENDIAN
17#define PT_LO(odd, even) odd
18#define PT_HI(odd, even) even
19#else
20#define PT_LO(odd, even) even
21#define PT_HI(odd, even) odd
22#endif
23
24#define PT_A4_ORG PT_LO(1, 0)
25#define PT_TSR PT_HI(1, 0)
26#define PT_ILC PT_LO(3, 2)
27#define PT_RILC PT_HI(3, 2)
28#define PT_CSR PT_LO(5, 4)
29#define PT_PC PT_HI(5, 4)
30#define PT_B16 PT_LO(7, 6)
31#define PT_B17 PT_HI(7, 6)
32#define PT_B18 PT_LO(9, 8)
33#define PT_B19 PT_HI(9, 8)
34#define PT_B20 PT_LO(11, 10)
35#define PT_B21 PT_HI(11, 10)
36#define PT_B22 PT_LO(13, 12)
37#define PT_B23 PT_HI(13, 12)
38#define PT_B24 PT_LO(15, 14)
39#define PT_B25 PT_HI(15, 14)
40#define PT_B26 PT_LO(17, 16)
41#define PT_B27 PT_HI(17, 16)
42#define PT_B28 PT_LO(19, 18)
43#define PT_B29 PT_HI(19, 18)
44#define PT_B30 PT_LO(21, 20)
45#define PT_B31 PT_HI(21, 20)
46#define PT_B0 PT_LO(23, 22)
47#define PT_B1 PT_HI(23, 22)
48#define PT_B2 PT_LO(25, 24)
49#define PT_B3 PT_HI(25, 24)
50#define PT_B4 PT_LO(27, 26)
51#define PT_B5 PT_HI(27, 26)
52#define PT_B6 PT_LO(29, 28)
53#define PT_B7 PT_HI(29, 28)
54#define PT_B8 PT_LO(31, 30)
55#define PT_B9 PT_HI(31, 30)
56#define PT_B10 PT_LO(33, 32)
57#define PT_B11 PT_HI(33, 32)
58#define PT_B12 PT_LO(35, 34)
59#define PT_B13 PT_HI(35, 34)
60#define PT_A16 PT_LO(37, 36)
61#define PT_A17 PT_HI(37, 36)
62#define PT_A18 PT_LO(39, 38)
63#define PT_A19 PT_HI(39, 38)
64#define PT_A20 PT_LO(41, 40)
65#define PT_A21 PT_HI(41, 40)
66#define PT_A22 PT_LO(43, 42)
67#define PT_A23 PT_HI(43, 42)
68#define PT_A24 PT_LO(45, 44)
69#define PT_A25 PT_HI(45, 44)
70#define PT_A26 PT_LO(47, 46)
71#define PT_A27 PT_HI(47, 46)
72#define PT_A28 PT_LO(49, 48)
73#define PT_A29 PT_HI(49, 48)
74#define PT_A30 PT_LO(51, 50)
75#define PT_A31 PT_HI(51, 50)
76#define PT_A0 PT_LO(53, 52)
77#define PT_A1 PT_HI(53, 52)
78#define PT_A2 PT_LO(55, 54)
79#define PT_A3 PT_HI(55, 54)
80#define PT_A4 PT_LO(57, 56)
81#define PT_A5 PT_HI(57, 56)
82#define PT_A6 PT_LO(59, 58)
83#define PT_A7 PT_HI(59, 58)
84#define PT_A8 PT_LO(61, 60)
85#define PT_A9 PT_HI(61, 60)
86#define PT_A10 PT_LO(63, 62)
87#define PT_A11 PT_HI(63, 62)
88#define PT_A12 PT_LO(65, 64)
89#define PT_A13 PT_HI(65, 64)
90#define PT_A14 PT_LO(67, 66)
91#define PT_A15 PT_HI(67, 66)
92#define PT_B14 PT_LO(69, 68)
93#define PT_B15 PT_HI(69, 68)
94
95#define NR_PTREGS 70
96
97#define PT_DP PT_B14 /* Data Segment Pointer (B14) */
98#define PT_SP PT_B15 /* Stack Pointer (B15) */
99
100#ifndef __ASSEMBLY__
101
102#ifdef _BIG_ENDIAN
103#define REG_PAIR(odd, even) unsigned long odd; unsigned long even
104#else
105#define REG_PAIR(odd, even) unsigned long even; unsigned long odd
106#endif
107
108/*
109 * this struct defines the way the registers are stored on the
110 * stack during a system call. fields defined with REG_PAIR
111 * are saved and restored using double-word memory operations
112 * which means the word ordering of the pair depends on endianess.
113 */
114struct pt_regs {
115 REG_PAIR(tsr, orig_a4);
116 REG_PAIR(rilc, ilc);
117 REG_PAIR(pc, csr);
118
119 REG_PAIR(b17, b16);
120 REG_PAIR(b19, b18);
121 REG_PAIR(b21, b20);
122 REG_PAIR(b23, b22);
123 REG_PAIR(b25, b24);
124 REG_PAIR(b27, b26);
125 REG_PAIR(b29, b28);
126 REG_PAIR(b31, b30);
127
128 REG_PAIR(b1, b0);
129 REG_PAIR(b3, b2);
130 REG_PAIR(b5, b4);
131 REG_PAIR(b7, b6);
132 REG_PAIR(b9, b8);
133 REG_PAIR(b11, b10);
134 REG_PAIR(b13, b12);
135
136 REG_PAIR(a17, a16);
137 REG_PAIR(a19, a18);
138 REG_PAIR(a21, a20);
139 REG_PAIR(a23, a22);
140 REG_PAIR(a25, a24);
141 REG_PAIR(a27, a26);
142 REG_PAIR(a29, a28);
143 REG_PAIR(a31, a30);
144
145 REG_PAIR(a1, a0);
146 REG_PAIR(a3, a2);
147 REG_PAIR(a5, a4);
148 REG_PAIR(a7, a6);
149 REG_PAIR(a9, a8);
150 REG_PAIR(a11, a10);
151 REG_PAIR(a13, a12);
152
153 REG_PAIR(a15, a14);
154 REG_PAIR(sp, dp);
155};
156
157#ifdef __KERNEL__
158
159#include <linux/linkage.h>
160
161#define user_mode(regs) ((((regs)->tsr) & 0x40) != 0)
162
163#define instruction_pointer(regs) ((regs)->pc)
164#define profile_pc(regs) instruction_pointer(regs)
165#define user_stack_pointer(regs) ((regs)->sp)
166
167extern void show_regs(struct pt_regs *);
168
169extern asmlinkage unsigned long syscall_trace_entry(struct pt_regs *regs);
170extern asmlinkage void syscall_trace_exit(struct pt_regs *regs);
171
172#endif /* __KERNEL__ */
173#endif /* __ASSEMBLY__ */
174#endif /* _ASM_C6X_PTRACE_H */
diff --git a/arch/c6x/include/asm/sections.h b/arch/c6x/include/asm/sections.h
new file mode 100644
index 000000000000..f703989d837a
--- /dev/null
+++ b/arch/c6x/include/asm/sections.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_C6X_SECTIONS_H
2#define _ASM_C6X_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6extern char _vectors_start[];
7extern char _vectors_end[];
8
9extern char _data_lma[];
10extern char _fdt_start[], _fdt_end[];
11
12#endif /* _ASM_C6X_SECTIONS_H */
diff --git a/arch/c6x/include/asm/setup.h b/arch/c6x/include/asm/setup.h
new file mode 100644
index 000000000000..1808f279f82e
--- /dev/null
+++ b/arch/c6x/include/asm/setup.h
@@ -0,0 +1,32 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2010 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_SETUP_H
12#define _ASM_C6X_SETUP_H
13
14#define COMMAND_LINE_SIZE 1024
15
16#ifndef __ASSEMBLY__
17extern char c6x_command_line[COMMAND_LINE_SIZE];
18
19extern int c6x_add_memory(phys_addr_t start, unsigned long size);
20
21extern unsigned long ram_start;
22extern unsigned long ram_end;
23
24extern int c6x_num_cores;
25extern unsigned int c6x_silicon_rev;
26extern unsigned int c6x_devstat;
27extern unsigned char c6x_fuse_mac[6];
28
29extern void machine_init(unsigned long dt_ptr);
30
31#endif /* !__ASSEMBLY__ */
32#endif /* _ASM_C6X_SETUP_H */
diff --git a/arch/c6x/include/asm/sigcontext.h b/arch/c6x/include/asm/sigcontext.h
new file mode 100644
index 000000000000..eb702f39cde7
--- /dev/null
+++ b/arch/c6x/include/asm/sigcontext.h
@@ -0,0 +1,80 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_SIGCONTEXT_H
12#define _ASM_C6X_SIGCONTEXT_H
13
14
15struct sigcontext {
16 unsigned long sc_mask; /* old sigmask */
17 unsigned long sc_sp; /* old user stack pointer */
18
19 unsigned long sc_a4;
20 unsigned long sc_b4;
21 unsigned long sc_a6;
22 unsigned long sc_b6;
23 unsigned long sc_a8;
24 unsigned long sc_b8;
25
26 unsigned long sc_a0;
27 unsigned long sc_a1;
28 unsigned long sc_a2;
29 unsigned long sc_a3;
30 unsigned long sc_a5;
31 unsigned long sc_a7;
32 unsigned long sc_a9;
33
34 unsigned long sc_b0;
35 unsigned long sc_b1;
36 unsigned long sc_b2;
37 unsigned long sc_b3;
38 unsigned long sc_b5;
39 unsigned long sc_b7;
40 unsigned long sc_b9;
41
42 unsigned long sc_a16;
43 unsigned long sc_a17;
44 unsigned long sc_a18;
45 unsigned long sc_a19;
46 unsigned long sc_a20;
47 unsigned long sc_a21;
48 unsigned long sc_a22;
49 unsigned long sc_a23;
50 unsigned long sc_a24;
51 unsigned long sc_a25;
52 unsigned long sc_a26;
53 unsigned long sc_a27;
54 unsigned long sc_a28;
55 unsigned long sc_a29;
56 unsigned long sc_a30;
57 unsigned long sc_a31;
58
59 unsigned long sc_b16;
60 unsigned long sc_b17;
61 unsigned long sc_b18;
62 unsigned long sc_b19;
63 unsigned long sc_b20;
64 unsigned long sc_b21;
65 unsigned long sc_b22;
66 unsigned long sc_b23;
67 unsigned long sc_b24;
68 unsigned long sc_b25;
69 unsigned long sc_b26;
70 unsigned long sc_b27;
71 unsigned long sc_b28;
72 unsigned long sc_b29;
73 unsigned long sc_b30;
74 unsigned long sc_b31;
75
76 unsigned long sc_csr;
77 unsigned long sc_pc;
78};
79
80#endif /* _ASM_C6X_SIGCONTEXT_H */
diff --git a/arch/c6x/include/asm/signal.h b/arch/c6x/include/asm/signal.h
new file mode 100644
index 000000000000..f1cd870596a3
--- /dev/null
+++ b/arch/c6x/include/asm/signal.h
@@ -0,0 +1,17 @@
1#ifndef _ASM_C6X_SIGNAL_H
2#define _ASM_C6X_SIGNAL_H
3
4#include <asm-generic/signal.h>
5
6#ifndef __ASSEMBLY__
7#include <linux/linkage.h>
8
9struct pt_regs;
10
11extern asmlinkage int do_rt_sigreturn(struct pt_regs *regs);
12extern asmlinkage void do_notify_resume(struct pt_regs *regs,
13 u32 thread_info_flags,
14 int syscall);
15#endif
16
17#endif /* _ASM_C6X_SIGNAL_H */
diff --git a/arch/c6x/include/asm/soc.h b/arch/c6x/include/asm/soc.h
new file mode 100644
index 000000000000..43f50159e59b
--- /dev/null
+++ b/arch/c6x/include/asm/soc.h
@@ -0,0 +1,35 @@
1/*
2 * Miscellaneous SoC-specific hooks.
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated
5 *
6 * Author: Mark Salter <msalter@redhat.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12#ifndef _ASM_C6X_SOC_H
13#define _ASM_C6X_SOC_H
14
15struct soc_ops {
16 /* Return active exception event or -1 if none */
17 int (*get_exception)(void);
18
19 /* Assert an event */
20 void (*assert_event)(unsigned int evt);
21};
22
23extern struct soc_ops soc_ops;
24
25extern int soc_get_exception(void);
26extern void soc_assert_event(unsigned int event);
27extern int soc_mac_addr(unsigned int index, u8 *addr);
28
29/*
30 * for mmio on SoC devices. regs are always same byte order as cpu.
31 */
32#define soc_readl(addr) __raw_readl(addr)
33#define soc_writel(b, addr) __raw_writel((b), (addr))
34
35#endif /* _ASM_C6X_SOC_H */
diff --git a/arch/c6x/include/asm/string.h b/arch/c6x/include/asm/string.h
new file mode 100644
index 000000000000..b21517c80a17
--- /dev/null
+++ b/arch/c6x/include/asm/string.h
@@ -0,0 +1,21 @@
1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2004, 2009, 2011 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_STRING_H
12#define _ASM_C6X_STRING_H
13
14#include <asm/page.h>
15#include <linux/linkage.h>
16
17asmlinkage extern void *memcpy(void *to, const void *from, size_t n);
18
19#define __HAVE_ARCH_MEMCPY
20
21#endif /* _ASM_C6X_STRING_H */
diff --git a/arch/c6x/include/asm/swab.h b/arch/c6x/include/asm/swab.h
new file mode 100644
index 000000000000..fd4bb0520e5e
--- /dev/null
+++ b/arch/c6x/include/asm/swab.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated
3 * Author: Mark Salter <msalter@redhat.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#ifndef _ASM_C6X_SWAB_H
10#define _ASM_C6X_SWAB_H
11
12static inline __attribute_const__ __u16 __c6x_swab16(__u16 val)
13{
14 asm("swap4 .l1 %0,%0\n" : "+a"(val));
15 return val;
16}
17
18static inline __attribute_const__ __u32 __c6x_swab32(__u32 val)
19{
20 asm("swap4 .l1 %0,%0\n"
21 "swap2 .l1 %0,%0\n"
22 : "+a"(val));
23 return val;
24}
25
26static inline __attribute_const__ __u64 __c6x_swab64(__u64 val)
27{
28 asm(" swap2 .s1 %p0,%P0\n"
29 "|| swap2 .l1 %P0,%p0\n"
30 " swap4 .l1 %p0,%p0\n"
31 " swap4 .l1 %P0,%P0\n"
32 : "+a"(val));
33 return val;
34}
35
36static inline __attribute_const__ __u32 __c6x_swahw32(__u32 val)
37{
38 asm("swap2 .l1 %0,%0\n" : "+a"(val));
39 return val;
40}
41
42static inline __attribute_const__ __u32 __c6x_swahb32(__u32 val)
43{
44 asm("swap4 .l1 %0,%0\n" : "+a"(val));
45 return val;
46}
47
48#define __arch_swab16 __c6x_swab16
49#define __arch_swab32 __c6x_swab32
50#define __arch_swab64 __c6x_swab64
51#define __arch_swahw32 __c6x_swahw32
52#define __arch_swahb32 __c6x_swahb32
53
54#endif /* _ASM_C6X_SWAB_H */
diff --git a/arch/c6x/include/asm/syscall.h b/arch/c6x/include/asm/syscall.h
new file mode 100644
index 000000000000..ae2be315ee9c
--- /dev/null
+++ b/arch/c6x/include/asm/syscall.h
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated
3 * Author: Mark Salter <msalter@redhat.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __ASM_C6X_SYSCALL_H
12#define __ASM_C6X_SYSCALL_H
13
14#include <linux/err.h>
15#include <linux/sched.h>
16
17static inline int syscall_get_nr(struct task_struct *task,
18 struct pt_regs *regs)
19{
20 return regs->b0;
21}
22
23static inline void syscall_rollback(struct task_struct *task,
24 struct pt_regs *regs)
25{
26 /* do nothing */
27}
28
29static inline long syscall_get_error(struct task_struct *task,
30 struct pt_regs *regs)
31{
32 return IS_ERR_VALUE(regs->a4) ? regs->a4 : 0;
33}
34
35static inline long syscall_get_return_value(struct task_struct *task,
36 struct pt_regs *regs)
37{
38 return regs->a4;
39}
40
41static inline void syscall_set_return_value(struct task_struct *task,
42 struct pt_regs *regs,
43 int error, long val)
44{
45 regs->a4 = error ?: val;
46}
47
48static inline void syscall_get_arguments(struct task_struct *task,
49 struct pt_regs *regs, unsigned int i,
50 unsigned int n, unsigned long *args)
51{
52 switch (i) {
53 case 0:
54 if (!n--)
55 break;
56 *args++ = regs->a4;
57 case 1:
58 if (!n--)
59 break;
60 *args++ = regs->b4;
61 case 2:
62 if (!n--)
63 break;
64 *args++ = regs->a6;
65 case 3:
66 if (!n--)
67 break;
68 *args++ = regs->b6;
69 case 4:
70 if (!n--)
71 break;