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authorPaulo Zanoni2013-04-08 13:48:07 -0500
committerGreg Kroah-Hartman2013-05-11 15:54:02 -0500
commit12622510457a776e4871e314c99ca1e279f8c399 (patch)
tree66b3744b4d6c90a56e290374a418141283cc6254
parentcbb83bb7bea7effffbd4097b3b355780e07f273d (diff)
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drm/i915: set CPT FDI RX polarity bits based on VBT
commit 3f704fa2778d3fe45e6529825a5c7a8bcbc686f4 upstream. Check the VBT to see if the machine has inverted FDI RX polarity on CPT. Based on this bit, set the appropriate bit on the TRANS_CHICKEN2 registers. This should fix some machines that were showing black screens on all outputs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60029 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c6
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h4
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c9
5 files changed, 16 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c3c179a784f..e78419f1f419 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -711,6 +711,7 @@ typedef struct drm_i915_private {
711 unsigned int int_crt_support:1; 711 unsigned int int_crt_support:1;
712 unsigned int lvds_use_ssc:1; 712 unsigned int lvds_use_ssc:1;
713 unsigned int display_clock_mode:1; 713 unsigned int display_clock_mode:1;
714 unsigned int fdi_rx_polarity_inverted:1;
714 int lvds_ssc_freq; 715 int lvds_ssc_freq;
715 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 716 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
716 unsigned int lvds_val; /* used for checking LVDS channel mode */ 717 unsigned int lvds_val; /* used for checking LVDS channel mode */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2bfd05a5da27..ce70f0ac1c73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3839,7 +3839,7 @@
3839#define _TRANSB_CHICKEN2 0xf1064 3839#define _TRANSB_CHICKEN2 0xf1064
3840#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3840#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3841#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 3841#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
3842 3842#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
3843 3843
3844#define SOUTH_CHICKEN1 0xc2000 3844#define SOUTH_CHICKEN1 0xc2000
3845#define FDIA_PHASE_SYNC_SHIFT_OVR 19 3845#define FDIA_PHASE_SYNC_SHIFT_OVR 19
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 55ffba1f5818..bd833918c492 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -351,12 +351,14 @@ parse_general_features(struct drm_i915_private *dev_priv,
351 dev_priv->lvds_ssc_freq = 351 dev_priv->lvds_ssc_freq =
352 intel_bios_ssc_frequency(dev, general->ssc_freq); 352 intel_bios_ssc_frequency(dev, general->ssc_freq);
353 dev_priv->display_clock_mode = general->display_clock_mode; 353 dev_priv->display_clock_mode = general->display_clock_mode;
354 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n", 354 dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
355 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
355 dev_priv->int_tv_support, 356 dev_priv->int_tv_support,
356 dev_priv->int_crt_support, 357 dev_priv->int_crt_support,
357 dev_priv->lvds_use_ssc, 358 dev_priv->lvds_use_ssc,
358 dev_priv->lvds_ssc_freq, 359 dev_priv->lvds_ssc_freq,
359 dev_priv->display_clock_mode); 360 dev_priv->display_clock_mode,
361 dev_priv->fdi_rx_polarity_inverted);
360 } 362 }
361} 363}
362 364
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 36e57f934373..e088d6f0956a 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -127,7 +127,9 @@ struct bdb_general_features {
127 /* bits 3 */ 127 /* bits 3 */
128 u8 disable_smooth_vision:1; 128 u8 disable_smooth_vision:1;
129 u8 single_dvi:1; 129 u8 single_dvi:1;
130 u8 rsvd9:6; /* finish byte */ 130 u8 rsvd9:1;
131 u8 fdi_rx_polarity_inverted:1;
132 u8 rsvd10:4; /* finish byte */
131 133
132 /* bits 4 */ 134 /* bits 4 */
133 u8 legacy_monitor_detect; 135 u8 legacy_monitor_detect;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dde0dedfc9c4..253bcf3bcc02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3560,6 +3560,7 @@ static void cpt_init_clock_gating(struct drm_device *dev)
3560{ 3560{
3561 struct drm_i915_private *dev_priv = dev->dev_private; 3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 int pipe; 3562 int pipe;
3563 uint32_t val;
3563 3564
3564 /* 3565 /*
3565 * On Ibex Peak and Cougar Point, we need to disable clock 3566 * On Ibex Peak and Cougar Point, we need to disable clock
@@ -3572,8 +3573,12 @@ static void cpt_init_clock_gating(struct drm_device *dev)
3572 /* The below fixes the weird display corruption, a few pixels shifted 3573 /* The below fixes the weird display corruption, a few pixels shifted
3573 * downward, on (only) LVDS of some HP laptops with IVY. 3574 * downward, on (only) LVDS of some HP laptops with IVY.
3574 */ 3575 */
3575 for_each_pipe(pipe) 3576 for_each_pipe(pipe) {
3576 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); 3577 val = TRANS_CHICKEN2_TIMING_OVERRIDE;
3578 if (dev_priv->fdi_rx_polarity_inverted)
3579 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3580 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3581 }
3577 /* WADP0ClockGatingDisable */ 3582 /* WADP0ClockGatingDisable */
3578 for_each_pipe(pipe) { 3583 for_each_pipe(pipe) {
3579 I915_WRITE(TRANS_CHICKEN1(pipe), 3584 I915_WRITE(TRANS_CHICKEN1(pipe),