drm/radeon: properly lock disp in mc_stop/resume for evergreen+

commit 968c01664ccbe0e46c19a1af662c4c266a904203 upstream.

Need to wait for the new addresses to take affect before
re-enabling the MC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2 files changed, 45 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4157c33516af..82d855f9a013 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1354,18 +1354,14 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
                                 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
                                         radeon_wait_for_vblank(rdev, i);
                                         tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
-                                        WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
                                         WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
-                                        WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
                                 }
                         } else {
                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
                                         radeon_wait_for_vblank(rdev, i);
                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
-                                        WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
-                                        WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
                                 }
                         }
                         /* wait for the next frame */
@@ -1392,6 +1388,22 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
         }
         /* wait for the MC to settle */
         udelay(100);
+
+        /* lock double buffered regs */
+        for (i = 0; i < rdev->num_crtc; i++) {
+                if (save->crtc_enabled[i]) {
+                        tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
+                        if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
+                                tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
+                                WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
+                        }
+                        tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+                        if (!(tmp & 1)) {
+                                tmp |= 1;
+                                WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+                        }
+                }
+        }
 }
 
 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1413,6 +1425,33 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 
+        /* unlock regs and wait for update */
+        for (i = 0; i < rdev->num_crtc; i++) {
+                if (save->crtc_enabled[i]) {
+                        tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
+                        if ((tmp & 0x3) != 0) {
+                                tmp &= ~0x3;
+                                WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+                        }
+                        tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
+                        if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
+                                tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
+                                WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
+                        }
+                        tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+                        if (tmp & 1) {
+                                tmp &= ~1;
+                                WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+                        }
+                        for (j = 0; j < rdev->usec_timeout; j++) {
+                                tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
+                                if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
+                                        break;
+                                udelay(1);
+                        }
+                }
+        }
+
         /* unblackout the MC */
         tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
         tmp &= ~BLACKOUT_MODE_MASK;
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index 034f4c22e5db..3e9773aea7fe 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -225,6 +225,8 @@
 #define EVERGREEN_CRTC_STATUS_POSITION                  0x6e90
 #define EVERGREEN_MASTER_UPDATE_MODE                    0x6ef8
 #define EVERGREEN_CRTC_UPDATE_LOCK                      0x6ed4
+#define EVERGREEN_MASTER_UPDATE_LOCK                    0x6ef4
+#define EVERGREEN_MASTER_UPDATE_MODE                    0x6ef8
 
 #define EVERGREEN_DC_GPIO_HPD_MASK                      0x64b0
 #define EVERGREEN_DC_GPIO_HPD_A                         0x64b4