drm/radeon/dce6: add missing display reg for tiling setup

commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream.

A new tiling config register for the display blocks was
added on DCE6.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=62889
https://bugs.freedesktop.org/show_bug.cgi?id=57919

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

4 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index b64e55dac757..ccc3987080bd 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -619,6 +619,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
         WREG32(GB_ADDR_CONFIG, gb_addr_config);
         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+        if (ASIC_IS_DCE6(rdev))
+                WREG32(DMIF_ADDR_CALC, gb_addr_config);
         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
         WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
         WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 48e5022ee921..e045f8cbcd4f 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -45,6 +45,10 @@
 #define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
 
 #define DMIF_ADDR_CONFIG                                0xBD4
+
+/* DCE6 only */
+#define DMIF_ADDR_CALC                                  0xC00
+
 #define SRBM_GFX_CNTL                                   0x0E44
 #define         RINGID(x)                                       (((x) & 0x3) << 0)
 #define         VMID(x)                                         (((x) & 0x7) << 0)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index dd007214dfff..47550ecfba24 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1659,6 +1659,7 @@ static void si_gpu_init(struct radeon_device *rdev)
 
         WREG32(GB_ADDR_CONFIG, gb_addr_config);
         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+        WREG32(DMIF_ADDR_CALC, gb_addr_config);
         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
         WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
         WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index c056aae814f0..e9a01f025dcd 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -60,6 +60,8 @@
 
 #define DMIF_ADDR_CONFIG                                0xBD4
 
+#define DMIF_ADDR_CALC                                  0xC00
+
 #define SRBM_STATUS                                     0xE50
 
 #define SRBM_SOFT_RESET                                 0x0E60