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authorAlex Deucher2013-04-05 09:28:08 -0500
committerGreg Kroah-Hartman2013-05-11 15:54:04 -0500
commit6e08af0fb303c97a5bd7be70922110c0a983a1d1 (patch)
treef444589eaede8d71e47b7031a5eadc023bab7c5c
parent01f2c8f8ece71325f2ea56b6397e0ed590fb505b (diff)
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drm/radeon/dce6: add missing display reg for tiling setup
commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream. A new tiling config register for the display blocks was added on DCE6. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=62889 https://bugs.freedesktop.org/show_bug.cgi?id=57919 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/gpu/drm/radeon/ni.c2
-rw-r--r--drivers/gpu/drm/radeon/nid.h4
-rw-r--r--drivers/gpu/drm/radeon/si.c1
-rw-r--r--drivers/gpu/drm/radeon/sid.h2
4 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index b64e55dac757..ccc3987080bd 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -619,6 +619,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
619 619
620 WREG32(GB_ADDR_CONFIG, gb_addr_config); 620 WREG32(GB_ADDR_CONFIG, gb_addr_config);
621 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 621 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
622 if (ASIC_IS_DCE6(rdev))
623 WREG32(DMIF_ADDR_CALC, gb_addr_config);
622 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 624 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
623 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 625 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
624 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 626 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 48e5022ee921..e045f8cbcd4f 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -45,6 +45,10 @@
45#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 45#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
46 46
47#define DMIF_ADDR_CONFIG 0xBD4 47#define DMIF_ADDR_CONFIG 0xBD4
48
49/* DCE6 only */
50#define DMIF_ADDR_CALC 0xC00
51
48#define SRBM_GFX_CNTL 0x0E44 52#define SRBM_GFX_CNTL 0x0E44
49#define RINGID(x) (((x) & 0x3) << 0) 53#define RINGID(x) (((x) & 0x3) << 0)
50#define VMID(x) (((x) & 0x7) << 0) 54#define VMID(x) (((x) & 0x7) << 0)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index dd007214dfff..47550ecfba24 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1659,6 +1659,7 @@ static void si_gpu_init(struct radeon_device *rdev)
1659 1659
1660 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1660 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1661 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1661 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1662 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1662 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1663 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1663 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1664 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1664 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1665 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index c056aae814f0..e9a01f025dcd 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -60,6 +60,8 @@
60 60
61#define DMIF_ADDR_CONFIG 0xBD4 61#define DMIF_ADDR_CONFIG 0xBD4
62 62
63#define DMIF_ADDR_CALC 0xC00
64
63#define SRBM_STATUS 0xE50 65#define SRBM_STATUS 0xE50
64 66
65#define SRBM_SOFT_RESET 0x0E60 67#define SRBM_SOFT_RESET 0x0E60