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authorAlex Deucher2013-04-17 08:35:39 -0500
committerGreg Kroah-Hartman2013-05-11 15:54:08 -0500
commit81f9eaffece244b74f1d0a25218b6d2ab5809638 (patch)
treeff9e1bab80375a122b3a30c5ba2761186d5351ad
parent4a0efa7ea15f619003b9ac58f9c2313bd98282dd (diff)
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drm/radeon: disable the crtcs in mc_stop (r5xx-r7xx) (v2)
commit e884fc640ccbdb6f94b9bdb57cfb8464b6688f4c upstream. Just disabling the mem requests should be enough, but that doesn't seem to work correctly on efi systems. v2: blank displays first, then disable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/rv515.c11
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 6ada4e4e7301..8ec2376d47c1 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -359,6 +359,7 @@
359 359
360#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0 360#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
361#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 361#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
362#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8
362 363
363/* master controls */ 364/* master controls */
364#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 365#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 6a1e5dd5b5ee..ffcba730c57c 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
305 radeon_wait_for_vblank(rdev, i); 305 radeon_wait_for_vblank(rdev, i);
306 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
306 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 307 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
307 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 308 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
309 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
308 } 310 }
309 /* wait for the next frame */ 311 /* wait for the next frame */
310 frame_count = radeon_get_vblank_counter(rdev, i); 312 frame_count = radeon_get_vblank_counter(rdev, i);
@@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
313 break; 315 break;
314 udelay(1); 316 udelay(1);
315 } 317 }
318
319 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
320 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
322 tmp &= ~AVIVO_CRTC_EN;
323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
325 save->crtc_enabled[i] = false;
326 /* ***** */
316 } else { 327 } else {
317 save->crtc_enabled[i] = false; 328 save->crtc_enabled[i] = false;
318 } 329 }