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authorAlex Deucher2013-04-18 08:36:42 -0500
committerGreg Kroah-Hartman2013-05-11 15:54:06 -0500
commit8cf84ffff78f75ef364853d29e671402a4d1efae (patch)
treea6a59d555f053e3bd4eb74ac0ec74bacf191b9f8
parent1b441ba2cf1d50f57cb68d26d3303cb695df0f66 (diff)
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drm/radeon: fix hdmi mode enable on RS600/RS690/RS740
commit dcb852905772416e322536ced5cb3c796d176af5 upstream. These chips were previously skipped since they are pre-R600. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 95970ec47c45..d89a1f83309f 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -489,7 +489,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
489 offset = dig->afmt->offset; 489 offset = dig->afmt->offset;
490 490
491 /* Older chipsets require setting HDMI and routing manually */ 491 /* Older chipsets require setting HDMI and routing manually */
492 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 492 if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
493 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 493 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
494 switch (radeon_encoder->encoder_id) { 494 switch (radeon_encoder->encoder_id) {
495 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 495 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -557,7 +557,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
557 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 557 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
558 558
559 /* Older chipsets not handled by AtomBIOS */ 559 /* Older chipsets not handled by AtomBIOS */
560 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 560 if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
561 switch (radeon_encoder->encoder_id) { 561 switch (radeon_encoder->encoder_id) {
562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
563 WREG32_P(AVIVO_TMDSA_CNTL, 0, 563 WREG32_P(AVIVO_TMDSA_CNTL, 0,