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authorAlex Deucher2013-04-10 08:47:05 -0500
committerGreg Kroah-Hartman2013-05-11 15:54:05 -0500
commitb38b76076dc96dc76b85e57e116867ee4dc62432 (patch)
treeb6148f8b3d1908d5893ba7f8cf6e508dc2e71aaa
parent609326a6060f71626cab7b4bc02b419e42c11f8d (diff)
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drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx
commit 2f86e2ede39a98650c2d465857405ef1c51372b1 upstream. Need to wait for the new addresses to take affect before re-enabling the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/rv515.c43
2 files changed, 44 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index ec576aaafb73..6ada4e4e7301 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -357,6 +357,7 @@
357#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4 357#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
358#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 358#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
359 359
360#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
360#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 361#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
361 362
362/* master controls */ 363/* master controls */
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 5e1ba16c7a77..6a1e5dd5b5ee 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -338,6 +338,22 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
338 } 338 }
339 /* wait for the MC to settle */ 339 /* wait for the MC to settle */
340 udelay(100); 340 udelay(100);
341
342 /* lock double buffered regs */
343 for (i = 0; i < rdev->num_crtc; i++) {
344 if (save->crtc_enabled[i]) {
345 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
346 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
347 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
348 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
349 }
350 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
351 if (!(tmp & 1)) {
352 tmp |= 1;
353 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
354 }
355 }
356 }
341} 357}
342 358
343void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 359void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -367,6 +383,33 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
367 } 383 }
368 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 384 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
369 385
386 /* unlock regs and wait for update */
387 for (i = 0; i < rdev->num_crtc; i++) {
388 if (save->crtc_enabled[i]) {
389 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
390 if ((tmp & 0x3) != 0) {
391 tmp &= ~0x3;
392 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
393 }
394 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
395 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
396 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
397 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
398 }
399 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
400 if (tmp & 1) {
401 tmp &= ~1;
402 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
403 }
404 for (j = 0; j < rdev->usec_timeout; j++) {
405 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
406 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
407 break;
408 udelay(1);
409 }
410 }
411 }
412
370 if (rdev->family >= CHIP_R600) { 413 if (rdev->family >= CHIP_R600) {
371 /* unblackout the MC */ 414 /* unblackout the MC */
372 if (rdev->family >= CHIP_RV770) 415 if (rdev->family >= CHIP_RV770)