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authorPraneeth Bajjuri2017-08-28 18:03:19 -0500
committerPraneeth Bajjuri2017-08-28 18:03:19 -0500
commitdda8acaf6f2d9bddce62c305edf6b3071f04c136 (patch)
tree612f8b7b18ff3a84184ddc0ce456b9b0287cace6 /arch
parentb22bbe0c5fa4fd5eb4609108a750b28a744a643e (diff)
parenteabbcea7629d5f2ec91568f7bd104536614107db (diff)
downloadkernel-omap-6AM.1.3-rvc-video.tar.gz
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Merge branch 'p-ti-lsk-android-linux-4.4.y' of git://git.omapzoom.org/kernel/omap into 6AM.1.3-rvc-video6AM.1.3-rvc-video
* 'p-ti-lsk-android-linux-4.4.y' of git://git.omapzoom.org/kernel/omap: (2048 commits) ARM: dts: dra7: Remove deprecated PCI compatible string ARM: dts: dra76-evm: Enable x2 PCIe lanes ARM: dts: DRA72x: Use PCIe compatible specific to dra72 ARM: dts: DRA74x: Use PCIe compatible specific to dra74 ARM: dts: dra7: Add properties to enable PCIe x2 lane mode PCI: dwc: pci-dra7xx: Enable x2 mode support PCI: dwc: dra7xx: Add support for SoC specific compatible strings dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 dt-bindings: PCI: dra7xx: Add SoC specific compatible strings ARM: dts: dra7-evm: Move pcie RC node to common file ARM: dts: dra76-evm: add higher speed MMC/SD modes Linux 4.4.84 usb: qmi_wwan: add D-Link DWM-222 device ID usb: optimize acpi companion search for usb port devices perf/x86: Fix LBR related crashes on Intel Atom pids: make task_tgid_nr_ns() safe Sanitize 'move_pages()' permission checks irqchip/atmel-aic: Fix unbalanced refcount in aic_common_rtc_irq_fixup() irqchip/atmel-aic: Fix unbalanced of_node_put() in aic_common_irq_fixup() x86/asm/64: Clear AC on NMI entries ... Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Conflicts: arch/arm/boot/dts/Makefile drivers/gpu/drm/omapdrm/dss/dispc.c
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/kernel/osf_sys.c6
-rw-r--r--arch/arc/include/asm/delay.h4
-rw-r--r--arch/arc/include/asm/entry-arcv2.h2
-rw-r--r--arch/arc/include/asm/ptrace.h2
-rw-r--r--arch/arc/kernel/unaligned.c3
-rw-r--r--arch/arc/mm/mmap.c2
-rw-r--r--arch/arm/boot/dts/Makefile7
-rw-r--r--arch/arm/boot/dts/armada-388-gp.dts4
-rw-r--r--arch/arm/boot/dts/at91-sama5d2_xplained.dts2
-rw-r--r--arch/arm/boot/dts/at91-sama5d3_xplained.dts5
-rw-r--r--arch/arm/boot/dts/at91-sama5d4_xplained.dts2
-rw-r--r--arch/arm/boot/dts/bcm5301x.dtsi4
-rw-r--r--arch/arm/boot/dts/dra7-evm-common.dtsi393
-rw-r--r--arch/arm/boot/dts/dra7-evm-fpd-auo-g101evn01.0.dts37
-rw-r--r--arch/arm/boot/dts/dra7-evm-fpd-lg.dts38
-rw-r--r--arch/arm/boot/dts/dra7-evm-lcd-lg.dts8
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts441
-rw-r--r--arch/arm/boot/dts/dra7.dtsi7
-rw-r--r--arch/arm/boot/dts/dra72-evm-common.dtsi27
-rw-r--r--arch/arm/boot/dts/dra72-evm-fpd-lg.dts39
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts34
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi12
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi12
-rw-r--r--arch/arm/boot/dts/dra76-evm-fpd-auo-g101evn01.0.dts67
-rw-r--r--arch/arm/boot/dts/dra76-evm.dts498
-rw-r--r--arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi435
-rw-r--r--arch/arm/boot/dts/dra76x.dtsi81
-rw-r--r--arch/arm/boot/dts/dra7x-evm-fpd-auo-g101evn01.0.dtsi107
-rw-r--r--arch/arm/boot/dts/dra7x-evm-fpd-lg.dtsi59
-rw-r--r--arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi3
-rw-r--r--arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi1
-rw-r--r--arch/arm/boot/dts/dra7xx-jamr3.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi1
-rw-r--r--arch/arm/boot/dts/sama5d2.dtsi35
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts1
-rw-r--r--arch/arm/configs/s3c2410_defconfig6
-rw-r--r--arch/arm/crypto/aes-ce-glue.c4
-rw-r--r--arch/arm/include/asm/elf.h8
-rw-r--r--arch/arm/include/asm/ftrace.h18
-rw-r--r--arch/arm/include/asm/kvm_mmu.h9
-rw-r--r--arch/arm/kernel/Makefile1
-rw-r--r--arch/arm/kernel/pj4-cp0.c4
-rw-r--r--arch/arm/kernel/ptrace.c2
-rw-r--r--arch/arm/kernel/vdso.c13
-rw-r--r--arch/arm/kvm/init.S5
-rw-r--r--arch/arm/kvm/mmu.c32
-rw-r--r--arch/arm/kvm/psci.c8
-rw-r--r--arch/arm/lib/getuser.S2
-rw-r--r--arch/arm/mach-at91/pm.c18
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/id.c14
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S3
-rw-r--r--arch/arm/mach-omap2/omap-smp.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c70
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c33
-rw-r--r--arch/arm/mach-omap2/soc.h6
-rw-r--r--arch/arm/mach-omap2/timer.c6
-rw-r--r--arch/arm/mm/fault.c4
-rw-r--r--arch/arm/mm/fault.h4
-rw-r--r--arch/arm/mm/mmap.c4
-rw-r--r--arch/arm/mm/mmu.c8
-rw-r--r--arch/arm/vdso/Makefile2
-rw-r--r--arch/arm64/Kconfig56
-rw-r--r--arch/arm64/Makefile16
-rw-r--r--arch/arm64/boot/dts/arm/juno-r1.dts28
-rw-r--r--arch/arm64/boot/dts/arm/juno-sched-energy.dtsi147
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts36
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts2
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi6
-rw-r--r--arch/arm64/configs/defconfig2
-rw-r--r--arch/arm64/crypto/Kconfig5
-rw-r--r--arch/arm64/crypto/Makefile3
-rw-r--r--arch/arm64/crypto/aes-glue.c4
-rw-r--r--arch/arm64/crypto/aes-modes.S88
-rw-r--r--arch/arm64/crypto/poly-hash-ce-core.S163
-rw-r--r--arch/arm64/crypto/poly-hash-ce-glue.c166
-rw-r--r--arch/arm64/include/asm/acpi.h6
-rw-r--r--arch/arm64/include/asm/alternative.h70
-rw-r--r--arch/arm64/include/asm/asm-uaccess.h13
-rw-r--r--arch/arm64/include/asm/assembler.h17
-rw-r--r--arch/arm64/include/asm/barrier.h21
-rw-r--r--arch/arm64/include/asm/cacheflush.h1
-rw-r--r--arch/arm64/include/asm/cmpxchg.h2
-rw-r--r--arch/arm64/include/asm/elf.h12
-rw-r--r--arch/arm64/include/asm/futex.h3
-rw-r--r--arch/arm64/include/asm/hardirq.h2
-rw-r--r--arch/arm64/include/asm/hw_breakpoint.h6
-rw-r--r--arch/arm64/include/asm/kexec.h98
-rw-r--r--arch/arm64/include/asm/kvm_mmu.h3
-rw-r--r--arch/arm64/include/asm/mmu.h2
-rw-r--r--arch/arm64/include/asm/mmu_context.h6
-rw-r--r--arch/arm64/include/asm/page.h12
-rw-r--r--arch/arm64/include/asm/ptrace.h2
-rw-r--r--arch/arm64/include/asm/smp.h52
-rw-r--r--arch/arm64/include/asm/spinlock.h7
-rw-r--r--arch/arm64/include/asm/thread_info.h2
-rw-r--r--arch/arm64/include/asm/uaccess.h119
-rw-r--r--arch/arm64/include/asm/vdso_datapage.h8
-rw-r--r--arch/arm64/include/asm/virt.h5
-rw-r--r--arch/arm64/kernel/Makefile8
-rw-r--r--arch/arm64/kernel/armv8_deprecated.c6
-rw-r--r--arch/arm64/kernel/asm-offsets.c14
-rw-r--r--arch/arm64/kernel/cpu-reset.S54
-rw-r--r--arch/arm64/kernel/cpu-reset.h34
-rw-r--r--arch/arm64/kernel/cpufeature.c36
-rw-r--r--arch/arm64/kernel/crash_dump.c71
-rw-r--r--arch/arm64/kernel/entry.S24
-rw-r--r--arch/arm64/kernel/head.S34
-rw-r--r--arch/arm64/kernel/hibernate.c92
-rw-r--r--arch/arm64/kernel/hw_breakpoint.c154
-rw-r--r--arch/arm64/kernel/hyp-stub.S10
-rw-r--r--arch/arm64/kernel/machine_kexec.c364
-rw-r--r--arch/arm64/kernel/ptrace.c7
-rw-r--r--arch/arm64/kernel/relocate_kernel.S130
-rw-r--r--arch/arm64/kernel/setup.c7
-rw-r--r--arch/arm64/kernel/smp.c153
-rw-r--r--arch/arm64/kernel/stacktrace.c5
-rw-r--r--arch/arm64/kernel/traps.c10
-rw-r--r--arch/arm64/kernel/vdso.c12
-rw-r--r--arch/arm64/kernel/vdso/Makefile7
-rw-r--r--arch/arm64/kernel/vdso/gettimeofday.S331
-rw-r--r--arch/arm64/kvm/hyp/Makefile4
-rw-r--r--arch/arm64/kvm/sys_regs.c6
-rw-r--r--arch/arm64/lib/clear_user.S3
-rw-r--r--arch/arm64/lib/copy_from_user.S3
-rw-r--r--arch/arm64/lib/copy_in_user.S3
-rw-r--r--arch/arm64/lib/copy_to_user.S3
-rw-r--r--arch/arm64/mm/cache.S6
-rw-r--r--arch/arm64/mm/fault.c17
-rw-r--r--arch/arm64/mm/hugetlbpage.c22
-rw-r--r--arch/arm64/mm/init.c181
-rw-r--r--arch/arm64/mm/mmu.c140
-rw-r--r--arch/arm64/mm/pageattr.c13
-rw-r--r--arch/arm64/mm/proc.S9
-rw-r--r--arch/arm64/net/bpf_jit_comp.c8
-rw-r--r--arch/arm64/xen/hypercall.S8
-rw-r--r--arch/c6x/kernel/ptrace.c41
-rw-r--r--arch/frv/mm/elf-fdpic.c2
-rw-r--r--arch/h8300/kernel/ptrace.c8
-rw-r--r--arch/ia64/Makefile4
-rw-r--r--arch/metag/include/asm/uaccess.h64
-rw-r--r--arch/metag/kernel/ptrace.c19
-rw-r--r--arch/metag/lib/usercopy.c312
-rw-r--r--arch/mips/Kconfig3
-rw-r--r--arch/mips/ath79/common.c16
-rw-r--r--arch/mips/bcm47xx/buttons.c10
-rw-r--r--arch/mips/cavium-octeon/octeon-memcpy.S20
-rw-r--r--arch/mips/configs/ip22_defconfig4
-rw-r--r--arch/mips/configs/ip27_defconfig3
-rw-r--r--arch/mips/configs/lemote2f_defconfig2
-rw-r--r--arch/mips/configs/malta_defconfig4
-rw-r--r--arch/mips/configs/malta_kvm_defconfig4
-rw-r--r--arch/mips/configs/malta_kvm_guest_defconfig4
-rw-r--r--arch/mips/configs/maltaup_xpa_defconfig4
-rw-r--r--arch/mips/configs/nlm_xlp_defconfig2
-rw-r--r--arch/mips/configs/nlm_xlr_defconfig2
-rw-r--r--arch/mips/dec/int-handler.S40
-rw-r--r--arch/mips/include/asm/branch.h5
-rw-r--r--arch/mips/include/asm/checksum.h2
-rw-r--r--arch/mips/include/asm/irq.h12
-rw-r--r--arch/mips/include/asm/spinlock.h8
-rw-r--r--arch/mips/include/asm/stackframe.h7
-rw-r--r--arch/mips/kernel/asm-offsets.c1
-rw-r--r--arch/mips/kernel/branch.c42
-rw-r--r--arch/mips/kernel/crash.c16
-rw-r--r--arch/mips/kernel/elf.c2
-rw-r--r--arch/mips/kernel/entry.S3
-rw-r--r--arch/mips/kernel/genex.S81
-rw-r--r--arch/mips/kernel/irq.c11
-rw-r--r--arch/mips/kernel/kgdb.c48
-rw-r--r--arch/mips/kernel/mips-r2-to-r6-emul.c12
-rw-r--r--arch/mips/kernel/pm-cps.c9
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/process.c166
-rw-r--r--arch/mips/kernel/ptrace.c5
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/syscall.c15
-rw-r--r--arch/mips/kernel/traps.c2
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c10
-rw-r--r--arch/mips/math-emu/cp1emu.c38
-rw-r--r--arch/mips/mm/mmap.c2
-rw-r--r--arch/mips/mm/sc-ip22.c54
-rw-r--r--arch/mips/mm/tlbex.c25
-rw-r--r--arch/mips/netlogic/common/reset.S11
-rw-r--r--arch/mips/netlogic/common/smpboot.S4
-rw-r--r--arch/mips/ralink/mt7620.c84
-rw-r--r--arch/mips/ralink/prom.c9
-rw-r--r--arch/mips/ralink/rt288x.c12
-rw-r--r--arch/mips/ralink/rt305x.c11
-rw-r--r--arch/mips/ralink/rt3883.c14
-rw-r--r--arch/mips/sgi-ip22/Platform2
-rw-r--r--arch/nios2/kernel/prom.c7
-rw-r--r--arch/nios2/kernel/setup.c3
-rw-r--r--arch/openrisc/kernel/vmlinux.lds.S2
-rw-r--r--arch/parisc/include/asm/bitops.h8
-rw-r--r--arch/parisc/include/asm/dma-mapping.h11
-rw-r--r--arch/parisc/include/asm/mmu_context.h15
-rw-r--r--arch/parisc/include/uapi/asm/bitsperlong.h2
-rw-r--r--arch/parisc/include/uapi/asm/swab.h5
-rw-r--r--arch/parisc/kernel/sys_parisc.c15
-rw-r--r--arch/parisc/kernel/syscall_table.S2
-rw-r--r--arch/parisc/mm/fault.c2
-rw-r--r--arch/powerpc/boot/zImage.lds.S1
-rw-r--r--arch/powerpc/include/asm/atomic.h4
-rw-r--r--arch/powerpc/include/asm/elf.h13
-rw-r--r--arch/powerpc/include/asm/reg.h2
-rw-r--r--arch/powerpc/kernel/align.c27
-rw-r--r--arch/powerpc/kernel/eeh.c10
-rw-r--r--arch/powerpc/kernel/eeh_driver.c21
-rw-r--r--arch/powerpc/kernel/entry_64.S6
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S12
-rw-r--r--arch/powerpc/kernel/hw_breakpoint.c4
-rw-r--r--arch/powerpc/kernel/kprobes.c11
-rw-r--r--arch/powerpc/kernel/mce.c2
-rw-r--r--arch/powerpc/kernel/prom_init.c3
-rw-r--r--arch/powerpc/kernel/setup_64.c9
-rw-r--r--arch/powerpc/kernel/traps.c4
-rw-r--r--arch/powerpc/kvm/book3s_hv.c60
-rw-r--r--arch/powerpc/kvm/book3s_hv_rmhandlers.S41
-rw-r--r--arch/powerpc/kvm/emulate.c1
-rw-r--r--arch/powerpc/lib/sstep.c39
-rw-r--r--arch/powerpc/mm/hash_native_64.c7
-rw-r--r--arch/powerpc/mm/slb_low.S10
-rw-r--r--arch/powerpc/mm/slice.c2
-rw-r--r--arch/powerpc/platforms/powernv/opal-wrappers.S2
-rw-r--r--arch/powerpc/platforms/pseries/dlpar.c1
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-memory.c2
-rw-r--r--arch/powerpc/platforms/pseries/reconfig.c1
-rw-r--r--arch/s390/Kconfig3
-rw-r--r--arch/s390/boot/compressed/misc.c35
-rw-r--r--arch/s390/include/asm/ctl_reg.h4
-rw-r--r--arch/s390/include/asm/elf.h15
-rw-r--r--arch/s390/include/asm/pgtable.h2
-rw-r--r--arch/s390/include/asm/processor.h3
-rw-r--r--arch/s390/include/asm/syscall.h6
-rw-r--r--arch/s390/include/asm/uaccess.h2
-rw-r--r--arch/s390/kernel/crash_dump.c33
-rw-r--r--arch/s390/kernel/entry.S40
-rw-r--r--arch/s390/kernel/ptrace.c8
-rw-r--r--arch/s390/kernel/setup.c8
-rw-r--r--arch/s390/kvm/kvm-s390.c3
-rw-r--r--arch/s390/mm/init.c10
-rw-r--r--arch/s390/mm/mmap.c4
-rw-r--r--arch/s390/mm/pgtable.c19
-rw-r--r--arch/s390/mm/vmem.c2
-rw-r--r--arch/s390/net/bpf_jit_comp.c3
-rw-r--r--arch/s390/pci/pci_dma.c16
-rw-r--r--arch/sh/mm/mmap.c4
-rw-r--r--arch/sparc/Kconfig4
-rw-r--r--arch/sparc/include/asm/mmu_64.h2
-rw-r--r--arch/sparc/include/asm/mmu_context_64.h46
-rw-r--r--arch/sparc/include/asm/pgtable_32.h4
-rw-r--r--arch/sparc/include/asm/pgtable_64.h15
-rw-r--r--arch/sparc/include/asm/pil.h1
-rw-r--r--arch/sparc/include/asm/setup.h2
-rw-r--r--arch/sparc/include/asm/trap_block.h1
-rw-r--r--arch/sparc/include/asm/vio.h1
-rw-r--r--arch/sparc/kernel/irq_64.c17
-rw-r--r--arch/sparc/kernel/kernel.h1
-rw-r--r--arch/sparc/kernel/ptrace_64.c2
-rw-r--r--arch/sparc/kernel/smp_64.c216
-rw-r--r--arch/sparc/kernel/sun4v_ivec.S15
-rw-r--r--arch/sparc/kernel/sys_sparc_64.c4
-rw-r--r--arch/sparc/kernel/traps_64.c5
-rw-r--r--arch/sparc/kernel/tsb.S23
-rw-r--r--arch/sparc/kernel/ttable_64.S2
-rw-r--r--arch/sparc/kernel/vio.c68
-rw-r--r--arch/sparc/mm/hugetlbpage.c2
-rw-r--r--arch/sparc/mm/init_32.c2
-rw-r--r--arch/sparc/mm/init_64.c88
-rw-r--r--arch/sparc/mm/tsb.c7
-rw-r--r--arch/sparc/mm/ultra.S5
-rw-r--r--arch/sparc/power/hibernate.c3
-rw-r--r--arch/tile/kernel/ptrace.c2
-rw-r--r--arch/tile/mm/hugetlbpage.c2
-rw-r--r--arch/x86/boot/boot.h2
-rw-r--r--arch/x86/boot/string.c1
-rw-r--r--arch/x86/boot/string.h9
-rw-r--r--arch/x86/crypto/ghash-clmulni-intel_glue.c26
-rw-r--r--arch/x86/crypto/sha1_avx2_x86_64_asm.S67
-rw-r--r--arch/x86/entry/entry_64.S2
-rw-r--r--arch/x86/entry/vdso/Makefile4
-rw-r--r--arch/x86/entry/vdso/vdso32-setup.c11
-rw-r--r--arch/x86/include/asm/elf.h15
-rw-r--r--arch/x86/include/asm/kvm_emulate.h4
-rw-r--r--arch/x86/include/asm/msr-index.h2
-rw-r--r--arch/x86/include/asm/pat.h1
-rw-r--r--arch/x86/include/asm/pmem.h45
-rw-r--r--arch/x86/include/asm/xen/hypercall.h3
-rw-r--r--arch/x86/kernel/acpi/boot.c8
-rw-r--r--arch/x86/kernel/apic/io_apic.c4
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd.c5
-rw-r--r--arch/x86/kernel/cpu/mshyperv.c24
-rw-r--r--arch/x86/kernel/cpu/perf_event.c4
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_lbr.c11
-rw-r--r--arch/x86/kernel/fpu/init.c1
-rw-r--r--arch/x86/kernel/ftrace.c12
-rw-r--r--arch/x86/kernel/head64.c1
-rw-r--r--arch/x86/kernel/hpet.c1
-rw-r--r--arch/x86/kernel/kprobes/common.h2
-rw-r--r--arch/x86/kernel/kprobes/core.c6
-rw-r--r--arch/x86/kernel/kprobes/opt.c2
-rw-r--r--arch/x86/kernel/kvm.c6
-rw-r--r--arch/x86/kernel/pci-calgary_64.c2
-rw-r--r--arch/x86/kernel/setup.c7
-rw-r--r--arch/x86/kernel/sys_x86_64.c4
-rw-r--r--arch/x86/kvm/cpuid.c39
-rw-r--r--arch/x86/kvm/cpuid.h9
-rw-r--r--arch/x86/kvm/emulate.c16
-rw-r--r--arch/x86/kvm/mmu.c7
-rw-r--r--arch/x86/kvm/mmu.h1
-rw-r--r--arch/x86/kvm/pmu_intel.c2
-rw-r--r--arch/x86/kvm/vmx.c108
-rw-r--r--arch/x86/kvm/x86.c69
-rw-r--r--arch/x86/lib/copy_user_64.S7
-rw-r--r--arch/x86/mm/hugetlbpage.c2
-rw-r--r--arch/x86/mm/init.c41
-rw-r--r--arch/x86/mm/kasan_init_64.c1
-rw-r--r--arch/x86/mm/mpx.c12
-rw-r--r--arch/x86/mm/numa_32.c1
-rw-r--r--arch/x86/mm/pat.c28
-rw-r--r--arch/x86/mm/tlb.c4
-rw-r--r--arch/x86/pci/xen.c23
-rw-r--r--arch/x86/platform/goldfish/goldfish.c14
-rw-r--r--arch/x86/platform/intel-mid/device_libs/platform_wdt.c2
-rw-r--r--arch/x86/tools/relocs.c3
-rw-r--r--arch/x86/um/ptrace_64.c2
-rw-r--r--arch/x86/xen/mmu.c7
-rw-r--r--arch/x86/xen/setup.c6
-rw-r--r--arch/x86/xen/spinlock.c6
-rw-r--r--arch/x86/xen/time.c6
-rw-r--r--arch/xtensa/include/asm/irq.h3
-rw-r--r--arch/xtensa/kernel/irq.c5
-rw-r--r--arch/xtensa/kernel/setup.c4
-rw-r--r--arch/xtensa/kernel/syscall.c2
-rw-r--r--arch/xtensa/platforms/xtfpga/include/platform/hardware.h6
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c10
342 files changed, 6762 insertions, 2266 deletions
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 6cc08166ff00..63f06a2b1f7f 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -1188,8 +1188,10 @@ SYSCALL_DEFINE4(osf_wait4, pid_t, pid, int __user *, ustatus, int, options,
1188 if (!access_ok(VERIFY_WRITE, ur, sizeof(*ur))) 1188 if (!access_ok(VERIFY_WRITE, ur, sizeof(*ur)))
1189 return -EFAULT; 1189 return -EFAULT;
1190 1190
1191 err = 0; 1191 err = put_user(status, ustatus);
1192 err |= put_user(status, ustatus); 1192 if (ret < 0)
1193 return err ? err : ret;
1194
1193 err |= __put_user(r.ru_utime.tv_sec, &ur->ru_utime.tv_sec); 1195 err |= __put_user(r.ru_utime.tv_sec, &ur->ru_utime.tv_sec);
1194 err |= __put_user(r.ru_utime.tv_usec, &ur->ru_utime.tv_usec); 1196 err |= __put_user(r.ru_utime.tv_usec, &ur->ru_utime.tv_usec);
1195 err |= __put_user(r.ru_stime.tv_sec, &ur->ru_stime.tv_sec); 1197 err |= __put_user(r.ru_stime.tv_sec, &ur->ru_stime.tv_sec);
diff --git a/arch/arc/include/asm/delay.h b/arch/arc/include/asm/delay.h
index a36e8601114d..d5da2115d78a 100644
--- a/arch/arc/include/asm/delay.h
+++ b/arch/arc/include/asm/delay.h
@@ -26,7 +26,9 @@ static inline void __delay(unsigned long loops)
26 " lp 1f \n" 26 " lp 1f \n"
27 " nop \n" 27 " nop \n"
28 "1: \n" 28 "1: \n"
29 : : "r"(loops)); 29 :
30 : "r"(loops)
31 : "lp_count");
30} 32}
31 33
32extern void __bad_udelay(void); 34extern void __bad_udelay(void);
diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h
index b5ff87e6f4b7..aee1a77934cf 100644
--- a/arch/arc/include/asm/entry-arcv2.h
+++ b/arch/arc/include/asm/entry-arcv2.h
@@ -16,6 +16,7 @@
16 ; 16 ;
17 ; Now manually save: r12, sp, fp, gp, r25 17 ; Now manually save: r12, sp, fp, gp, r25
18 18
19 PUSH r30
19 PUSH r12 20 PUSH r12
20 21
21 ; Saving pt_regs->sp correctly requires some extra work due to the way 22 ; Saving pt_regs->sp correctly requires some extra work due to the way
@@ -72,6 +73,7 @@
72 POPAX AUX_USER_SP 73 POPAX AUX_USER_SP
731: 741:
74 POP r12 75 POP r12
76 POP r30
75 77
76.endm 78.endm
77 79
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 69095da1fcfd..47111d565a95 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -84,7 +84,7 @@ struct pt_regs {
84 unsigned long fp; 84 unsigned long fp;
85 unsigned long sp; /* user/kernel sp depending on where we came from */ 85 unsigned long sp; /* user/kernel sp depending on where we came from */
86 86
87 unsigned long r12; 87 unsigned long r12, r30;
88 88
89 /*------- Below list auto saved by h/w -----------*/ 89 /*------- Below list auto saved by h/w -----------*/
90 unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11; 90 unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
diff --git a/arch/arc/kernel/unaligned.c b/arch/arc/kernel/unaligned.c
index abd961f3e763..5f69c3bd59bb 100644
--- a/arch/arc/kernel/unaligned.c
+++ b/arch/arc/kernel/unaligned.c
@@ -241,8 +241,9 @@ int misaligned_fixup(unsigned long address, struct pt_regs *regs,
241 if (state.fault) 241 if (state.fault)
242 goto fault; 242 goto fault;
243 243
244 /* clear any remanants of delay slot */
244 if (delay_mode(regs)) { 245 if (delay_mode(regs)) {
245 regs->ret = regs->bta; 246 regs->ret = regs->bta & ~1U;
246 regs->status32 &= ~STATUS_DE_MASK; 247 regs->status32 &= ~STATUS_DE_MASK;
247 } else { 248 } else {
248 regs->ret += state.instr_len; 249 regs->ret += state.instr_len;
diff --git a/arch/arc/mm/mmap.c b/arch/arc/mm/mmap.c
index 2e06d56e987b..cf4ae6958240 100644
--- a/arch/arc/mm/mmap.c
+++ b/arch/arc/mm/mmap.c
@@ -64,7 +64,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
64 64
65 vma = find_vma(mm, addr); 65 vma = find_vma(mm, addr);
66 if (TASK_SIZE - len >= addr && 66 if (TASK_SIZE - len >= addr &&
67 (!vma || addr + len <= vma->vm_start)) 67 (!vma || addr + len <= vm_start_gap(vma)))
68 return addr; 68 return addr;
69 } 69 }
70 70
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c1bff8a87485..4e037366a62f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -494,11 +494,13 @@ dtb-$(CONFIG_SOC_OMAP5) += \
494dtb-$(CONFIG_SOC_DRA7XX) += \ 494dtb-$(CONFIG_SOC_DRA7XX) += \
495 dra7-evm.dtb \ 495 dra7-evm.dtb \
496 dra7-evm-lcd-lg.dtb \ 496 dra7-evm-lcd-lg.dtb \
497 dra7-evm-fpd-lg.dtb \
497 dra7-evm-lcd-lg-late-attach.dtb \ 498 dra7-evm-lcd-lg-late-attach.dtb \
498 dra7-evm-lcd-lg-late-attach-no-map.dtb \ 499 dra7-evm-lcd-lg-late-attach-no-map.dtb \
499 dra7-evm-lcd-osd.dtb \ 500 dra7-evm-lcd-osd.dtb \
500 dra7-evm-lcd-osd101t2587.dtb \ 501 dra7-evm-lcd-osd101t2587.dtb \
501 dra7-evm-lcd-osd-late-attach.dtb \ 502 dra7-evm-lcd-osd-late-attach.dtb \
503 dra7-evm-fpd-auo-g101evn01.0.dtb \
502 dra7-evm-vision.dtb \ 504 dra7-evm-vision.dtb \
503 dra7-evm-robust-rvc.dtb \ 505 dra7-evm-robust-rvc.dtb \
504 dra7-evm-early-video.dtb \ 506 dra7-evm-early-video.dtb \
@@ -516,6 +518,7 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
516 dra72-evm-lcd-lg.dtb \ 518 dra72-evm-lcd-lg.dtb \
517 dra72-evm-lcd-osd.dtb \ 519 dra72-evm-lcd-osd.dtb \
518 dra72-evm-lcd-osd101t2587.dtb \ 520 dra72-evm-lcd-osd101t2587.dtb \
521 dra72-evm-fpd-lg.dtb \
519 dra72-evm-revc.dtb \ 522 dra72-evm-revc.dtb \
520 dra72-evm-revc-lcd-osd101t2045.dtb \ 523 dra72-evm-revc-lcd-osd101t2045.dtb \
521 dra72-evm-revc-lcd-osd101t2587.dtb \ 524 dra72-evm-revc-lcd-osd101t2587.dtb \
@@ -524,7 +527,9 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
524 dra71-evm.dtb \ 527 dra71-evm.dtb \
525 dra71-evm-lcd-auo-g101evn01.0.dtb \ 528 dra71-evm-lcd-auo-g101evn01.0.dtb \
526 dra71-evm-robust-rvc.dtb \ 529 dra71-evm-robust-rvc.dtb \
527 dra71-evm-early-video.dtb 530 dra71-evm-early-video.dtb \
531 dra76-evm.dtb \
532 dra76-evm-fpd-auo-g101evn01.0.dtb
528dtb-$(CONFIG_ARCH_ORION5X) += \ 533dtb-$(CONFIG_ARCH_ORION5X) += \
529 orion5x-lacie-d2-network.dtb \ 534 orion5x-lacie-d2-network.dtb \
530 orion5x-lacie-ethernet-disk-mini-v2.dtb \ 535 orion5x-lacie-ethernet-disk-mini-v2.dtb \
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index cd316021d6ce..6c1b45c1af66 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -89,7 +89,7 @@
89 pinctrl-names = "default"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pca0_pins>; 90 pinctrl-0 = <&pca0_pins>;
91 interrupt-parent = <&gpio0>; 91 interrupt-parent = <&gpio0>;
92 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 92 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
93 gpio-controller; 93 gpio-controller;
94 #gpio-cells = <2>; 94 #gpio-cells = <2>;
95 interrupt-controller; 95 interrupt-controller;
@@ -101,7 +101,7 @@
101 compatible = "nxp,pca9555"; 101 compatible = "nxp,pca9555";
102 pinctrl-names = "default"; 102 pinctrl-names = "default";
103 interrupt-parent = <&gpio0>; 103 interrupt-parent = <&gpio0>;
104 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 104 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
105 gpio-controller; 105 gpio-controller;
106 #gpio-cells = <2>; 106 #gpio-cells = <2>;
107 interrupt-controller; 107 interrupt-controller;
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index e74df327cdd3..20618a897c99 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -122,6 +122,8 @@
122 uart1: serial@f8020000 { 122 uart1: serial@f8020000 {
123 pinctrl-names = "default"; 123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart1_default>; 124 pinctrl-0 = <&pinctrl_uart1_default>;
125 atmel,use-dma-rx;
126 atmel,use-dma-tx;
125 status = "okay"; 127 status = "okay";
126 }; 128 };
127 129
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index f3e2b96c06a3..0bd325c314e1 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -162,9 +162,10 @@
162 }; 162 };
163 163
164 adc0: adc@f8018000 { 164 adc0: adc@f8018000 {
165 atmel,adc-vref = <3300>;
166 atmel,adc-channels-used = <0xfe>;
165 pinctrl-0 = < 167 pinctrl-0 = <
166 &pinctrl_adc0_adtrg 168 &pinctrl_adc0_adtrg
167 &pinctrl_adc0_ad0
168 &pinctrl_adc0_ad1 169 &pinctrl_adc0_ad1
169 &pinctrl_adc0_ad2 170 &pinctrl_adc0_ad2
170 &pinctrl_adc0_ad3 171 &pinctrl_adc0_ad3
@@ -172,8 +173,6 @@
172 &pinctrl_adc0_ad5 173 &pinctrl_adc0_ad5
173 &pinctrl_adc0_ad6 174 &pinctrl_adc0_ad6
174 &pinctrl_adc0_ad7 175 &pinctrl_adc0_ad7
175 &pinctrl_adc0_ad8
176 &pinctrl_adc0_ad9
177 >; 176 >;
178 status = "okay"; 177 status = "okay";
179 }; 178 };
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
index da84e65b56ef..e27024cdf48b 100644
--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -110,6 +110,8 @@
110 }; 110 };
111 111
112 usart3: serial@fc00c000 { 112 usart3: serial@fc00c000 {
113 atmel,use-dma-rx;
114 atmel,use-dma-tx;
113 status = "okay"; 115 status = "okay";
114 }; 116 };
115 117
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 6f50f672efbd..de8ac998604d 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -54,14 +54,14 @@
54 timer@0200 { 54 timer@0200 {
55 compatible = "arm,cortex-a9-global-timer"; 55 compatible = "arm,cortex-a9-global-timer";
56 reg = <0x0200 0x100>; 56 reg = <0x0200 0x100>;
57 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 57 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
58 clocks = <&clk_periph>; 58 clocks = <&clk_periph>;
59 }; 59 };
60 60
61 local-timer@0600 { 61 local-timer@0600 {
62 compatible = "arm,cortex-a9-twd-timer"; 62 compatible = "arm,cortex-a9-twd-timer";
63 reg = <0x0600 0x100>; 63 reg = <0x0600 0x100>;
64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 64 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
65 clocks = <&clk_periph>; 65 clocks = <&clk_periph>;
66 }; 66 };
67 67
diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
new file mode 100644
index 000000000000..2bbc04791628
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
@@ -0,0 +1,393 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/clk/ti-dra7-atl.h>
11#include <dt-bindings/input/input.h>
12
13/ {
14 aliases {
15 display0 = &hdmi0;
16 sound0 = &sound0;
17 sound1 = &hdmi;
18 };
19
20 chosen {
21 stdout-path = &uart1;
22 };
23
24 sound0: sound0 {
25 compatible = "simple-audio-card";
26 simple-audio-card,name = "DRA7xx-EVM";
27 simple-audio-card,widgets =
28 "Headphone", "Headphone Jack",
29 "Line", "Line Out",
30 "Microphone", "Mic Jack",
31 "Line", "Line In";
32 simple-audio-card,routing =
33 "Headphone Jack", "HPLOUT",
34 "Headphone Jack", "HPROUT",
35 "Line Out", "LLOUT",
36 "Line Out", "RLOUT",
37 "MIC3L", "Mic Jack",
38 "MIC3R", "Mic Jack",
39 "Mic Jack", "Mic Bias",
40 "LINE1L", "Line In",
41 "LINE1R", "Line In";
42 simple-audio-card,format = "dsp_b";
43 simple-audio-card,bitclock-master = <&sound0_master>;
44 simple-audio-card,frame-master = <&sound0_master>;
45 simple-audio-card,bitclock-inversion;
46
47 sound0_master: simple-audio-card,cpu {
48 sound-dai = <&mcasp3>;
49 system-clock-frequency = <11289600>;
50 };
51
52 simple-audio-card,codec {
53 sound-dai = <&tlv320aic3106>;
54 clocks = <&atl_clkin2_ck>;
55 };
56 };
57
58 extcon_usb1: extcon_usb1 {
59 compatible = "linux,extcon-usb-gpio";
60 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
61 };
62
63 leds {
64 compatible = "gpio-leds";
65 led0 {
66 label = "dra7:usr1";
67 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
68 default-state = "off";
69 };
70
71 led1 {
72 label = "dra7:usr2";
73 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
74 default-state = "off";
75 };
76
77 led2 {
78 label = "dra7:usr3";
79 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
80 default-state = "off";
81 };
82
83 led3 {
84 label = "dra7:usr4";
85 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
86 default-state = "off";
87 };
88 };
89
90 gpio_keys {
91 compatible = "gpio-keys";
92 #address-cells = <1>;
93 #size-cells = <0>;
94 autorepeat;
95
96 USER1 {
97 label = "btnUser1";
98 linux,code = <BTN_0>;
99 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
100 };
101
102 USER2 {
103 label = "btnUser2";
104 linux,code = <BTN_1>;
105 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
106 };
107 };
108
109 hdmi0: connector@1 {
110 compatible = "hdmi-connector";
111 label = "hdmi";
112
113 type = "a";
114
115 port {
116 hdmi_connector_in: endpoint {
117 remote-endpoint = <&tpd12s015_out>;
118 };
119 };
120 };
121
122 tpd12s015: encoder@1 {
123 ports {
124 #address-cells = <1>;
125 #size-cells = <0>;
126
127 port@0 {
128 reg = <0>;
129
130 tpd12s015_in: endpoint {
131 remote-endpoint = <&hdmi_out>;
132 };
133 };
134
135 port@1 {
136 reg = <1>;
137
138 tpd12s015_out: endpoint {
139 remote-endpoint = <&hdmi_connector_in>;
140 };
141 };
142 };
143 };
144
145 clk_ov10633_fixed: clk_ov10633_fixed {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-frequency = <24000000>;
149 };
150};
151
152&dra7_pmx_core {
153 dcan1_pins_default: dcan1_pins_default {
154 pinctrl-single,pins = <
155 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
156 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
157 >;
158 };
159
160 dcan1_pins_sleep: dcan1_pins_sleep {
161 pinctrl-single,pins = <
162 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
163 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
164 >;
165 };
166};
167
168&i2c3 {
169 status = "okay";
170 clock-frequency = <400000>;
171};
172
173&mcspi1 {
174 status = "okay";
175};
176
177&mcspi2 {
178 status = "okay";
179};
180
181&uart1 {
182 status = "okay";
183 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
184 <&dra7_pmx_core 0x3e0>;
185};
186
187&uart2 {
188 status = "okay";
189};
190
191&uart3 {
192 status = "okay";
193};
194
195&qspi {
196 status = "okay";
197
198 spi-max-frequency = <76800000>;
199 m25p80@0 {
200 compatible = "s25fl256s1";
201 spi-max-frequency = <76800000>;
202 reg = <0>;
203 spi-tx-bus-width = <1>;
204 spi-rx-bus-width = <4>;
205 #address-cells = <1>;
206 #size-cells = <1>;
207
208 /* MTD partition table.
209 * The ROM checks the first four physical blocks
210 * for a valid file to boot and the flash here is
211 * 64KiB block size.
212 */
213 partition@0 {
214 label = "QSPI.SPL";
215 reg = <0x00000000 0x000040000>;
216 };
217 partition@1 {
218 label = "QSPI.u-boot";
219 reg = <0x00040000 0x00100000>;
220 };
221 partition@2 {
222 label = "QSPI.u-boot-spl-os";
223 reg = <0x00140000 0x00080000>;
224 };
225 partition@3 {
226 label = "QSPI.u-boot-env";
227 reg = <0x001c0000 0x00010000>;
228 };
229 partition@4 {
230 label = "QSPI.u-boot-env.backup1";
231 reg = <0x001d0000 0x0010000>;
232 };
233 partition@5 {
234 label = "QSPI.kernel";
235 reg = <0x001e0000 0x0800000>;
236 };
237 partition@6 {
238 label = "QSPI.file-system";
239 reg = <0x009e0000 0x01620000>;
240 };
241 };
242};
243
244&omap_dwc3_1 {
245 extcon = <&extcon_usb1>;
246};
247
248&usb1 {
249 dr_mode = "otg";
250};
251
252&usb2 {
253 dr_mode = "host";
254};
255
256&dcan1 {
257 status = "ok";
258 pinctrl-names = "default", "sleep", "active";
259 pinctrl-0 = <&dcan1_pins_sleep>;
260 pinctrl-1 = <&dcan1_pins_sleep>;
261 pinctrl-2 = <&dcan1_pins_default>;
262};
263
264&atl {
265 assigned-clocks = <&abe_dpll_sys_clk_mux>,
266 <&atl_gfclk_mux>,
267 <&dpll_abe_ck>,
268 <&dpll_abe_m2x2_ck>,
269 <&atl_clkin1_ck>,
270 <&atl_clkin2_ck>;
271 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
272 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
273 <11289600>, <11289600>;
274
275 status = "okay";
276
277 atl2 {
278 bws = <DRA7_ATL_WS_MCASP2_FSX>;
279 aws = <DRA7_ATL_WS_MCASP3_FSX>;
280 };
281};
282
283&mcasp3 {
284 #sound-dai-cells = <0>;
285
286 assigned-clocks = <&mcasp3_ahclkx_mux>;
287 assigned-clock-parents = <&atl_clkin2_ck>;
288
289 status = "okay";
290
291 op-mode = <0>; /* MCASP_IIS_MODE */
292 tdm-slots = <2>;
293 /* 4 serializer */
294 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
295 1 2 0 0
296 >;
297 tx-num-evt = <32>;
298 rx-num-evt = <32>;
299};
300
301&mailbox5 {
302 status = "okay";
303 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
304 status = "okay";
305 };
306 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
307 status = "okay";
308 };
309};
310
311&mailbox6 {
312 status = "okay";
313 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
314 status = "okay";
315 };
316 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
317 status = "okay";
318 };
319};
320
321&mmu0_dsp1 {
322 status = "okay";
323};
324
325&mmu1_dsp1 {
326 status = "okay";
327};
328
329&mmu0_dsp2 {
330 status = "okay";
331};
332
333&mmu1_dsp2 {
334 status = "okay";
335};
336
337&mmu_ipu1 {
338 status = "okay";
339};
340
341&mmu_ipu2 {
342 status = "okay";
343};
344
345&ipu2 {
346 status = "okay";
347 memory-region = <&ipu2_cma_pool>;
348 mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
349 timers = <&timer3>;
350 watchdog-timers = <&timer4>, <&timer9>;
351};
352
353&ipu1 {
354 status = "okay";
355 memory-region = <&ipu1_cma_pool>;
356 mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
357 timers = <&timer11>;
358 watchdog-timers = <&timer7>, <&timer8>;
359};
360
361&dsp1 {
362 status = "okay";
363 memory-region = <&dsp1_cma_pool>;
364 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
365 timers = <&timer5>;
366 watchdog-timers = <&timer10>;
367};
368
369&dsp2 {
370 status = "okay";
371 memory-region = <&dsp2_cma_pool>;
372 mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
373 timers = <&timer6>;
374 watchdog-timers = <&timer13>;
375};
376
377&vip1 {
378 status = "okay";
379};
380
381&hdmi {
382 status = "okay";
383
384 port {
385 hdmi_out: endpoint {
386 remote-endpoint = <&tpd12s015_in>;
387 };
388 };
389};
390
391&pcie1_rc {
392 status = "okay";
393};
diff --git a/arch/arm/boot/dts/dra7-evm-fpd-auo-g101evn01.0.dts b/arch/arm/boot/dts/dra7-evm-fpd-auo-g101evn01.0.dts
new file mode 100644
index 000000000000..64e79754bb22
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm-fpd-auo-g101evn01.0.dts
@@ -0,0 +1,37 @@
1#include "dra7-evm.dts"
2#include "dra7x-evm-fpd-auo-g101evn01.0.dtsi"
3
4/ {
5 aliases {
6 display0 = &fpd_disp;
7 display1 = &hdmi0;
8 };
9};
10
11&dss {
12 ports {
13 status = "ok";
14 };
15};
16
17&disp_ser {
18 status = "ok";
19 ranges = <0x0 0x2d>;
20};
21
22/* Tie the end points of DSS and FPDLink together */
23
24&fpd_in {
25 remote-endpoint = <&dpi_out3>;
26};
27
28&dpi_out3 {
29 remote-endpoint = <&fpd_in>;
30};
31
32&lcd_fpd {
33 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
34 /* P0, SEL_GPMC_AD_VID_S0 */
35
36 status = "ok";
37};
diff --git a/arch/arm/boot/dts/dra7-evm-fpd-lg.dts b/arch/arm/boot/dts/dra7-evm-fpd-lg.dts
new file mode 100644
index 000000000000..b8df0766ecff
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm-fpd-lg.dts
@@ -0,0 +1,38 @@
1#include "dra7-evm.dts"
2#include "dra7x-evm-fpd-lg.dtsi"
3
4/ {
5 aliases {
6 display0 = &fpd_disp;
7 display1 = &hdmi0;
8 };
9};
10
11&dss {
12 ports {
13 status = "ok";
14 };
15};
16
17&disp_ser {
18 status = "ok";
19 ranges = <0x2c 0x2c>,
20 <0x1c 0x1c>;
21};
22
23/* Tie the end points of DSS and FPDLink together */
24
25&fpd_in {
26 remote-endpoint = <&dpi_out3>;
27};
28
29&dpi_out3 {
30 remote-endpoint = <&fpd_in>;
31};
32
33&lcd_fpd {
34 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
35 /* P0, SEL_GPMC_AD_VID_S0 */
36
37 status = "ok";
38};
diff --git a/arch/arm/boot/dts/dra7-evm-lcd-lg.dts b/arch/arm/boot/dts/dra7-evm-lcd-lg.dts
index f67beaa8ff01..2b09d3a8839f 100644
--- a/arch/arm/boot/dts/dra7-evm-lcd-lg.dts
+++ b/arch/arm/boot/dts/dra7-evm-lcd-lg.dts
@@ -14,3 +14,11 @@
14 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 14 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
15}; 15};
16 16
17
18/* Uncomment the below lines to enable the FPDLink display */
19
20/*
21&lcd_fpd {
22 status = "okay";
23};
24*/
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c2af973a17c2..4a8697306e7a 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -8,9 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "dra74x.dtsi" 10#include "dra74x.dtsi"
11#include <dt-bindings/gpio/gpio.h> 11#include "dra7-evm-common.dtsi"
12#include <dt-bindings/clk/ti-dra7-atl.h>
13#include <dt-bindings/input/input.h>
14 12
15/ { 13/ {
16 model = "TI DRA742"; 14 model = "TI DRA742";
@@ -56,13 +54,17 @@
56 }; 54 };
57 55
58 aliases { 56 aliases {
59 display0 = &hdmi0;
60 display1 = &fpd_disp;
61 sound0 = &snd0;
62 sound1 = &hdmi;
63 i2c7 = &disp_ser; 57 i2c7 = &disp_ser;
64 }; 58 };
65 59
60 evm_1v8_sw: fixedregulator-evm_1v8 {
61 compatible = "regulator-fixed";
62 regulator-name = "evm_1v8";
63 vin-supply = <&smps9_reg>;
64 regulator-min-microvolt = <1800000>;
65 regulator-max-microvolt = <1800000>;
66 };
67
66 evm_3v3_sd: fixedregulator-sd { 68 evm_3v3_sd: fixedregulator-sd {
67 compatible = "regulator-fixed"; 69 compatible = "regulator-fixed";
68 regulator-name = "evm_3v3_sd"; 70 regulator-name = "evm_3v3_sd";
@@ -99,16 +101,6 @@
99 enable-active-high; 101 enable-active-high;
100 }; 102 };
101 103
102 extcon_usb1: extcon_usb1 {
103 compatible = "linux,extcon-usb-gpio";
104 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
105 };
106
107 extcon_usb2: extcon_usb2 {
108 compatible = "linux,extcon-usb-gpio";
109 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
110 };
111
112 vtt_fixed: fixedregulator-vtt { 104 vtt_fixed: fixedregulator-vtt {
113 compatible = "regulator-fixed"; 105 compatible = "regulator-fixed";
114 regulator-name = "vtt_fixed"; 106 regulator-name = "vtt_fixed";
@@ -121,151 +113,28 @@
121 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 113 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
122 }; 114 };
123 115
124 snd0: sound@0 { 116 extcon_usb2: extcon_usb2 {
125 compatible = "simple-audio-card"; 117 compatible = "linux,extcon-usb-gpio";
126 simple-audio-card,name = "DRA7xx-EVM"; 118 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
127 simple-audio-card,widgets =
128 "Headphone", "Headphone Jack",
129 "Line", "Line Out",
130 "Microphone", "Mic Jack",
131 "Line", "Line In";
132 simple-audio-card,routing =
133 "Headphone Jack", "HPLOUT",
134 "Headphone Jack", "HPROUT",
135 "Line Out", "LLOUT",
136 "Line Out", "RLOUT",
137 "MIC3L", "Mic Jack",
138 "MIC3R", "Mic Jack",
139 "Mic Jack", "Mic Bias",
140 "LINE1L", "Line In",
141 "LINE1R", "Line In";
142 simple-audio-card,format = "dsp_b";
143 simple-audio-card,bitclock-master = <&sound0_master>;
144 simple-audio-card,frame-master = <&sound0_master>;
145 simple-audio-card,bitclock-inversion;
146
147 sound0_master: simple-audio-card,cpu {
148 sound-dai = <&mcasp3>;
149 system-clock-frequency = <11289600>;
150 };
151
152 simple-audio-card,codec {
153 sound-dai = <&tlv320aic3106>;
154 clocks = <&atl_clkin2_ck>;
155 };
156 };
157
158 leds {
159 compatible = "gpio-leds";
160 led@0 {
161 label = "dra7:usr1";
162 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
163 default-state = "off";
164 };
165
166 led@1 {
167 label = "dra7:usr2";
168 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
169 default-state = "off";
170 };
171
172 led@2 {
173 label = "dra7:usr3";
174 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
175 default-state = "off";
176 };
177
178 led@3 {
179 label = "dra7:usr4";
180 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
181 default-state = "off";
182 };
183 };
184
185 gpio_keys {
186 compatible = "gpio-keys";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 autorepeat;
190
191 USER1 {
192 label = "btnUser1";
193 linux,code = <BTN_0>;
194 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
195 };
196
197 USER2 {
198 label = "btnUser2";
199 linux,code = <BTN_1>;
200 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
201 };
202 };
203
204 hdmi0: connector@1 {
205 compatible = "hdmi-connector";
206 label = "hdmi";
207
208 type = "a";
209
210 port {
211 hdmi_connector_in: endpoint {
212 remote-endpoint = <&tpd12s015_out>;
213 };
214 };
215 }; 119 };
216 120
217 tpd12s015: encoder@1 { 121};
218 compatible = "ti,dra7evm-tpd12s015";
219
220 pinctrl-names = "i2c", "ddc";
221 pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
222 pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
223
224 ddc-i2c-bus = <&i2c2>;
225 mcasp-gpio = <&mcasp8>;
226
227 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
228 <&pcf_hdmi 5 0>, /* P5, LS OE */
229 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
230
231 ports {
232 #address-cells = <1>;
233 #size-cells = <0>;
234
235 port@0 {
236 reg = <0>;
237 122
238 tpd12s015_in: endpoint@0 { 123&tpd12s015 {
239 remote-endpoint = <&hdmi_out>; 124 compatible = "ti,dra7evm-tpd12s015";
240 }; 125 pinctrl-names = "i2c", "ddc";
241 }; 126 pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
127 pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
242 128
243 port@1 { 129 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
244 reg = <1>; 130 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
131 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
245 132
246 tpd12s015_out: endpoint@0 { 133 ddc-i2c-bus = <&i2c2>;
247 remote-endpoint = <&hdmi_connector_in>; 134 mcasp-gpio = <&mcasp8>;
248 };
249 };
250 };
251 };
252}; 135};
253 136
254&dra7_pmx_core { 137&dra7_pmx_core {
255 dcan1_pins_default: dcan1_pins_default {
256 pinctrl-single,pins = <
257 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
258 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
259 >;
260 };
261
262 dcan1_pins_sleep: dcan1_pins_sleep {
263 pinctrl-single,pins = <
264 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
265 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
266 >;
267 };
268
269 hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin { 138 hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
270 pinctrl-single,pins = < 139 pinctrl-single,pins = <
271 /* this pin is used as a GPIO via mcasp */ 140 /* this pin is used as a GPIO via mcasp */
@@ -758,6 +627,8 @@
758 tps659038: tps659038@58 { 627 tps659038: tps659038@58 {
759 compatible = "ti,tps659038"; 628 compatible = "ti,tps659038";
760 reg = <0x58>; 629 reg = <0x58>;
630 ti,palmas-override-powerhold;
631 ti,system-power-controller;
761 632
762 tps659038_pmic { 633 tps659038_pmic {
763 compatible = "ti,tps659038-pmic"; 634 compatible = "ti,tps659038-pmic";
@@ -978,59 +849,10 @@ i2c_p3_exp: &i2c2 {
978 849
979 #address-cells = <1>; 850 #address-cells = <1>;
980 #size-cells = <0>; 851 #size-cells = <0>;
981 ranges = <0x2c 0x2c>, 852 status = "disabled";
982 <0x1c 0x1c>;
983
984 disp_des: deserializer@2c {
985 compatible = "ti,ds90uh928q";
986 reg = <0x2c>;
987 slave-mode;
988 };
989
990 /* TLC chip for LCD panel power and backlight */
991 fpd_disp: tlc59108@1c {
992 status = "disabled";
993 reg = <0x1c>;
994 compatible = "ti,tlc59108-fpddisp";
995 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
996 /* P0, SEL_GPMC_AD_VID_S0 */
997
998 port@lcd3 {
999 fpd_in: endpoint {
1000 remote-endpoint = <&dpi_out3>;
1001 };
1002 };
1003 };
1004 }; 853 };
1005}; 854};
1006 855
1007&i2c3 {
1008 status = "okay";
1009 clock-frequency = <400000>;
1010};
1011
1012&mcspi1 {
1013 status = "okay";
1014};
1015
1016&mcspi2 {
1017 status = "okay";
1018};
1019
1020&uart1 {
1021 status = "okay";
1022 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1023 <&dra7_pmx_core 0x3e0>;
1024};
1025
1026&uart2 {
1027 status = "okay";
1028};
1029
1030&uart3 {
1031 status = "okay";
1032};
1033
1034&mmc1 { 856&mmc1 {
1035 status = "okay"; 857 status = "okay";
1036 vmmc-supply = <&evm_3v3_sd>; 858 vmmc-supply = <&evm_3v3_sd>;
@@ -1088,7 +910,7 @@ i2c_p3_exp: &i2c2 {
1088 910
1089 #address-cells = <1>; 911 #address-cells = <1>;
1090 #size-cells = <0>; 912 #size-cells = <0>;
1091 wlcore: wlcore@0 { 913 wlcore: wlcore@2 {
1092 compatible = "ti,wl1835"; 914 compatible = "ti,wl1835";
1093 reg = <2>; 915 reg = <2>;
1094 interrupt-parent = <&gpio5>; 916 interrupt-parent = <&gpio5>;
@@ -1116,75 +938,10 @@ i2c_p3_exp: &i2c2 {
1116 vdd-supply = <&smps7_reg>; 938 vdd-supply = <&smps7_reg>;
1117}; 939};
1118 940
1119&pcie1_rc {
1120 status = "okay";
1121};
1122
1123&qspi {
1124 status = "okay";
1125
1126 spi-max-frequency = <76800000>;
1127 m25p80@0 {
1128 compatible = "s25fl256s1";
1129 spi-max-frequency = <76800000>;
1130 reg = <0>;
1131 spi-tx-bus-width = <1>;
1132 spi-rx-bus-width = <4>;
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135
1136 /* MTD partition table.
1137 * The ROM checks the first four physical blocks
1138 * for a valid file to boot and the flash here is
1139 * 64KiB block size.
1140 */
1141 partition@0 {
1142 label = "QSPI.SPL";
1143 reg = <0x00000000 0x000040000>;
1144 };
1145 partition@1 {
1146 label = "QSPI.u-boot";
1147 reg = <0x00040000 0x00100000>;
1148 };
1149 partition@2 {
1150 label = "QSPI.u-boot-spl-os";
1151 reg = <0x00140000 0x00080000>;
1152 };
1153 partition@3 {
1154 label = "QSPI.u-boot-env";
1155 reg = <0x001c0000 0x00010000>;
1156 };
1157 partition@4 {
1158 label = "QSPI.u-boot-env.backup1";
1159 reg = <0x001d0000 0x0010000>;
1160 };
1161 partition@5 {
1162 label = "QSPI.kernel";
1163 reg = <0x001e0000 0x0800000>;
1164 };
1165 partition@6 {
1166 label = "QSPI.file-system";
1167 reg = <0x009e0000 0x01620000>;
1168 };
1169 };
1170};
1171
1172&omap_dwc3_1 {
1173 extcon = <&extcon_usb1>;
1174};
1175
1176&omap_dwc3_2 { 941&omap_dwc3_2 {
1177 extcon = <&extcon_usb2>; 942 extcon = <&extcon_usb2>;
1178}; 943};
1179 944
1180&usb1 {
1181 dr_mode = "otg";
1182};
1183
1184&usb2 {
1185 dr_mode = "host";
1186};
1187
1188&elm { 945&elm {
1189 status = "okay"; 946 status = "okay";
1190}; 947};
@@ -1301,131 +1058,6 @@ i2c_p3_exp: &i2c2 {
1301 dual_emac_res_vlan = <2>; 1058 dual_emac_res_vlan = <2>;
1302}; 1059};
1303 1060
1304&dcan1 {
1305 status = "ok";
1306 pinctrl-names = "default", "sleep", "active";
1307 pinctrl-0 = <&dcan1_pins_sleep>;
1308 pinctrl-1 = <&dcan1_pins_sleep>;
1309 pinctrl-2 = <&dcan1_pins_default>;
1310};
1311
1312&atl {
1313 assigned-clocks = <&abe_dpll_sys_clk_mux>,
1314 <&atl_gfclk_mux>,
1315 <&dpll_abe_ck>,
1316 <&dpll_abe_m2x2_ck>,
1317 <&atl_clkin1_ck>,
1318 <&atl_clkin2_ck>;
1319 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
1320 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
1321 <11289600>, <11289600>;
1322
1323 status = "okay";
1324
1325 atl2 {
1326 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1327 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1328 };
1329};
1330
1331&mcasp3 {
1332 #sound-dai-cells = <0>;
1333
1334 assigned-clocks = <&mcasp3_ahclkx_mux>;
1335 assigned-clock-parents = <&atl_clkin2_ck>;
1336
1337 status = "okay";
1338
1339 op-mode = <0>; /* MCASP_IIS_MODE */
1340 tdm-slots = <2>;
1341 /* 4 serializer */
1342 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1343 1 2 0 0
1344 >;
1345 tx-num-evt = <32>;
1346 rx-num-evt = <32>;
1347};
1348
1349&mcasp8 {
1350 /* not used for audio. only the AXR2 pin is used as GPIO */
1351 status = "okay";
1352};
1353
1354&mailbox5 {
1355 status = "okay";
1356 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
1357 status = "okay";
1358 };
1359 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
1360 status = "okay";
1361 };
1362};
1363
1364&mailbox6 {
1365 status = "okay";
1366 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
1367 status = "okay";
1368 };
1369 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
1370 status = "okay";
1371 };
1372};
1373
1374&mmu0_dsp1 {
1375 status = "okay";
1376};
1377
1378&mmu1_dsp1 {
1379 status = "okay";
1380};
1381
1382&mmu0_dsp2 {
1383 status = "okay";
1384};
1385
1386&mmu1_dsp2 {
1387 status = "okay";
1388};
1389
1390&mmu_ipu1 {
1391 status = "okay";
1392};
1393
1394&mmu_ipu2 {
1395 status = "okay";
1396};
1397
1398&ipu2 {
1399 status = "okay";
1400 memory-region = <&ipu2_cma_pool>;
1401 mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
1402 timers = <&timer3>;
1403 watchdog-timers = <&timer4>, <&timer9>;
1404};
1405
1406&ipu1 {
1407 status = "okay";
1408 memory-region = <&ipu1_cma_pool>;
1409 mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
1410 timers = <&timer11>;
1411 watchdog-timers = <&timer7>, <&timer8>;
1412};
1413
1414&dsp1 {
1415 status = "okay";
1416 memory-region = <&dsp1_cma_pool>;
1417 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
1418 timers = <&timer5>;
1419 watchdog-timers = <&timer10>;
1420};
1421
1422&dsp2 {
1423 status = "okay";
1424 memory-region = <&dsp2_cma_pool>;
1425 mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
1426 timers = <&timer6>;
1427};
1428
1429&dss { 1061&dss {
1430 status = "okay"; 1062 status = "okay";
1431 1063
@@ -1440,29 +1072,18 @@ i2c_p3_exp: &i2c2 {
1440 reg = <2>; 1072 reg = <2>;
1441 1073
1442 dpi_out3: endpoint { 1074 dpi_out3: endpoint {
1443 remote-endpoint = <&fpd_in>;
1444 data-lines = <24>; 1075 data-lines = <24>;
1445 }; 1076 };
1446 }; 1077 };
1447 }; 1078 };
1448}; 1079};
1449 1080
1450&bb2d {
1451 status = "okay";
1452};
1453
1454&hdmi { 1081&hdmi {
1455 status = "ok";
1456 vdda-supply = <&ldo3_reg>; 1082 vdda-supply = <&ldo3_reg>;
1457
1458 port {
1459 hdmi_out: endpoint {
1460 remote-endpoint = <&tpd12s015_in>;
1461 };
1462 };
1463}; 1083};
1464 1084
1465&vip1 { 1085&mcasp8 {
1086 /* not used for audio. only the AXR2 pin is used as GPIO */
1466 status = "okay"; 1087 status = "okay";
1467}; 1088};
1468 1089
@@ -1474,6 +1095,10 @@ video_in: &vin1a {
1474 }; 1095 };
1475}; 1096};
1476 1097
1098&bb2d {
1099 status = "okay";
1100};
1101
1477#include "dra7xx-jamr3.dtsi" 1102#include "dra7xx-jamr3.dtsi"
1478&tvp_5158{ 1103&tvp_5158{
1479 mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>, /*CAM_FPD_MUX_S0*/ 1104 mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>, /*CAM_FPD_MUX_S0*/
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 4a2b643bd60d..43316d454d41 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -300,7 +300,6 @@
300 * node and enable pcie1_ep mode. 300 * node and enable pcie1_ep mode.
301 */ 301 */
302 pcie1_rc: pcie_rc@51000000 { 302 pcie1_rc: pcie_rc@51000000 {
303 compatible = "ti,dra7-pcie";
304 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 303 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
305 reg-names = "rc_dbics", "ti_conf", "config"; 304 reg-names = "rc_dbics", "ti_conf", "config";
306 interrupts = <0 232 0x4>, <0 233 0x4>; 305 interrupts = <0 232 0x4>, <0 233 0x4>;
@@ -315,6 +314,8 @@
315 ti,hwmods = "pcie1"; 314 ti,hwmods = "pcie1";
316 phys = <&pcie1_phy>; 315 phys = <&pcie1_phy>;
317 phy-names = "pcie-phy0"; 316 phy-names = "pcie-phy0";
317 syscon-lane-conf = <&scm_conf 0x558>;
318 syscon-lane-sel = <&scm_conf_pcie 0x18>;
318 interrupt-map-mask = <0 0 0 7>; 319 interrupt-map-mask = <0 0 0 7>;
319 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 320 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
320 <0 0 0 2 &pcie1_intc 2>, 321 <0 0 0 2 &pcie1_intc 2>,
@@ -329,7 +330,6 @@
329 }; 330 };
330 331
331 pcie1_ep: pcie_ep@51000000 { 332 pcie1_ep: pcie_ep@51000000 {
332 compatible = "ti,dra7-pcie-ep";
333 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 333 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
334 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 334 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
335 interrupts = <0 232 0x4>; 335 interrupts = <0 232 0x4>;
@@ -351,8 +351,7 @@
351 ranges = <0x51800000 0x51800000 0x3000 351 ranges = <0x51800000 0x51800000 0x3000
352 0x0 0x30000000 0x10000000>; 352 0x0 0x30000000 0x10000000>;
353 status = "disabled"; 353 status = "disabled";
354 pcie@51800000 { 354 pcie2_rc: pcie@51800000 {
355 compatible = "ti,dra7-pcie";
356 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 355 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
357 reg-names = "rc_dbics", "ti_conf", "config"; 356 reg-names = "rc_dbics", "ti_conf", "config";
358 interrupts = <0 355 0x4>, <0 356 0x4>; 357 interrupts = <0 355 0x4>, <0 356 0x4>;
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 4ff5187da184..aa3b8abde63d 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -16,7 +16,6 @@
16 16
17 aliases { 17 aliases {
18 display0 = &hdmi0; 18 display0 = &hdmi0;
19 display1 = &fpd_disp;
20 sound0 = &snd0; 19 sound0 = &snd0;
21 sound1 = &hdmi; 20 sound1 = &hdmi;
22 i2c7 = &disp_ser; 21 i2c7 = &disp_ser;
@@ -589,35 +588,14 @@ i2c_p3_exp: &i2c5 {
589 disp_ser: serializer@1b { 588 disp_ser: serializer@1b {
590 compatible = "ti,ds90uh925q"; 589 compatible = "ti,ds90uh925q";
591 reg = <0x1b>; 590 reg = <0x1b>;
591 status = "disabled";
592 592
593 #address-cells = <1>; 593 #address-cells = <1>;
594 #size-cells = <0>; 594 #size-cells = <0>;
595 ranges = <0x2c 0x2c>,
596 <0x1c 0x1c>;
597
598 disp_des: deserializer@2c {
599 compatible = "ti,ds90uh928q";
600 reg = <0x2c>;
601 slave-mode;
602 };
603
604 /* TLC chip for LCD panel power and backlight */
605 fpd_disp: tlc59108@1c {
606 status = "disabled";
607 reg = <0x1c>;
608 compatible = "ti,tlc59108-fpddisp";
609 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
610 /* P0, SEL_GPMC_AD_VID_S0 */
611
612 port@lcd3 {
613 fpd_in: endpoint {
614 remote-endpoint = <&dpi_out3>;
615 };
616 };
617 };
618 }; 595 };
619}; 596};
620 597
598
621&dss { 599&dss {
622 status = "ok"; 600 status = "ok";
623 vdda_video-supply = <&ldo5_reg>; 601 vdda_video-supply = <&ldo5_reg>;
@@ -630,7 +608,6 @@ i2c_p3_exp: &i2c5 {
630 reg = <2>; 608 reg = <2>;
631 609
632 dpi_out3: endpoint { 610 dpi_out3: endpoint {
633 remote-endpoint = <&fpd_in>;
634 data-lines = <24>; 611 data-lines = <24>;
635 }; 612 };
636 }; 613 };
diff --git a/arch/arm/boot/dts/dra72-evm-fpd-lg.dts b/arch/arm/boot/dts/dra72-evm-fpd-lg.dts
new file mode 100644
index 000000000000..9ed0f66fdb76
--- /dev/null
+++ b/arch/arm/boot/dts/dra72-evm-fpd-lg.dts
@@ -0,0 +1,39 @@
1#include "dra72-evm.dts"
2#include "dra7x-evm-fpd-lg.dtsi"
3
4/* Set display aliases for use by Android */
5/ {
6 aliases {
7 display0 = &fpd_disp;
8 display1 = &hdmi0;
9 };
10};
11
12&dss {
13 ports {
14 status = "ok";
15 };
16};
17
18&disp_ser {
19 status = "ok";
20 ranges = <0x2c 0x2c>,
21 <0x1c 0x1c>;
22};
23
24/* Tie the end points of DSS and FPDLink together */
25
26&fpd_in {
27 remote-endpoint = <&dpi_out3>;
28};
29
30&dpi_out3 {
31 remote-endpoint = <&fpd_in>;
32};
33
34&lcd_fpd {
35 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
36 /* P0, SEL_GPMC_AD_VID_S0 */
37
38 status = "ok";
39};
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index deef9b8520b2..cc108d2f9b09 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -11,7 +11,6 @@
11 11
12 aliases { 12 aliases {
13 display0 = &hdmi0; 13 display0 = &hdmi0;
14 display1 = &fpd_disp;
15 sound1 = &hdmi; 14 sound1 = &hdmi;
16 i2c7 = &disp_ser; 15 i2c7 = &disp_ser;
17 }; 16 };
@@ -215,39 +214,6 @@
215 }; 214 };
216}; 215};
217 216
218&i2c5 {
219 disp_ser: serializer@1b {
220 compatible = "ti,ds90uh925q";
221 reg = <0x1b>;
222
223 #address-cells = <1>;
224 #size-cells = <0>;
225 ranges = <0x2c 0x2c>,
226 <0x1c 0x1c>;
227
228 disp_des: deserializer@2c {
229 compatible = "ti,ds90uh928q";
230 reg = <0x2c>;
231 slave-mode;
232 };
233
234 /* TLC chip for LCD panel power and backlight */
235 fpd_disp: tlc59108@1c {
236 status = "disabled";
237 reg = <0x1c>;
238 compatible = "ti,tlc59108-fpddisp";
239 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
240 /* P0, SEL_GPMC_AD_VID_S0 */
241
242 port@lcd3 {
243 fpd_in: endpoint {
244 remote-endpoint = <&dpi_out3>;
245 };
246 };
247 };
248 };
249};
250
251&hdmi { 217&hdmi {
252 vdda_video-supply = <&ldo5_reg>; 218 vdda_video-supply = <&ldo5_reg>;
253}; 219};
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index 68341c30beb1..29705754460c 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -140,3 +140,15 @@
140 status = "disabled"; 140 status = "disabled";
141 }; 141 };
142}; 142};
143
144&pcie1_rc {
145 compatible = "ti,dra726-pcie-rc";
146};
147
148&pcie1_ep {
149 compatible = "ti,dra726-pcie-ep";
150};
151
152&pcie2_rc {
153 compatible = "ti,dra726-pcie-rc";
154};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index b96f6c7f77d0..a95a1d17ad2d 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -259,3 +259,15 @@
259 status = "disabled"; 259 status = "disabled";
260 }; 260 };
261}; 261};
262
263&pcie1_rc {
264 compatible = "ti,dra746-pcie-rc";
265};
266
267&pcie1_ep {
268 compatible = "ti,dra746-pcie-ep";
269};
270
271&pcie2_rc {
272 compatible = "ti,dra746-pcie-rc";
273};
diff --git a/arch/arm/boot/dts/dra76-evm-fpd-auo-g101evn01.0.dts b/arch/arm/boot/dts/dra76-evm-fpd-auo-g101evn01.0.dts
new file mode 100644
index 000000000000..69983d70d1f4
--- /dev/null
+++ b/arch/arm/boot/dts/dra76-evm-fpd-auo-g101evn01.0.dts
@@ -0,0 +1,67 @@
1#include "dra76-evm.dts"
2#include "dra7x-evm-fpd-auo-g101evn01.0.dtsi"
3
4/ {
5 aliases {
6 display0 = &fpd_disp;
7 display1 = &hdmi0;
8 };
9};
10
11&dss {
12 ports {
13 status = "ok";
14 };
15};
16
17&disp_ser {
18 status = "ok";
19 ranges = <0x0 0x2d>;
20};
21
22/* Tie the end points of DSS and FPDLink together */
23&fpd_in {
24 remote-endpoint = <&dpi_out3>;
25};
26
27&dpi_out3 {
28 remote-endpoint = <&fpd_in>;
29};
30
31&lcd_fpd {
32 status = "ok";
33};
34
35/* U21 on the EVM */
36/* gpmc_ad_vid_s0: high: GPMC , low: VOUT3 */
37&pcf_gpio_21 {
38 p0 {
39 gpio-hog;
40 gpios = <0 GPIO_ACTIVE_HIGH>;
41 output-low;
42 line-name = "gpmc_ad_vid_s0";
43 };
44};
45
46
47/* U110 on the EVM. For Rev A boards */
48/*
49&pcf_hdmi {
50 p11 {
51 gpio-hog;
52 gpios = <11 GPIO_ACTIVE_HIGH>;
53 output-low;
54 line-name = "disp1_vpoc_onn";
55 };
56};
57*/
58
59/* For supplying power to the display via FPDLink */
60&gpio2 {
61 p2 {
62 gpio-hog;
63 gpios = <2 GPIO_ACTIVE_HIGH>;
64 output-low;
65 line-name = "disp1_vpoc_onn";
66 };
67};
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
new file mode 100644
index 000000000000..213f4b53f965
--- /dev/null
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -0,0 +1,498 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra76x.dtsi"
11#include "dra7-evm-common.dtsi"
12#include "dra76x-mmc-iodelay.dtsi"
13#include <dt-bindings/net/ti-dp83867.h>
14
15/ {
16 model = "TI DRA762 EVM";
17 compatible = "ti,dra76-evm", "ti,dra76", "ti,dra7";
18
19 memory {
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x80000000>;
22 };
23
24 reserved-memory {
25 #address-cells = <2>;
26 #size-cells = <2>;
27 ranges;
28
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x0 0x95800000 0x0 0x3800000>;
32 reusable;
33 status = "okay";
34 };
35
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x0 0x99000000 0x0 0x4000000>;
39 reusable;
40 status = "okay";
41 };
42
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x0 0x9d000000 0x0 0x2000000>;
46 reusable;
47 status = "okay";
48 };
49
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x0 0x9f000000 0x0 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
57
58 aliases {
59 i2c7 = &disp_ser;
60 };
61
62 vsys_12v0: fixedregulator-vsys12v0 {
63 /* main supply */
64 compatible = "regulator-fixed";
65 regulator-name = "vsys_12v0";
66 regulator-min-microvolt = <12000000>;
67 regulator-max-microvolt = <12000000>;
68 regulator-always-on;
69 regulator-boot-on;
70 };
71
72 vsys_5v0: fixedregulator-vsys5v0 {
73 /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
74 compatible = "regulator-fixed";
75 regulator-name = "vsys_5v0";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 vin-supply = <&vsys_12v0>;
79 regulator-always-on;
80 regulator-boot-on;
81 };
82
83 vsys_3v3: fixedregulator-vsys3v3 {
84 /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
85 compatible = "regulator-fixed";
86 regulator-name = "vsys_3v3";
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
89 vin-supply = <&vsys_12v0>;
90 regulator-always-on;
91 regulator-boot-on;
92 };
93
94 vio_3v3: fixedregulator-vio_3v3 {
95 compatible = "regulator-fixed";
96 regulator-name = "vio_3v3";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 vin-supply = <&vsys_3v3>;
100 regulator-always-on;
101 regulator-boot-on;
102 };
103
104 vio_3v3_sd: fixedregulator-sd {
105 compatible = "regulator-fixed";
106 regulator-name = "vio_3v3_sd";
107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <3300000>;
109 vin-supply = <&vio_3v3>;
110 enable-active-high;
111 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
112 };
113
114 vio_1v8: fixedregulator-vio_1v8 {
115 compatible = "regulator-fixed";
116 regulator-name = "vio_1v8";
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>;
119 vin-supply = <&smps5_reg>;
120 };
121
122 vtt_fixed: fixedregulator-vtt {
123 compatible = "regulator-fixed";
124 regulator-name = "vtt_fixed";
125 regulator-min-microvolt = <1350000>;
126 regulator-max-microvolt = <1350000>;
127 vin-supply = <&vsys_3v3>;
128 regulator-always-on;
129 regulator-boot-on;
130 };
131
132 aic_dvdd: fixedregulator-aic_dvdd {
133 /* TPS77018DBVT */
134 compatible = "regulator-fixed";
135 regulator-name = "aic_dvdd";
136 vin-supply = <&vio_3v3>;
137 regulator-min-microvolt = <1800000>;
138 regulator-max-microvolt = <1800000>;
139 };
140};
141
142&i2c1 {
143 status = "okay";
144 clock-frequency = <400000>;
145
146 tps65917: tps65917@58 {
147 compatible = "ti,tps65917";
148 reg = <0x58>;
149 ti,system-power-controller;
150 interrupt-controller;
151 #interrupt-cells = <2>;
152
153 tps65917_pmic {
154 compatible = "ti,tps65917-pmic";
155
156 smps12-in-supply = <&vsys_3v3>;
157 smps3-in-supply = <&vsys_3v3>;
158 smps4-in-supply = <&vsys_3v3>;
159 smps5-in-supply = <&vsys_3v3>;
160 ldo1-in-supply = <&vsys_3v3>;
161 ldo2-in-supply = <&vsys_3v3>;
162 ldo3-in-supply = <&vsys_5v0>;
163 ldo4-in-supply = <&vsys_5v0>;
164 ldo5-in-supply = <&vsys_3v3>;
165
166 tps65917_regulators: regulators {
167 smps12_reg: smps12 {
168 /* VDD_DSPEVE */
169 regulator-name = "smps12";
170 regulator-min-microvolt = <850000>;
171 regulator-max-microvolt = <1250000>;
172 regulator-always-on;
173 regulator-boot-on;
174 };
175
176 smps3_reg: smps3 {
177 /* VDD_CORE */
178 regulator-name = "smps3";
179 regulator-min-microvolt = <850000>;
180 regulator-max-microvolt = <1250000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 smps4_reg: smps4 {
186 /* VDD_IVA */
187 regulator-name = "smps4";
188 regulator-min-microvolt = <850000>;
189 regulator-max-microvolt = <1250000>;
190 regulator-always-on;
191 regulator-boot-on;
192 };
193
194 smps5_reg: smps5 {
195 /* VDDS1V8 */
196 regulator-name = "smps5";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 ldo1_reg: ldo1 {
204 /* LDO1_OUT --> VDA_PHY1_1V8 */
205 regulator-name = "ldo1";
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <1800000>;
208 regulator-always-on;
209 regulator-boot-on;
210 regulator-allow-bypass;
211 };
212
213 ldo2_reg: ldo2 {
214 /* LDO2_OUT --> VDA_PHY2_1V8 */
215 regulator-name = "ldo2";
216 regulator-min-microvolt = <1800000>;
217 regulator-max-microvolt = <1800000>;
218 regulator-allow-bypass;
219 regulator-always-on;
220 };
221
222 ldo3_reg: ldo3 {
223 /* VDA_USB_3V3 */
224 regulator-name = "ldo3";
225 regulator-min-microvolt = <3300000>;
226 regulator-max-microvolt = <3300000>;
227 regulator-boot-on;
228 regulator-always-on;
229 };
230
231 ldo5_reg: ldo5 {
232 /* VDDA_1V8_PLL */
233 regulator-name = "ldo5";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239
240 ldo4_reg: ldo4 {
241 /* VDD_SDIO_DV */
242 regulator-name = "ldo4";
243 regulator-min-microvolt = <1800000>;
244 regulator-max-microvolt = <3300000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248 };
249 };
250
251 tps65917_power_button {
252 compatible = "ti,palmas-pwrbutton";
253 interrupt-parent = <&tps65917>;
254 interrupts = <1 IRQ_TYPE_NONE>;
255 wakeup-source;
256 ti,palmas-long-press-seconds = <6>;
257 };
258 };
259
260 lp87565: lp87565@60 {
261 compatible = "ti,lp87565-q1";
262 reg = <0x60>;
263
264 buck10-in-supply =<&vsys_3v3>;
265 buck23-in-supply =<&vsys_3v3>;
266
267 regulators: regulators {
268 buck10_reg: buck10 {
269 /*VDD_MPU*/
270 regulator-name = "buck10";
271 regulator-min-microvolt = <850000>;
272 regulator-max-microvolt = <1250000>;
273 regulator-always-on;
274 regulator-boot-on;
275 };
276
277 buck23_reg: buck23 {
278 /* VDD_GPU*/
279 regulator-name = "buck23";
280 regulator-min-microvolt = <850000>;
281 regulator-max-microvolt = <1250000>;
282 regulator-boot-on;
283 regulator-always-on;
284 };
285 };
286 };
287
288 pcf_lcd: pcf8757@20 {
289 compatible = "ti,pcf8575", "nxp,pcf8575";
290 reg = <0x20>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 interrupt-parent = <&gpio1>;
296 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
297 };
298
299 pcf_gpio_21: pcf8757@21 {
300 compatible = "ti,pcf8575", "nxp,pcf8575";
301 reg = <0x21>;
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-parent = <&gpio1>;
305 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 };
309
310 pcf_hdmi: pcf8575@26 {
311 compatible = "ti,pcf8575", "nxp,pcf8575";
312 reg = <0x26>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 p1 {
316 /* vin6_sel_s0: high: VIN6, low: audio */
317 gpio-hog;
318 gpios = <1 GPIO_ACTIVE_HIGH>;
319 output-low;
320 line-name = "vin6_sel_s0";
321 };
322 };
323
324 tlv320aic3106: tlv320aic3106@19 {
325 #sound-dai-cells = <0>;
326 compatible = "ti,tlv320aic3106";
327 reg = <0x19>;
328 adc-settle-ms = <40>;
329 ai3x-micbias-vg = <1>; /* 2.0V */
330 status = "okay";
331
332 /* Regulators */
333 AVDD-supply = <&vio_3v3>;
334 IOVDD-supply = <&vio_3v3>;
335 DRVDD-supply = <&vio_3v3>;
336 DVDD-supply = <&aic_dvdd>;
337 };
338};
339
340&tpd12s015 {
341 compatible = "ti,tpd12s015";
342
343 gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
344 <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
345 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
346
347};
348
349&mmc1 {
350 status = "okay";
351 vmmc-supply = <&vio_3v3_sd>;
352 vmmc_aux-supply = <&ldo4_reg>;
353 bus-width = <4>;
354 /*
355 * SDCD signal is not being used here - using the fact that GPIO mode
356 * is always hardwired.
357 */
358 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
359 max-frequency = <192000000>;
360 pinctrl-names = "default", "hs";
361 pinctrl-0 = <&mmc1_pins_default>;
362 pinctrl-1 = <&mmc1_pins_hs>;
363};
364
365&mmc2 {
366 status = "okay";
367 vmmc-supply = <&vio_1v8>;
368 bus-width = <8>;
369 max-frequency = <192000000>;
370 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
371 pinctrl-0 = <&mmc2_pins_default>;
372 pinctrl-1 = <&mmc2_pins_hs>;
373 pinctrl-2 = <&mmc2_pins_ddr>;
374 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
375};
376
377&oppdm_mpu {
378 vdd-supply = <&buck10_reg>;
379};
380
381&oppdm_dspeve {
382 vdd-supply = <&smps12_reg>;
383};
384
385&oppdm_gpu {
386 vdd-supply = <&buck23_reg>;
387};
388
389&oppdm_ivahd {
390 vdd-supply = <&smps4_reg>;
391};
392
393&oppdm_core {
394 vdd-supply = <&smps3_reg>;
395};
396
397/* No RTC on this device */
398&rtc {
399 status = "disabled";
400};
401
402&mac {
403 status = "okay";
404
405 dual_emac;
406};
407
408&cpsw_emac0 {
409 phy_id = <&davinci_mdio>, <2>;
410 phy-mode = "rgmii-id";
411 dual_emac_res_vlan = <1>;
412};
413
414&cpsw_emac1 {
415 phy_id = <&davinci_mdio>, <3>;
416 phy-mode = "rgmii-id";
417 dual_emac_res_vlan = <2>;
418};
419
420&davinci_mdio {
421 dp83867_0: ethernet-phy@2 {
422 reg = <2>;
423 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
424 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
425 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
426 ti,min-output-impedance;
427 ti,dp83867-rxctrl-strap-quirk;
428 };
429
430 dp83867_1: ethernet-phy@3 {
431 reg = <3>;
432 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
433 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
434 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
435 ti,min-output-impedance;
436 ti,dp83867-rxctrl-strap-quirk;
437 };
438};
439
440&usb2_phy1 {
441 phy-supply = <&ldo3_reg>;
442};
443
444&usb2_phy2 {
445 phy-supply = <&ldo3_reg>;
446};
447
448&i2c3 {
449 disp_ser: serializer@0c {
450 compatible = "ti,ds90ub921q";
451 reg = <0x0c>;
452
453 #address-cells = <1>;
454 #size-cells = <0>;
455 status = "disabled";
456 };
457};
458
459&dss {
460 status = "ok";
461 vdda_video-supply = <&ldo5_reg>;
462
463 ports {
464 #address-cells = <1>;
465 #size-cells = <0>;
466
467 status = "disabled";
468
469 port@lcd3 {
470 reg = <2>;
471
472 dpi_out3: endpoint {
473 data-lines = <24>;
474 };
475 };
476 };
477};
478
479&hdmi {
480 vdda-supply = <&ldo1_reg>;
481};
482
483&qspi {
484 spi-max-frequency = <96000000>;
485 m25p80@0 {
486 spi-max-frequency = <96000000>;
487 };
488};
489
490&pcie2_phy {
491 status = "okay";
492};
493
494&pcie1_rc {
495 num-lanes = <2>;
496 phys = <&pcie1_phy>, <&pcie2_phy>;
497 phy-names = "pcie-phy0", "pcie-phy1";
498};
diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 000000000000..c95a8a1091ab
--- /dev/null
+++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,435 @@
1/*
2 * MMC IOdelay values for TI's DRA76x and AM576x SoCs.
3 *
4 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/*
17 * Rules for modifying this file:
18 * a) Update of this file should typically correspond to a datamanual revision.
19 * Datamanual revision that was used should be updated in comment below.
20 * If there is no update to datamanual, do not update the values. If you
21 * need to use values different from that recommended by the datamanual
22 * for your design, then you should consider adding values to the device-
23 * -tree file for your board directly.
24 * b) We keep the mode names as close to the datamanual as possible. So
25 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
26 * we follow that in code too.
27 * c) If the values change between multiple revisions of silicon, we add
28 * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
29 * 'rev20' for PG 2.0 and so on.
30 * d) The node name and node label should be the exact same string. This is
31 * to curb naming creativity and achieve consistency.
32 *
33 * Datamanual Revisions:
34 *
35 * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
36 *
37 */
38
39&dra7_pmx_core {
40 mmc1_pins_default: mmc1_pins_default {
41 pinctrl-single,pins = <
42 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
43 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
44 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
45 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
46 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
47 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 >;
49 };
50
51 mmc1_pins_sdr12: mmc1_pins_sdr12 {
52 pinctrl-single,pins = <
53 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
54 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
55 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
56 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
57 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
58 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
59 >;
60 };
61
62 mmc1_pins_hs: mmc1_pins_hs {
63 pinctrl-single,pins = <
64 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
65 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
66 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
67 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
68 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
69 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
70 >;
71 };
72
73 mmc1_pins_sdr25: mmc1_pins_sdr25 {
74 pinctrl-single,pins = <
75 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
76 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
77 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
78 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
79 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
80 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
81 >;
82 };
83
84 mmc1_pins_sdr50: mmc1_pins_sdr50 {
85 pinctrl-single,pins = <
86 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
87 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
88 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
89 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
90 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
91 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
92 >;
93 };
94
95 mmc1_pins_ddr50: mmc1_pins_ddr50 {
96 pinctrl-single,pins = <
97 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
98 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
99 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
100 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
101 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
102 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
103 >;
104 };
105
106 mmc1_pins_sdr104: mmc1_pins_sdr104 {
107 pinctrl-single,pins = <
108 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
109 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
110 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
111 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
112 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
113 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
114 >;
115 };
116
117 mmc2_pins_default: mmc2_pins_default {
118 pinctrl-single,pins = <
119 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
120 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
121 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
122 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
123 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
124 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
125 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
126 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
127 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
128 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
129 >;
130 };
131
132 mmc2_pins_hs: mmc2_pins_hs {
133 pinctrl-single,pins = <
134 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
135 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
136 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
137 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
138 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
139 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
140 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
141 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
142 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
143 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
144 >;
145 };
146
147 mmc2_pins_ddr: mmc2_pins_ddr {
148 pinctrl-single,pins = <
149 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
150 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
151 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
152 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
153 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
154 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
155 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
156 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
157 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
158 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
159 >;
160 };
161
162 mmc2_pins_hs200: mmc2_pins_hs200 {
163 pinctrl-single,pins = <
164 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
165 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
166 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
167 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
168 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
169 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
170 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
171 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
172 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
173 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
174 >;
175 };
176
177 mmc3_pins_default: mmc3_pins_default {
178 pinctrl-single,pins = <
179 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
180 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
181 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
182 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
183 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
184 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
185 >;
186 };
187
188 mmc3_pins_hs: mmc3_pins_hs {
189 pinctrl-single,pins = <
190 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
191 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
192 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
193 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
194 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
195 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
196 >;
197 };
198
199 mmc3_pins_sdr12: mmc3_pins_sdr12 {
200 pinctrl-single,pins = <
201 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
202 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
203 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
204 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
205 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
206 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
207 >;
208 };
209
210 mmc3_pins_sdr25: mmc3_pins_sdr25 {
211 pinctrl-single,pins = <
212 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
213 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
214 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
215 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
216 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
217 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
218 >;
219 };
220
221 mmc3_pins_sdr50: mmc3_pins_sdr50 {
222 pinctrl-single,pins = <
223 DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
224 DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
225 DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
226 DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
227 DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
228 DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
229 >;
230 };
231
232 mmc4_pins_default: mmc4_pins_default {
233 pinctrl-single,pins = <
234 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
235 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
236 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
237 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
238 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
239 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
240 >;
241 };
242
243 mmc4_pins_sdr12: mmc4_pins_sdr12 {
244 pinctrl-single,pins = <
245 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
246 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
247 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
248 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
249 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
250 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
251 >;
252 };
253
254 mmc4_pins_hs: mmc4_pins_hs {
255 pinctrl-single,pins = <
256 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
257 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
258 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
259 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
260 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
261 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
262 >;
263 };
264
265 mmc4_pins_sdr25: mmc4_pins_sdr25 {
266 pinctrl-single,pins = <
267 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
268 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
269 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
270 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
271 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
272 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
273 >;
274 };
275};
276
277&dra7_iodelay_core {
278
279 /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
280 mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
281 pinctrl-single,pins = <
282 0x618 (A_DELAY(489) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
283 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */
284 0x630 (A_DELAY(374) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */
285 0x63c (A_DELAY(31) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */
286 0x648 (A_DELAY(56) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */
287 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
288 0x620 (A_DELAY(1355) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
289 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
290 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
291 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
292 0x638 (A_DELAY(0) | G_DELAY(4)) /* CFG_MMC1_DAT0_OUT */
293 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
294 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
295 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
296 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
297 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
298 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
299 >;
300 };
301
302 /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
303 mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
304 pinctrl-single,pins = <
305 0x620 (A_DELAY(892) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
306 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
307 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
308 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
309 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
310 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
311 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
312 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
313 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
314 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
315 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
316 >;
317 };
318
319 /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
320 mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
321 pinctrl-single,pins = <
322 0x190 (A_DELAY(384) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
323 0x194 (A_DELAY(0) | G_DELAY(174)) /* CFG_GPMC_A19_OUT */
324 0x1a8 (A_DELAY(410) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
325 0x1ac (A_DELAY(85) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
326 0x1b4 (A_DELAY(468) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
327 0x1b8 (A_DELAY(139) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
328 0x1c0 (A_DELAY(676) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
329 0x1c4 (A_DELAY(69) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
330 0x1d0 (A_DELAY(1062) | G_DELAY(154)) /* CFG_GPMC_A23_OUT */
331 0x1d8 (A_DELAY(640) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
332 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
333 0x1e4 (A_DELAY(356) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
334 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
335 0x1f0 (A_DELAY(579) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
336 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
337 0x1fc (A_DELAY(435) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
338 0x200 (A_DELAY(36) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
339 0x364 (A_DELAY(759) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
340 0x368 (A_DELAY(72) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
341 >;
342 };
343
344 /* Corresponds to MMC3_MANUAL1 in datamanual */
345 mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
346 pinctrl-single,pins = <
347 0x678 (A_DELAY(0) | G_DELAY(386)) /* CFG_MMC3_CLK_IN */
348 0x680 (A_DELAY(605) | G_DELAY(0)) /* CFG_MMC3_CLK_OUT */
349 0x684 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_IN */
350 0x688 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OEN */
351 0x68c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OUT */
352 0x690 (A_DELAY(171) | G_DELAY(0)) /* CFG_MMC3_DAT0_IN */
353 0x694 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OEN */
354 0x698 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OUT */
355 0x69c (A_DELAY(221) | G_DELAY(0)) /* CFG_MMC3_DAT1_IN */
356 0x6a0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OEN */
357 0x6a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OUT */
358 0x6a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_IN */
359 0x6ac (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OEN */
360 0x6b0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OUT */
361 0x6b4 (A_DELAY(474) | G_DELAY(0)) /* CFG_MMC3_DAT3_IN */
362 0x6b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OEN */
363 0x6bc (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OUT */
364 >;
365 };
366
367 /* Corresponds to MMC3_MANUAL2 in datamanual */
368 mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
369 pinctrl-single,pins = <
370 0x678 (A_DELAY(852) | G_DELAY(0)) /* CFG_MMC3_CLK_IN */
371 0x680 (A_DELAY(94) | G_DELAY(0)) /* CFG_MMC3_CLK_OUT */
372 0x684 (A_DELAY(122) | G_DELAY(0)) /* CFG_MMC3_CMD_IN */
373 0x688 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OEN */
374 0x68c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OUT */
375 0x690 (A_DELAY(91) | G_DELAY(0)) /* CFG_MMC3_DAT0_IN */
376 0x694 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OEN */
377 0x698 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OUT */
378 0x69c (A_DELAY(57) | G_DELAY(0)) /* CFG_MMC3_DAT1_IN */
379 0x6a0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OEN */
380 0x6a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OUT */
381 0x6a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_IN */
382 0x6ac (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OEN */
383 0x6b0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OUT */
384 0x6b4 (A_DELAY(375) | G_DELAY(0)) /* CFG_MMC3_DAT3_IN */
385 0x6b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OEN */
386 0x6bc (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OUT */
387 >;
388 };
389
390 /* Corresponds to MMC4_MANUAL1 in datamanual */
391 mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
392 pinctrl-single,pins = <
393 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
394 0x848 (A_DELAY(1147) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
395 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
396 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
397 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
398 0x870 (A_DELAY(2165) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
399 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
400 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
401 0x87c (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_RTSN_IN */
402 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
403 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
404 0x888 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_RXD_IN */
405 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
406 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
407 0x894 (A_DELAY(2172) | G_DELAY(44)) /* CFG_UART2_TXD_IN */
408 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
409 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
410 >;
411 };
412
413 /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
414 mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
415 pinctrl-single,pins = <
416 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
417 0x848 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
418 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
419 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
420 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
421 0x870 (A_DELAY(785) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
422 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
423 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
424 0x87c (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
425 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
426 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
427 0x888 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
428 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
429 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
430 0x894 (A_DELAY(835) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
431 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
432 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
433 >;
434 };
435};
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
new file mode 100644
index 000000000000..6edc1d40fe19
--- /dev/null
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra74x.dtsi"
10
11/ {
12 compatible = "ti,dra762", "ti,dra7";
13
14 ocp {
15 cal: cal@4845b000 {
16 compatible = "ti,dra72-cal";
17 ti,hwmods = "cal";
18 reg = <0x489B0000 0x400>,
19 <0x489B0800 0x40>,
20 <0x489B0900 0x40>,
21 <0x4A0026DC 0x4>;
22 reg-names = "cal_top",
23 "cal_rx_core0",
24 "cal_rx_core1",
25 "camerrx_control";
26 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 status = "disabled";
30
31 ports {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 csi2_0: port@0 {
36 reg = <0>;
37 };
38 csi2_1: port@1 {
39 reg = <1>;
40 };
41 };
42 };
43 };
44};
45
46/* MCAN interrupts are hard-wired to irqs 67, 68 */
47&crossbar_mpu {
48 ti,irqs-skip = <10 67 68 133 139 140>;
49};
50
51&cpu0_opp_table {
52 opp_plus@1800000000 {
53 opp-hz = /bits/ 64 <1800000000>;
54 opp-microvolt = <1250000 950000 1250000>;
55 opp-supported-hw = <0xFF 0x08>;
56 };
57};
58
59&oppdm_mpu {
60 ti,efuse-settings = <
61 /* uV offset */
62 1060000 0x0
63 1160000 0x4
64 1210000 0x8
65 1250000 0xC
66 >;
67};
68
69&abb_mpu {
70 ti,abb_info = <
71 /*uV ABB efuse rbb_m fbb_m vset_m*/
72 1060000 0 0x0 0 0x02000000 0x01F00000
73 1160000 0 0x4 0 0x02000000 0x01F00000
74 1210000 0 0x8 0 0x02000000 0x01F00000
75 1250000 0 0xC 0 0x02000000 0x01F00000
76 >;
77};
78
79&mmc3 {
80 max-frequency = <96000000>;
81};
diff --git a/arch/arm/boot/dts/dra7x-evm-fpd-auo-g101evn01.0.dtsi b/arch/arm/boot/dts/dra7x-evm-fpd-auo-g101evn01.0.dtsi
new file mode 100644
index 000000000000..c928be92c1ac
--- /dev/null
+++ b/arch/arm/boot/dts/dra7x-evm-fpd-auo-g101evn01.0.dtsi
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/ {
10 backlight {
11 compatible = "led-backlight";
12 leds = <&backlight_led>;
13 brightness-levels = <0 2 38 74 110 146 182 218 255>;
14 default-brightness-level = <8>;
15
16 enable-gpios = <&pcf_display_board 0 GPIO_ACTIVE_LOW>;
17 };
18
19 lcd_fpd: display {
20 compatible = "auo,g101evn01.0", "panel-dpi";
21
22 label = "lcd_fpd";
23 status = "disabled";
24
25 panel-timing {
26 clock-frequency = <68930000>;
27 hactive = <1280>;
28 vactive = <800>;
29
30 hfront-porch = <48>;
31 hsync-len = <32>;
32 hback-porch = <48>;
33
34 vfront-porch = <4>;
35 vsync-len = <4>;
36 vback-porch = <8>;
37
38 hsync-active = <0>;
39 vsync-active = <0>;
40 de-active = <1>;
41 pixelclk-active = <1>;
42 };
43
44 port {
45 fpd_in: endpoint {
46 };
47 };
48 };
49};
50
51&disp_ser {
52
53 /*
54 * 0x2c - deserializer
55 * 0x40 - TLC59108
56 * 0x27 - PCF8575
57 * 0x57 - EEPROM
58 * 0x14 - Goodix Touch Controller
59 * 0x28 - RF430CL330H
60 */
61
62 disp_des: deserializer@2c {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 compatible = "ti,ds90ub924q";
66 reg = <0x2c>;
67 slave-mode;
68 };
69
70 /* TLC chip for LCD panel power and backlight */
71 fpd_disp: tlc59108@40 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "ti,tlc59108";
75 reg = <0x40>;
76
77 backlight_led: bl@2 {
78 label = "backlight";
79 reg = <0x2>;
80 };
81 };
82
83 pcf_display_board: gpio@27 {
84 compatible = "nxp,pcf8575";
85 reg = <0x27>;
86 gpio-controller;
87 #gpio-cells = <2>;
88 };
89
90 touchscreen: goodix-gt9271@14 {
91 status = "okay";
92 compatible = "goodix,gt9271";
93 reg = <0x14>;
94
95 touchscreen-size-x = <1280>;
96 touchscreen-size-y = <800>;
97 touchscreen-inverted-y;
98
99 /* Reset gpio line is inverted before going to touch panel */
100 reset-gpios = <&pcf_display_board 5 GPIO_ACTIVE_LOW>;
101 irq-gpios = <&pcf_display_board 6 GPIO_ACTIVE_HIGH>;
102 };
103
104 /* Below two slaves on the I2C bus are not yet defined */
105 /* ID EEPROM 0x57 */
106 /* RF430CL330H 0x28 */
107};
diff --git a/arch/arm/boot/dts/dra7x-evm-fpd-lg.dtsi b/arch/arm/boot/dts/dra7x-evm-fpd-lg.dtsi
new file mode 100644
index 000000000000..b4760b4efdad
--- /dev/null
+++ b/arch/arm/boot/dts/dra7x-evm-fpd-lg.dtsi
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10
11
12/ {
13 lcd_fpd: display_fpd {
14 /*
15 * This is not really a dpi panel, but panel-dpi driver
16 * works as dummy panel driver.
17 */
18 compatible = "lg,lp101wx2", "panel-dpi";
19
20 label = "lcd_fpd";
21 status = "disabled";
22
23 panel-timing {
24 clock-frequency = <69300404>;
25 hactive = <1280>;
26 vactive = <800>;
27
28 hfront-porch = <48>;
29 hback-porch = <44>;
30 hsync-len = <32>;
31
32 vfront-porch = <4>;
33 vback-porch = <7>;
34 vsync-len = <12>;
35
36 hsync-active = <0>;
37 vsync-active = <0>;
38 de-active = <1>;
39 pixelclk-active = <0>;
40 };
41
42 port {
43 fpd_in: endpoint {
44 };
45 };
46 };
47};
48
49&disp_ser {
50 disp_des: deserializer@2c {
51 compatible = "ti,ds90uh928q";
52 reg = <0x2c>;
53 slave-mode;
54 };
55 fpd_disp: tlc59108@1c {
56 compatible = "ti,tlc59108";
57 reg = <0x1c>;
58 };
59};
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
index 97939eef7b94..23268b7a474f 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi
@@ -12,7 +12,6 @@
12 aliases { 12 aliases {
13 display0 = &tlc59108; 13 display0 = &tlc59108;
14 display1 = &hdmi0; 14 display1 = &hdmi0;
15 display2 = &fpd_disp;
16 }; 15 };
17 16
18 backlight { 17 backlight {
@@ -51,7 +50,7 @@
51 hsync-active = <0>; 50 hsync-active = <0>;
52 vsync-active = <0>; 51 vsync-active = <0>;
53 de-active = <1>; 52 de-active = <1>;
54 pixelclk-active = <1>; 53 pixelclk-active = <0>;
55 }; 54 };
56 55
57 port { 56 port {
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
index 219e4f953797..7dc9c986a73a 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi
@@ -10,7 +10,6 @@
10 aliases { 10 aliases {
11 display0 = &lcd; 11 display0 = &lcd;
12 display1 = &hdmi0; 12 display1 = &hdmi0;
13 display2 = &fpd_disp;
14 }; 13 };
15 14
16 lcd_bl: backlight { 15 lcd_bl: backlight {
diff --git a/arch/arm/boot/dts/dra7xx-jamr3.dtsi b/arch/arm/boot/dts/dra7xx-jamr3.dtsi
index 994c6e735789..894e97f93775 100644
--- a/arch/arm/boot/dts/dra7xx-jamr3.dtsi
+++ b/arch/arm/boot/dts/dra7xx-jamr3.dtsi
@@ -47,7 +47,17 @@
47 <&hwspinlock 6>, 47 <&hwspinlock 6>,
48 <&hwspinlock 7>, 48 <&hwspinlock 7>,
49 <&hwspinlock 8>, 49 <&hwspinlock 8>,
50 <&hwspinlock 9>; 50 <&hwspinlock 9>,
51 <&hwspinlock 10>,
52 <&hwspinlock 11>,
53 <&hwspinlock 12>,
54 <&hwspinlock 13>,
55 <&hwspinlock 14>,
56 <&hwspinlock 15>,
57 <&hwspinlock 16>,
58 <&hwspinlock 17>,
59 <&hwspinlock 18>,
60 <&hwspinlock 19>;
51 }; 61 };
52 62
53 sr0 { 63 sr0 {
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 4b0ec0703825..8ca9217204a0 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -30,7 +30,7 @@
30 /* kHz uV */ 30 /* kHz uV */
31 996000 1250000 31 996000 1250000
32 792000 1175000 32 792000 1175000
33 396000 1075000 33 396000 1150000
34 >; 34 >;
35 fsl,soc-operating-points = < 35 fsl,soc-operating-points = <
36 /* ARM kHz SOC-PU uV */ 36 /* ARM kHz SOC-PU uV */
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 5f5e0f3d5b64..27cd4abfc74d 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -697,6 +697,8 @@
697 vmmc_aux-supply = <&vsim>; 697 vmmc_aux-supply = <&vsim>;
698 bus-width = <8>; 698 bus-width = <8>;
699 non-removable; 699 non-removable;
700 no-sdio;
701 no-sd;
700}; 702};
701 703
702&mmc3 { 704&mmc3 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index f648ec2dd5a6..304bcf9b630e 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -1022,6 +1022,7 @@
1022 phy-names = "sata-phy"; 1022 phy-names = "sata-phy";
1023 clocks = <&sata_ref_clk>; 1023 clocks = <&sata_ref_clk>;
1024 ti,hwmods = "sata"; 1024 ti,hwmods = "sata";
1025 ports-implemented = <0x1>;
1025 }; 1026 };
1026 1027
1027 dss: dss@58000000 { 1028 dss: dss@58000000 {
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 4dfca8fc49b3..1bc61ece2589 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -856,6 +856,13 @@
856 compatible = "atmel,at91sam9260-usart"; 856 compatible = "atmel,at91sam9260-usart";
857 reg = <0xf801c000 0x100>; 857 reg = <0xf801c000 0x100>;
858 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 858 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
859 dmas = <&dma0
860 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
861 AT91_XDMAC_DT_PERID(35))>,
862 <&dma0
863 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
864 AT91_XDMAC_DT_PERID(36))>;
865 dma-names = "tx", "rx";
859 clocks = <&uart0_clk>; 866 clocks = <&uart0_clk>;
860 clock-names = "usart"; 867 clock-names = "usart";
861 status = "disabled"; 868 status = "disabled";
@@ -865,6 +872,13 @@
865 compatible = "atmel,at91sam9260-usart"; 872 compatible = "atmel,at91sam9260-usart";
866 reg = <0xf8020000 0x100>; 873 reg = <0xf8020000 0x100>;
867 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 874 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
875 dmas = <&dma0
876 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
877 AT91_XDMAC_DT_PERID(37))>,
878 <&dma0
879 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
880 AT91_XDMAC_DT_PERID(38))>;
881 dma-names = "tx", "rx";
868 clocks = <&uart1_clk>; 882 clocks = <&uart1_clk>;
869 clock-names = "usart"; 883 clock-names = "usart";
870 status = "disabled"; 884 status = "disabled";
@@ -874,6 +888,13 @@
874 compatible = "atmel,at91sam9260-usart"; 888 compatible = "atmel,at91sam9260-usart";
875 reg = <0xf8024000 0x100>; 889 reg = <0xf8024000 0x100>;
876 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 890 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
891 dmas = <&dma0
892 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
893 AT91_XDMAC_DT_PERID(39))>,
894 <&dma0
895 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
896 AT91_XDMAC_DT_PERID(40))>;
897 dma-names = "tx", "rx";
877 clocks = <&uart2_clk>; 898 clocks = <&uart2_clk>;
878 clock-names = "usart"; 899 clock-names = "usart";
879 status = "disabled"; 900 status = "disabled";
@@ -985,6 +1006,13 @@
985 compatible = "atmel,at91sam9260-usart"; 1006 compatible = "atmel,at91sam9260-usart";
986 reg = <0xfc008000 0x100>; 1007 reg = <0xfc008000 0x100>;
987 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 1008 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1009 dmas = <&dma0
1010 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1011 AT91_XDMAC_DT_PERID(41))>,
1012 <&dma0
1013 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1014 AT91_XDMAC_DT_PERID(42))>;
1015 dma-names = "tx", "rx";
988 clocks = <&uart3_clk>; 1016 clocks = <&uart3_clk>;
989 clock-names = "usart"; 1017 clock-names = "usart";
990 status = "disabled"; 1018 status = "disabled";
@@ -993,6 +1021,13 @@
993 uart4: serial@fc00c000 { 1021 uart4: serial@fc00c000 {
994 compatible = "atmel,at91sam9260-usart"; 1022 compatible = "atmel,at91sam9260-usart";
995 reg = <0xfc00c000 0x100>; 1023 reg = <0xfc00c000 0x100>;
1024 dmas = <&dma0
1025 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1026 AT91_XDMAC_DT_PERID(43))>,
1027 <&dma0
1028 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1029 AT91_XDMAC_DT_PERID(44))>;
1030 dma-names = "tx", "rx";
996 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 1031 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
997 clocks = <&uart4_clk>; 1032 clocks = <&uart4_clk>;
998 clock-names = "usart"; 1033 clock-names = "usart";
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ed7e1009326c..d9ee0fd817e9 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -565,6 +565,7 @@
565 regulator-name = "+3VS,vdd_pnl"; 565 regulator-name = "+3VS,vdd_pnl";
566 regulator-min-microvolt = <3300000>; 566 regulator-min-microvolt = <3300000>;
567 regulator-max-microvolt = <3300000>; 567 regulator-max-microvolt = <3300000>;
568 regulator-boot-on;
568 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; 569 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
569 enable-active-high; 570 enable-active-high;
570 }; 571 };
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f3142369f594..01116ee1284b 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -87,9 +87,9 @@ CONFIG_IPV6_TUNNEL=m
87CONFIG_NETFILTER=y 87CONFIG_NETFILTER=y
88CONFIG_NF_CONNTRACK=m 88CONFIG_NF_CONNTRACK=m
89CONFIG_NF_CONNTRACK_EVENTS=y 89CONFIG_NF_CONNTRACK_EVENTS=y
90CONFIG_NF_CT_PROTO_DCCP=m 90CONFIG_NF_CT_PROTO_DCCP=y
91CONFIG_NF_CT_PROTO_SCTP=m 91CONFIG_NF_CT_PROTO_SCTP=y
92CONFIG_NF_CT_PROTO_UDPLITE=m 92CONFIG_NF_CT_PROTO_UDPLITE=y
93CONFIG_NF_CONNTRACK_AMANDA=m 93CONFIG_NF_CONNTRACK_AMANDA=m
94CONFIG_NF_CONNTRACK_FTP=m 94CONFIG_NF_CONNTRACK_FTP=m
95CONFIG_NF_CONNTRACK_H323=m 95CONFIG_NF_CONNTRACK_H323=m
diff --git a/arch/arm/crypto/aes-ce-glue.c b/arch/arm/crypto/aes-ce-glue.c
index 679c589c4828..1f7b98e1a00d 100644
--- a/arch/arm/crypto/aes-ce-glue.c
+++ b/arch/arm/crypto/aes-ce-glue.c
@@ -369,7 +369,7 @@ static struct crypto_alg aes_algs[] = { {
369 .cra_blkcipher = { 369 .cra_blkcipher = {
370 .min_keysize = AES_MIN_KEY_SIZE, 370 .min_keysize = AES_MIN_KEY_SIZE,
371 .max_keysize = AES_MAX_KEY_SIZE, 371 .max_keysize = AES_MAX_KEY_SIZE,
372 .ivsize = AES_BLOCK_SIZE, 372 .ivsize = 0,
373 .setkey = ce_aes_setkey, 373 .setkey = ce_aes_setkey,
374 .encrypt = ecb_encrypt, 374 .encrypt = ecb_encrypt,
375 .decrypt = ecb_decrypt, 375 .decrypt = ecb_decrypt,
@@ -446,7 +446,7 @@ static struct crypto_alg aes_algs[] = { {
446 .cra_ablkcipher = { 446 .cra_ablkcipher = {
447 .min_keysize = AES_MIN_KEY_SIZE, 447 .min_keysize = AES_MIN_KEY_SIZE,
448 .max_keysize = AES_MAX_KEY_SIZE, 448 .max_keysize = AES_MAX_KEY_SIZE,
449 .ivsize = AES_BLOCK_SIZE, 449 .ivsize = 0,
450 .setkey = ablk_set_key, 450 .setkey = ablk_set_key,
451 .encrypt = ablk_encrypt, 451 .encrypt = ablk_encrypt,
452 .decrypt = ablk_decrypt, 452 .decrypt = ablk_decrypt,
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index d2315ffd8f12..f13ae153fb24 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -112,12 +112,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
112#define CORE_DUMP_USE_REGSET 112#define CORE_DUMP_USE_REGSET
113#define ELF_EXEC_PAGESIZE 4096 113#define ELF_EXEC_PAGESIZE 4096
114 114
115/* This is the location that an ET_DYN program is loaded if exec'ed. Typical 115/* This is the base location for PIE (ET_DYN with INTERP) loads. */
116 use of this is to invoke "./ld.so someprog" to test out a new version of 116#define ELF_ET_DYN_BASE 0x400000UL
117 the loader. We need to make sure that it is out of the way of the program
118 that it will "exec", and that there is sufficient room for the brk. */
119
120#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
121 117
122/* When the program starts, a1 contains a pointer to a function to be 118/* When the program starts, a1 contains a pointer to a function to be
123 registered with atexit, as per the SVR4 ABI. A value of 0 means we 119 registered with atexit, as per the SVR4 ABI. A value of 0 means we
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index bfe2a2f5a644..22b73112b75f 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -54,6 +54,24 @@ static inline void *return_address(unsigned int level)
54 54
55#define ftrace_return_address(n) return_address(n) 55#define ftrace_return_address(n) return_address(n)
56 56
57#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
58
59static inline bool arch_syscall_match_sym_name(const char *sym,
60 const char *name)
61{
62 if (!strcmp(sym, "sys_mmap2"))
63 sym = "sys_mmap_pgoff";
64 else if (!strcmp(sym, "sys_statfs64_wrapper"))
65 sym = "sys_statfs64";
66 else if (!strcmp(sym, "sys_fstatfs64_wrapper"))
67 sym = "sys_fstatfs64";
68 else if (!strcmp(sym, "sys_arm_fadvise64_64"))
69 sym = "sys_fadvise64_64";
70
71 /* Ignore case since sym may start with "SyS" instead of "sys" */
72 return !strcasecmp(sym, name);
73}
74
57#endif /* ifndef __ASSEMBLY__ */ 75#endif /* ifndef __ASSEMBLY__ */
58 76
59#endif /* _ASM_ARM_FTRACE */ 77#endif /* _ASM_ARM_FTRACE */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index c7ba9a42e857..ebf866a3a8c8 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -205,18 +205,12 @@ static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
205 * and iterate over the range. 205 * and iterate over the range.
206 */ 206 */
207 207
208 bool need_flush = !vcpu_has_cache_enabled(vcpu) || ipa_uncached;
209
210 VM_BUG_ON(size & ~PAGE_MASK); 208 VM_BUG_ON(size & ~PAGE_MASK);
211 209
212 if (!need_flush && !icache_is_pipt())
213 goto vipt_cache;
214
215 while (size) { 210 while (size) {
216 void *va = kmap_atomic_pfn(pfn); 211 void *va = kmap_atomic_pfn(pfn);
217 212
218 if (need_flush) 213 kvm_flush_dcache_to_poc(va, PAGE_SIZE);
219 kvm_flush_dcache_to_poc(va, PAGE_SIZE);
220 214
221 if (icache_is_pipt()) 215 if (icache_is_pipt())
222 __cpuc_coherent_user_range((unsigned long)va, 216 __cpuc_coherent_user_range((unsigned long)va,
@@ -228,7 +222,6 @@ static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
228 kunmap_atomic(va); 222 kunmap_atomic(va);
229 }