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authorRalf Baechle2013-04-22 10:57:54 -0500
committerGreg Kroah-Hartman2013-04-25 14:51:25 -0500
commit65dcded2f1e5582e8f0fe6ef315b2274270a6302 (patch)
tree7a369d65d9bc5d2d9b26deafb23b551e402e7739 /arch
parent7a5324f9edf0e920c99ed90872e1baeaf04acbc1 (diff)
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Revert "MIPS: page.h: Provide more readable definition for PAGE_MASK."
commit 3b5e50edaf500f392f4a372296afc0b99ffa7e70 upstream. This reverts commit c17a6554782ad531f4713b33fd6339ba67ef6391. Manuel Lauss writes: lmo commit c17a6554 (MIPS: page.h: Provide more readable definition for PAGE_MASK) apparently breaks ioremap of 36-bit addresses on my Alchemy systems (PCI and PCMCIA) The reason is that in arch/mips/mm/ioremap.c line 157 (phys_addr &= PAGE_MASK) bits 32-35 are cut off. Seems the new PAGE_MASK is explicitly 32bit, or one could make it signed instead of unsigned long. From: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/page.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index dbaec94046da..21bff32ca854 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,7 +31,7 @@
31#define PAGE_SHIFT 16 31#define PAGE_SHIFT 16
32#endif 32#endif
33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
34#define PAGE_MASK (~(PAGE_SIZE - 1)) 34#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
35 35
36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)