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authorJacob Keller2013-03-02 01:51:42 -0600
committerGreg Kroah-Hartman2013-05-07 22:08:24 -0500
commitc7e1e426d0b6bc1ab07779615c81faf6176901e5 (patch)
treefb0581a4903d773f43a0ca6169e14992645f279a /drivers
parent870ef91261887958df8b91a14386bd9fc4485325 (diff)
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ixgbe: fix EICR write in ixgbe_msix_other
commit d87d830720a1446403ed38bfc2da268be0d356d1 upstream. Previously, the ixgbe_msix_other was writing the full 32bits of the set interrupts, instead of only the ones which the ixgbe_msix_other is handling. This resulted in a loss of performance when the X540's PPS feature is enabled due to sometimes clearing queue interrupts which resulted in the driver not getting the interrupt for cleaning the q_vector rings often enough. The fix is to simply mask the lower 16bits off so that this handler does not write them in the EICR, which causes them to remain high and be properly handled by the clean_rings interrupt routine as normal. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_main.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 0d03d387c332..911956e53281 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -2407,6 +2407,16 @@ static irqreturn_t ixgbe_msix_other(int irq, void *data)
2407 * with the write to EICR. 2407 * with the write to EICR.
2408 */ 2408 */
2409 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2409 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2410
2411 /* The lower 16bits of the EICR register are for the queue interrupts
2412 * which should be masked here in order to not accidently clear them if
2413 * the bits are high when ixgbe_msix_other is called. There is a race
2414 * condition otherwise which results in possible performance loss
2415 * especially if the ixgbe_msix_other interrupt is triggering
2416 * consistently (as it would when PPS is turned on for the X540 device)
2417 */
2418 eicr &= 0xFFFF0000;
2419
2410 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2420 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2411 2421
2412 if (eicr & IXGBE_EICR_LSC) 2422 if (eicr & IXGBE_EICR_LSC)