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-rw-r--r--android/configs/android-recommended.cfg2
-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/dra7-evm-early-video.dts21
-rwxr-xr-xarch/arm/boot/dts/dra7-evm-robust-rvc.dts220
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts2
-rw-r--r--arch/arm/boot/dts/dra7.dtsi4
-rw-r--r--arch/arm/boot/dts/dra71-evm-early-video.dts21
-rw-r--r--arch/arm/boot/dts/dra71-evm-robust-rvc.dts228
-rw-r--r--arch/arm/boot/dts/dra71-evm.dts4
-rw-r--r--arch/arm/boot/dts/dra72-evm-common.dtsi4
-rw-r--r--arch/arm/boot/dts/dra72-evm-robust-rvc.dts216
-rw-r--r--arch/arm/boot/dts/dra7x-evm-lcd-auo-g101evn01.0.dtsi1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c3
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c2
-rw-r--r--drivers/clk/clk.c9
-rw-r--r--drivers/gpio/gpio-omap.c160
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-dpi.c8
-rw-r--r--drivers/gpu/drm/omapdrm/dss/Kconfig6
-rw-r--r--drivers/gpu/drm/omapdrm/dss/core.c41
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c52
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dpi.c15
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.c23
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss_features.c9
-rw-r--r--drivers/gpu/drm/omapdrm/omap_crtc.c8
-rw-r--r--drivers/gpu/drm/omapdrm/omap_drv.h2
-rw-r--r--drivers/gpu/drm/omapdrm/omap_irq.c18
-rw-r--r--drivers/video/backlight/led_bl.c11
-rw-r--r--include/video/omapdss.h17
-rw-r--r--ti_config_fragments/audio_display.cfg1
29 files changed, 1079 insertions, 34 deletions
diff --git a/android/configs/android-recommended.cfg b/android/configs/android-recommended.cfg
index eecf8d80453a..6fd099015525 100644
--- a/android/configs/android-recommended.cfg
+++ b/android/configs/android-recommended.cfg
@@ -99,7 +99,7 @@ CONFIG_MD=y
99CONFIG_MEDIA_SUPPORT=y 99CONFIG_MEDIA_SUPPORT=y
100CONFIG_MEMORY_STATE_TIME=y 100CONFIG_MEMORY_STATE_TIME=y
101CONFIG_MSDOS_FS=y 101CONFIG_MSDOS_FS=y
102CONFIG_PANIC_TIMEOUT=5 102CONFIG_PANIC_TIMEOUT=0
103CONFIG_PANTHERLORD_FF=y 103CONFIG_PANTHERLORD_FF=y
104CONFIG_PERF_EVENTS=y 104CONFIG_PERF_EVENTS=y
105CONFIG_PM_DEBUG=y 105CONFIG_PM_DEBUG=y
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c57745523e4..4e037366a62f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -502,6 +502,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
502 dra7-evm-lcd-osd-late-attach.dtb \ 502 dra7-evm-lcd-osd-late-attach.dtb \
503 dra7-evm-fpd-auo-g101evn01.0.dtb \ 503 dra7-evm-fpd-auo-g101evn01.0.dtb \
504 dra7-evm-vision.dtb \ 504 dra7-evm-vision.dtb \
505 dra7-evm-robust-rvc.dtb \
506 dra7-evm-early-video.dtb \
505 am57xx-beagle-x15.dtb \ 507 am57xx-beagle-x15.dtb \
506 am57xx-beagle-x15-revb1.dtb \ 508 am57xx-beagle-x15-revb1.dtb \
507 am571x-idk.dtb \ 509 am571x-idk.dtb \
@@ -521,8 +523,11 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
521 dra72-evm-revc-lcd-osd101t2045.dtb \ 523 dra72-evm-revc-lcd-osd101t2045.dtb \
522 dra72-evm-revc-lcd-osd101t2587.dtb \ 524 dra72-evm-revc-lcd-osd101t2587.dtb \
523 dra72-evm-vision.dtb \ 525 dra72-evm-vision.dtb \
526 dra72-evm-robust-rvc.dtb \
524 dra71-evm.dtb \ 527 dra71-evm.dtb \
525 dra71-evm-lcd-auo-g101evn01.0.dtb \ 528 dra71-evm-lcd-auo-g101evn01.0.dtb \
529 dra71-evm-robust-rvc.dtb \
530 dra71-evm-early-video.dtb \
526 dra76-evm.dtb \ 531 dra76-evm.dtb \
527 dra76-evm-fpd-auo-g101evn01.0.dtb 532 dra76-evm-fpd-auo-g101evn01.0.dtb
528dtb-$(CONFIG_ARCH_ORION5X) += \ 533dtb-$(CONFIG_ARCH_ORION5X) += \
diff --git a/arch/arm/boot/dts/dra7-evm-early-video.dts b/arch/arm/boot/dts/dra7-evm-early-video.dts
new file mode 100644
index 000000000000..155f0dcb7e19
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm-early-video.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra7-evm-robust-rvc.dts"
10
11&reserved_mem{
12 earlyvid_1: earlyvid1@0xA2400000 {
13 reg = <0x0 0xA2400000 0x0 0x600000>;
14 status = "okay";
15 };
16
17 earlyvid_2: earlyvid2@0xA3000000 {
18 reg = <0x0 0xA3000000 0x0 0x100000>;
19 status = "okay";
20 };
21};
diff --git a/arch/arm/boot/dts/dra7-evm-robust-rvc.dts b/arch/arm/boot/dts/dra7-evm-robust-rvc.dts
new file mode 100755
index 000000000000..12235618e3a1
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm-robust-rvc.dts
@@ -0,0 +1,220 @@
1/*
2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra7-evm-lcd-lg.dts"
10
11/*
12 * Reserving memory used by Vision SDK configured at
13 * \vision_sdk\build\tda2xx\mem_segment_definition_1024mb_linux.xs
14 * Address 0x84000000 - 0x94000000 of size 0x10000000 for NDK_MEM and
15 * SR1_FRAME_BUFFER_MEM
16 * Address 0xA0000000 - 0xA2000000 of size 0x2000000 for SR0, REMOTE_LOG_MEM,
17 * LINK_STATS_MEM, SYSTEM_IPC_SHM_MEM, HDVPSS_DESC_MEM,
18 * TRACE_BUF, EXC_DATA, and PM_DATA
19 */
20&reserved_mem{
21 rvc_pool1: rvc1@0x84000000 {
22 reg = <0x0 0x84000000 0x0 0x10000000>;
23 status = "okay";
24 };
25
26 rvc_pool2: rvc2@0xA0000000 {
27 reg = <0x0 0xA0000000 0x0 0x2000000>;
28 status = "okay";
29 };
30};
31
32/*
33 * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
34 * Page Table Address for IPU1 0xbfc00000
35 * Page Table Address for IPU2 0xbfc08000
36 * Page Table Address for DSP1 0xbfc10000
37 * Page Table Address for DSP2 0xbfc18000
38 */
39&reserved_mem {
40 latea_pagetbl: late_pgtbl@bfc00000 {
41 reg = <0x0 0xbfc00000 0x0 0x100000>;
42 no-map;
43 status = "okay";
44 };
45};
46
47&ipu2_cma_pool {
48 reg = <0x0 0x94000000 0x0 0x5000000>;
49};
50
51&mbox_ipu2_ipc3x {
52 ti,no-reset-on-init;
53 ti,no-idle-on-init;
54};
55
56&mmu_ipu2 {
57 ti,late-attach;
58 ti,no-reset-on-init;
59 ti,no-idle-on-init;
60};
61
62&ipu2 {
63 ti,late-attach;
64 ti,no-reset-on-init;
65 ti,no-idle-on-init;
66};
67
68&dsp1 {
69 ti,late-attach;
70 ti,no-reset-on-init;
71 ti,no-idle-on-init;
72};
73
74&mmu0_dsp1 {
75 ti,late-attach;
76 ti,no-reset-on-init;
77 ti,no-idle-on-init;
78};
79
80&mmu1_dsp1 {
81 ti,late-attach;
82 ti,no-reset-on-init;
83 ti,no-idle-on-init;
84};
85
86&dsp2_cma_pool {
87 reg = <0x0 0x9f000000 0x0 0x1000000>;
88};
89
90&dsp1_cma_pool {
91 reg = <0x0 0x99000000 0x0 0x4000000>;
92};
93
94&mbox_dsp1_ipc3x {
95 ti,no-reset-on-init;
96 ti,no-idle-on-init;
97};
98
99&mailbox5 {
100 ti,no-reset-on-init;
101 ti,no-idle-on-init;
102};
103
104&mailbox6 {
105 ti,no-reset-on-init;
106 ti,no-idle-on-init;
107};
108
109&mailbox7 {
110 ti,no-reset-on-init;
111 ti,no-idle-on-init;
112};
113
114&vip1 {
115 status = "disabled";
116 ti,no-reset-on-init;
117 ti,no-idle-on-init;
118};
119
120&vin1a {
121 status = "disabled";
122};
123
124&vpe{
125 status = "disabled";
126 ti,no-reset-on-init;
127 ti,no-idle-on-init;
128};
129
130&pcf_hdmi {
131 lines-initial-states = <0xffe3>;
132};
133
134&ov_10633 {
135 status = "disabled";
136};
137
138&dispc{
139 ti,no-reset-on-init;
140 ti,no-idle-on-init;
141};
142
143&dss {
144 /delete-property/ ti,enable-opt-clks-on-reset;
145 ti,no-reset-on-init;
146 ti,no-idle-on-init;
147 is_shared=<1>;
148};
149
150&timer3{
151 ti,late-attach;
152 ti,no-reset-on-init;
153 ti,no-idle-on-init;
154};
155
156&timer4{
157 ti,late-attach;
158 ti,no-reset-on-init;
159 ti,no-idle-on-init;
160};
161
162&timer5{
163 ti,late-attach;
164 ti,no-reset-on-init;
165 ti,no-idle-on-init;
166};
167
168&timer6{
169 ti,late-attach;
170 ti,no-reset-on-init;
171 ti,no-idle-on-init;
172};
173
174&timer9{
175 ti,late-attach;
176 ti,no-reset-on-init;
177 ti,no-idle-on-init;
178};
179
180&timer10{
181 ti,late-attach;
182 ti,no-reset-on-init;
183 ti,no-idle-on-init;
184};
185
186&timer11{
187 ti,late-attach;
188 ti,no-reset-on-init;
189 ti,no-idle-on-init;
190};
191
192&tvp_5158 {
193 status = "disabled";
194};
195
196/* With RVC, since IPU2 CMEM is 80MB
197 * from 0x94000000 - 0x99000000
198 * cmem_radio needs to move from
199 * 0x95400000 to 0xA2000000 for radio to work with RVC.
200 */
201
202&cmem_radio {
203 reg = <0x0 0xA2000000 0x0 0x400000>;
204};
205
206
207/* Set the default value of the GPIO to be
208 * high instead of default low. Otherwise, the LCD
209 * backlight briefly turns off and turns on
210 * again.
211 */
212&lcd {
213 gpio-init-val=<7>;
214};
215
216/ {
217 backlight {
218 gpio-init-val=<7>;
219 };
220};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index aee34b6d45c1..4a8697306e7a 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -828,7 +828,7 @@ i2c_p3_exp: &i2c2 {
828 }; 828 };
829 }; 829 };
830 830
831 ov10633@37 { 831 ov_10633: ov10633@37 {
832 compatible = "ovti,ov10633"; 832 compatible = "ovti,ov10633";
833 reg = <0x37>; 833 reg = <0x37>;
834 834
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f9b778bb6a13..43316d454d41 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -2116,7 +2116,7 @@
2116 #size-cells = <1>; 2116 #size-cells = <1>;
2117 ranges; 2117 ranges;
2118 2118
2119 dispc@58001000 { 2119 dispc: dispc@58001000 {
2120 compatible = "ti,dra7-dispc"; 2120 compatible = "ti,dra7-dispc";
2121 reg = <0x58001000 0x1000>; 2121 reg = <0x58001000 0x1000>;
2122 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 2122 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -2144,7 +2144,7 @@
2144 }; 2144 };
2145 }; 2145 };
2146 2146
2147 vpe { 2147 vpe: vpe {
2148 compatible = "ti,vpe"; 2148 compatible = "ti,vpe";
2149 ti,hwmods = "vpe"; 2149 ti,hwmods = "vpe";
2150 clocks = <&dpll_core_h23x2_ck>; 2150 clocks = <&dpll_core_h23x2_ck>;
diff --git a/arch/arm/boot/dts/dra71-evm-early-video.dts b/arch/arm/boot/dts/dra71-evm-early-video.dts
new file mode 100644
index 000000000000..48ae5047116c
--- /dev/null
+++ b/arch/arm/boot/dts/dra71-evm-early-video.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra71-evm-robust-rvc.dts"
10
11&reserved_mem{
12 earlyvid_1: earlyvid1@0xA2400000 {
13 reg = <0x0 0xA2400000 0x0 0x600000>;
14 status = "okay";
15 };
16
17 earlyvid_2: earlyvid2@0xA3000000 {
18 reg = <0x0 0xA3000000 0x0 0x100000>;
19 status = "okay";
20 };
21};
diff --git a/arch/arm/boot/dts/dra71-evm-robust-rvc.dts b/arch/arm/boot/dts/dra71-evm-robust-rvc.dts
new file mode 100644
index 000000000000..312649f7dc2a
--- /dev/null
+++ b/arch/arm/boot/dts/dra71-evm-robust-rvc.dts
@@ -0,0 +1,228 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra71-evm-lcd-auo-g101evn01.0.dts"
10
11/*
12 * Reserving memory used by Vision SDK configured at
13 * \vision_sdk\build\tda2xx\mem_segment_definition_1024mb_linux.xs
14 * Address 0x84000000 - 0x94000000 of size 0x10000000 for NDK_MEM and
15 * SR1_FRAME_BUFFER_MEM
16 * Address 0xA0000000 - 0xA2000000 of size 0x2000000 for SR0, REMOTE_LOG_MEM,
17 * LINK_STATS_MEM, SYSTEM_IPC_SHM_MEM, HDVPSS_DESC_MEM,
18 * TRACE_BUF, EXC_DATA, and PM_DATA
19 */
20&reserved_mem{
21 rvc_pool1: rvc1@0x84000000 {
22 reg = <0x0 0x84000000 0x0 0x10000000>;
23 status = "okay";
24 };
25
26 rvc_pool2: rvc2@0xA0000000 {
27 reg = <0x0 0xA0000000 0x0 0x2000000>;
28 status = "okay";
29 };
30};
31
32/*
33 * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
34 * Page Table Address for IPU1 0xbfc00000
35 * Page Table Address for IPU2 0xbfc08000
36 * Page Table Address for DSP1 0xbfc10000
37 * Page Table Address for DSP2 0xbfc18000
38 */
39&reserved_mem {
40 latea_pagetbl: late_pgtbl@bfc00000 {
41 reg = <0x0 0xbfc00000 0x0 0x100000>;
42 no-map;
43 status = "okay";
44 };
45};
46
47&ipu2_cma_pool {
48 reg = <0x0 0x94000000 0x0 0x5000000>;
49};
50
51&mbox_ipu2_ipc3x {
52 ti,no-reset-on-init;
53 ti,no-idle-on-init;
54};
55
56&mmu_ipu2 {
57 ti,late-attach;
58 ti,no-reset-on-init;
59 ti,no-idle-on-init;
60};
61
62&ipu2 {
63 ti,late-attach;
64 ti,no-reset-on-init;
65 ti,no-idle-on-init;
66};
67
68&dsp1 {
69 ti,late-attach;
70 ti,no-reset-on-init;
71 ti,no-idle-on-init;
72};
73
74&mmu0_dsp1 {
75 ti,late-attach;
76 ti,no-reset-on-init;
77 ti,no-idle-on-init;
78};
79
80&mmu1_dsp1 {
81 ti,late-attach;
82 ti,no-reset-on-init;
83 ti,no-idle-on-init;
84};
85
86&dsp1_cma_pool {
87 reg = <0x0 0x99000000 0x0 0x4000000>;
88};
89
90&mbox_dsp1_ipc3x {
91 ti,no-reset-on-init;
92 ti,no-idle-on-init;
93};
94
95&mailbox5 {
96 ti,no-reset-on-init;
97 ti,no-idle-on-init;
98};
99
100&mailbox6 {
101 ti,no-reset-on-init;
102 ti,no-idle-on-init;
103};
104
105&mailbox7 {
106 ti,no-reset-on-init;
107 ti,no-idle-on-init;
108};
109
110&vip1 {
111 status = "disabled";
112 ti,no-reset-on-init;
113 ti,no-idle-on-init;
114};
115
116&vin2a {
117 status = "disabled";
118};
119
120&vpe{
121 status = "disabled";
122 ti,no-reset-on-init;
123 ti,no-idle-on-init;
124};
125
126&pcf_hdmi {
127 lines-initial-states = <0xffe3>;
128};
129
130&ov_10633 {
131 status = "disabled";
132};
133
134&dispc{
135 ti,no-reset-on-init;
136 ti,no-idle-on-init;
137};
138
139&dss {
140 ti,no-reset-on-init;
141 ti,no-idle-on-init;
142 is_shared=<1>;
143 skip_dss_initial=<0>;
144};
145
146&timer3{
147 ti,late-attach;
148 ti,no-reset-on-init;
149 ti,no-idle-on-init;
150};
151
152&timer4{
153 ti,late-attach;
154 ti,no-reset-on-init;
155 ti,no-idle-on-init;
156};
157
158&timer5{
159 ti,late-attach;
160 ti,no-reset-on-init;
161 ti,no-idle-on-init;
162};
163
164&timer6{
165 ti,late-attach;
166 ti,no-reset-on-init;
167 ti,no-idle-on-init;
168};
169
170&timer9{
171 ti,late-attach;
172 ti,no-reset-on-init;
173 ti,no-idle-on-init;
174};
175
176&timer10{
177 ti,late-attach;
178 ti,no-reset-on-init;
179 ti,no-idle-on-init;
180};
181
182&timer11{
183 ti,late-attach;
184 ti,no-reset-on-init;
185 ti,no-idle-on-init;
186};
187
188&tvp_5158 {
189 status = "disabled";
190};
191
192/* With RVC, since IPU2 CMEM is 80MB
193 * from 0x94000000 - 0x99000000
194 * cmem_radio needs to move from
195 * 0x95400000 to 0xA2000000 for radio to work with RVC.
196 */
197
198&cmem_radio {
199 reg = <0x0 0xA2000000 0x0 0x400000>;
200};
201
202
203/* Set the default value of the GPIO to be
204 * high instead of default low. Otherwise, the LCD
205 * backlight briefly turns off and turns on
206 * again.
207 */
208&lcd {
209 gpio-init-val=<7>;
210};
211
212/ {
213 backlight {
214 gpio-init-val=<7>;
215 };
216};
217
218&tpd12s015 {
219 status = "disabled";
220};
221
222&mac {
223 status = "disabled";
224};
225
226&gpio_csi2_adap {
227 status = "disabled";
228}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index 1a6cb83fddb8..d5207896b97f 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -385,7 +385,7 @@ i2c_p3_exp: &i2c5 {
385 status = "okay"; 385 status = "okay";
386 clock-frequency = <400000>; 386 clock-frequency = <400000>;
387 387
388 ov10633@37 { 388 ov_10633: ov10633@37 {
389 compatible = "ovti,ov10633"; 389 compatible = "ovti,ov10633";
390 reg = <0x37>; 390 reg = <0x37>;
391 391
@@ -464,6 +464,7 @@ video_in: &vin2a {
464 interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 464 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
465}; 465};
466 466
467#if 0
467&pcf_hdmi { 468&pcf_hdmi {
468 p0 { 469 p0 {
469 /* 470 /*
@@ -476,6 +477,7 @@ video_in: &vin2a {
476 line-name = "pm_oe_n"; 477 line-name = "pm_oe_n";
477 }; 478 };
478}; 479};
480#endif
479 481
480&mmc1 { 482&mmc1 {
481 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; 483 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 1896ef30f673..aa3b8abde63d 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -297,6 +297,7 @@ i2c_p3_exp: &i2c5 {
297 * VIN2_S0 driven high otherwise Ethernet stops working 297 * VIN2_S0 driven high otherwise Ethernet stops working
298 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 298 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
299 */ 299 */
300#if 0
300 lines-initial-states = <0x0f2b>; 301 lines-initial-states = <0x0f2b>;
301 302
302 p1 { 303 p1 {
@@ -306,9 +307,10 @@ i2c_p3_exp: &i2c5 {
306 output-low; 307 output-low;
307 line-name = "vin6_sel_s0"; 308 line-name = "vin6_sel_s0";
308 }; 309 };
310#endif
309 }; 311 };
310 312
311 ov10633@37 { 313 ov_10633: ov10633@37 {
312 compatible = "ovti,ov10633"; 314 compatible = "ovti,ov10633";
313 reg = <0x37>; 315 reg = <0x37>;
314 316
diff --git a/arch/arm/boot/dts/dra72-evm-robust-rvc.dts b/arch/arm/boot/dts/dra72-evm-robust-rvc.dts
new file mode 100644
index 000000000000..c482e90808f1
--- /dev/null
+++ b/arch/arm/boot/dts/dra72-evm-robust-rvc.dts
@@ -0,0 +1,216 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra72-evm-lcd-lg.dts"
10
11/*
12 * Reserving memory used by Vision SDK configured at
13 * \vision_sdk\build\tda2xx\mem_segment_definition_1024mb_linux.xs
14 * Address 0x84000000 - 0x94000000 of size 0x10000000 for NDK_MEM and
15 * SR1_FRAME_BUFFER_MEM
16 * Address 0xA0000000 - 0xA2000000 of size 0x2000000 for SR0, REMOTE_LOG_MEM,
17 * LINK_STATS_MEM, SYSTEM_IPC_SHM_MEM, HDVPSS_DESC_MEM,
18 * TRACE_BUF, EXC_DATA, and PM_DATA
19 */
20&reserved_mem{
21 rvc_pool1: rvc1@0x84000000 {
22 reg = <0x0 0x84000000 0x0 0x10000000>;
23 status = "okay";
24 };
25
26 rvc_pool2: rvc2@0xA0000000 {
27 reg = <0x0 0xA0000000 0x0 0x2000000>;
28 status = "okay";
29 };
30};
31
32/*
33 * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
34 * Page Table Address for IPU1 0xbfc00000
35 * Page Table Address for IPU2 0xbfc08000
36 * Page Table Address for DSP1 0xbfc10000
37 * Page Table Address for DSP2 0xbfc18000
38 */
39&reserved_mem {
40 latea_pagetbl: late_pgtbl@bfc00000 {
41 reg = <0x0 0xbfc00000 0x0 0x100000>;
42 no-map;
43 status = "okay";
44 };
45};
46
47&ipu2_cma_pool {
48 reg = <0x0 0x94000000 0x0 0x5000000>;
49};
50
51&mbox_ipu2_ipc3x {
52 ti,no-reset-on-init;
53 ti,no-idle-on-init;
54};
55
56&mmu_ipu2 {
57 ti,late-attach;
58 ti,no-reset-on-init;
59 ti,no-idle-on-init;
60};
61
62&ipu2 {
63 ti,late-attach;
64 ti,no-reset-on-init;
65 ti,no-idle-on-init;
66};
67
68&dsp1 {
69 ti,late-attach;
70 ti,no-reset-on-init;
71 ti,no-idle-on-init;
72};
73
74&mmu0_dsp1 {
75 ti,late-attach;
76 ti,no-reset-on-init;
77 ti,no-idle-on-init;
78};
79
80&mmu1_dsp1 {
81 ti,late-attach;
82 ti,no-reset-on-init;
83 ti,no-idle-on-init;
84};
85
86&dsp1_cma_pool {
87 reg = <0x0 0x99000000 0x0 0x4000000>;
88};
89
90&mbox_dsp1_ipc3x {
91 ti,no-reset-on-init;
92 ti,no-idle-on-init;
93};
94
95&mailbox5 {
96 ti,no-reset-on-init;
97 ti,no-idle-on-init;
98};
99
100&mailbox6 {
101 ti,no-reset-on-init;
102 ti,no-idle-on-init;
103};
104
105&mailbox7 {
106 ti,no-reset-on-init;
107 ti,no-idle-on-init;
108};
109
110&vip1 {
111 status = "disabled";
112 ti,no-reset-on-init;
113 ti,no-idle-on-init;
114};
115
116&vin2a {
117 status = "disabled";
118};
119
120&vpe{
121 status = "disabled";
122 ti,no-reset-on-init;
123 ti,no-idle-on-init;
124};
125
126&pcf_hdmi {
127 lines-initial-states = <0xffe3>;
128};
129
130&ov_10633 {
131 status = "disabled";
132};
133
134&dispc{
135 ti,no-reset-on-init;
136 ti,no-idle-on-init;
137};
138
139&dss {
140 /delete-property/ ti,enable-opt-clks-on-reset;
141 ti,no-reset-on-init;
142 ti,no-idle-on-init;
143 is_shared=<1>;
144};
145
146&timer3{
147 ti,late-attach;
148 ti,no-reset-on-init;
149 ti,no-idle-on-init;
150};
151
152&timer4{
153 ti,late-attach;
154 ti,no-reset-on-init;
155 ti,no-idle-on-init;
156};
157
158&timer5{
159 ti,late-attach;
160 ti,no-reset-on-init;
161 ti,no-idle-on-init;
162};
163
164&timer6{
165 ti,late-attach;
166 ti,no-reset-on-init;
167 ti,no-idle-on-init;
168};
169
170&timer9{
171 ti,late-attach;
172 ti,no-reset-on-init;
173 ti,no-idle-on-init;
174};
175
176&timer10{
177 ti,late-attach;
178 ti,no-reset-on-init;
179 ti,no-idle-on-init;
180};
181
182&timer11{
183 ti,late-attach;
184 ti,no-reset-on-init;
185 ti,no-idle-on-init;
186};
187
188&tvp_5158 {
189 status = "disabled";
190};
191
192/* With RVC, since IPU2 CMEM is 80MB
193 * from 0x94000000 - 0x99000000
194 * cmem_radio needs to move from
195 * 0x95400000 to 0xA2000000 for radio to work with RVC.
196 */
197
198&cmem_radio {
199 reg = <0x0 0xA2000000 0x0 0x400000>;
200};
201
202
203/* Set the default value of the GPIO to be
204 * high instead of default low. Otherwise, the LCD
205 * backlight briefly turns off and turns on
206 * again.
207 */
208&lcd {
209 gpio-init-val=<7>;
210};
211
212/ {
213 backlight {
214 gpio-init-val=<7>;
215 };
216};
diff --git a/arch/arm/boot/dts/dra7x-evm-lcd-auo-g101evn01.0.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-auo-g101evn01.0.dtsi
index 010012e40065..5173353217cd 100644
--- a/arch/arm/boot/dts/dra7x-evm-lcd-auo-g101evn01.0.dtsi
+++ b/arch/arm/boot/dts/dra7x-evm-lcd-auo-g101evn01.0.dtsi
@@ -65,6 +65,7 @@
65 reg = <0x27>; 65 reg = <0x27>;
66 gpio-controller; 66 gpio-controller;
67 #gpio-cells = <2>; 67 #gpio-cells = <2>;
68 lines-initial-states = <0xb2db>;
68 }; 69 };
69 70
70 touchscreen: goodix-gt9271@14 { 71 touchscreen: goodix-gt9271@14 {
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 7bc25d3bc449..2028a81e13e6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -786,7 +786,6 @@ static struct omap_hwmod dra7xx_dss_hwmod = {
786 .name = "dss_core", 786 .name = "dss_core",
787 .class = &dra7xx_dss_hwmod_class, 787 .class = &dra7xx_dss_hwmod_class,
788 .clkdm_name = "dss_clkdm", 788 .clkdm_name = "dss_clkdm",
789 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
790 .sdma_reqs = dra7xx_dss_sdma_reqs, 789 .sdma_reqs = dra7xx_dss_sdma_reqs,
791 .main_clk = "dss_dss_clk", 790 .main_clk = "dss_dss_clk",
792 .prcm = { 791 .prcm = {
@@ -842,7 +841,6 @@ static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
842 }, 841 },
843 }, 842 },
844 .dev_attr = &dss_dispc_dev_attr, 843 .dev_attr = &dss_dispc_dev_attr,
845 .parent_hwmod = &dra7xx_dss_hwmod,
846}; 844};
847 845
848/* 846/*
@@ -884,7 +882,6 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
884 }, 882 },
885 .opt_clks = dss_hdmi_opt_clks, 883 .opt_clks = dss_hdmi_opt_clks,
886 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), 884 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
887 .parent_hwmod = &dra7xx_dss_hwmod,
888}; 885};
889 886
890/* AES (the 'P' (public) device) */ 887/* AES (the 'P' (public) device) */
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index f50963916a21..2497e6f04ea0 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -36,7 +36,7 @@ static struct powerdomain iva_7xx_pwrdm = {
36 .name = "iva_pwrdm", 36 .name = "iva_pwrdm",
37 .prcm_offs = DRA7XX_PRM_IVA_INST, 37 .prcm_offs = DRA7XX_PRM_IVA_INST,
38 .prcm_partition = DRA7XX_PRM_PARTITION, 38 .prcm_partition = DRA7XX_PRM_PARTITION,
39 .pwrsts = PWRSTS_OFF_ON, 39 .pwrsts = PWRSTS_ON,
40 .banks = 4, 40 .banks = 4,
41 .pwrsts_mem_on = { 41 .pwrsts_mem_on = {
42 [0] = PWRSTS_ON, /* hwa_mem */ 42 [0] = PWRSTS_ON, /* hwa_mem */
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 28ae80d71328..000c36a31db8 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -24,6 +24,8 @@
24#include <linux/sched.h> 24#include <linux/sched.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26 26
27#include <video/omapdss.h>
28
27#include "clk.h" 29#include "clk.h"
28 30
29static DEFINE_SPINLOCK(enable_lock); 31static DEFINE_SPINLOCK(enable_lock);
@@ -245,6 +247,13 @@ static int clk_disable_unused(void)
245{ 247{
246 struct clk_core *core; 248 struct clk_core *core;
247 249
250 /*
251 * In case of display sharing, do not explicitly disable unused clocks
252 * as the remote core will be using them
253 */
254 if (omapdss_display_share())
255 return 0;
256
248 if (clk_ignore_unused) { 257 if (clk_ignore_unused) {
249 pr_warn("clk: Not disabling unused clocks\n"); 258 pr_warn("clk: Not disabling unused clocks\n");
250 return 0; 259 return 0;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 87afbea1e7a3..a370380da5a2 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -88,6 +88,26 @@ struct gpio_bank {
88#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) 88#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
89#define LINE_USED(line, offset) (line & (BIT(offset))) 89#define LINE_USED(line, offset) (line & (BIT(offset)))
90 90
91/* RVC HACK for GPIO control from M4 for reverse gear detection
92 * On Android, to find the GPIO dev_name, you run
93 * "ls /sys/devices/platform/44000000.ocp/ | grep gpio"
94 * 48051000.gpio <-- TRM Table 27-16, GPIO7 module base address
95 * 48053000.gpio <-- TRM Table 27-16, GPIO8 module base address
96 * 48055000.gpio <-- TRM Table 27-16, GPIO2 module base address
97 * 48057000.gpio <-- TRM Table 27-16, GPIO3 module base address
98 * 48059000.gpio <-- TRM Table 27-16, GPIO4 module base address
99 * 4805b000.gpio <-- TRM Table 27-16, GPIO5 module base address
100 * 4805d000.gpio <-- TRM Table 27-16, GPIO6 module base address
101 * 4ae10000.gpio <-- TRM Table 27-16, GPIO1 module base address
102 * To get the name, you can use api: dev_name(bank->dev)
103 * By default RVC package uses GPIO7 for reverse gear detection;
104 * the device name is 48051000.gpio
105 * By default RVC package uses pin 18; gpio is 18
106 */
107#define GPIO_STRING_7 "48051000.gpio"
108#define GPIO_STRING_LEN (13)
109#define GPIO_PIN_18 (18)
110
91static void omap_gpio_unmask_irq(struct irq_data *d); 111static void omap_gpio_unmask_irq(struct irq_data *d);
92 112
93static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) 113static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
@@ -102,8 +122,16 @@ static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
102 void __iomem *reg = bank->base; 122 void __iomem *reg = bank->base;
103 u32 l; 123 u32 l;
104 124
125 /* Ignore omap_set_gpio_direction device match GPIO_STRING_7 and
126 * GPIO_PIN_18 used by RVC
127 */
128 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
129 GPIO_STRING_LEN) == 0) && (gpio == GPIO_PIN_18))
130 return;
131
105 reg += bank->regs->direction; 132 reg += bank->regs->direction;
106 l = readl_relaxed(reg); 133 l = readl_relaxed(reg);
134
107 if (is_input) 135 if (is_input)
108 l |= BIT(gpio); 136 l |= BIT(gpio);
109 else 137 else
@@ -120,6 +148,13 @@ static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
120 void __iomem *reg = bank->base; 148 void __iomem *reg = bank->base;
121 u32 l = BIT(offset); 149 u32 l = BIT(offset);
122 150
151 /* Ignore omap_set_gpio_dataout_reg device match GPIO_STRING_7 and
152 * GPIO_PIN_18 used by RVC
153 */
154 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
155 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
156 return;
157
123 if (enable) { 158 if (enable) {
124 reg += bank->regs->set_dataout; 159 reg += bank->regs->set_dataout;
125 bank->context.dataout |= l; 160 bank->context.dataout |= l;
@@ -139,6 +174,14 @@ static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
139 u32 gpio_bit = BIT(offset); 174 u32 gpio_bit = BIT(offset);
140 u32 l; 175 u32 l;
141 176
177 /* Ignore omap_set_gpio_dataout_mask device match GPIO_STRING_7 and
178 * GPIO_PIN_18 used by RVC
179 */
180
181 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
182 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
183 return;
184
142 l = readl_relaxed(reg); 185 l = readl_relaxed(reg);
143 if (enable) 186 if (enable)
144 l |= gpio_bit; 187 l |= gpio_bit;
@@ -298,6 +341,13 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
298 void __iomem *base = bank->base; 341 void __iomem *base = bank->base;
299 u32 gpio_bit = BIT(gpio); 342 u32 gpio_bit = BIT(gpio);
300 343
344 /* Ignore omap_set_gpio_trigger device match GPIO_STRING_7 and
345 * GPIO_PIN_18 used by RVC
346 */
347 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
348 GPIO_STRING_LEN) == 0) && (gpio == GPIO_PIN_18))
349 return;
350
301 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, 351 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
302 trigger & IRQ_TYPE_LEVEL_LOW); 352 trigger & IRQ_TYPE_LEVEL_LOW);
303 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, 353 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
@@ -382,6 +432,13 @@ static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
382 void __iomem *base = bank->base; 432 void __iomem *base = bank->base;
383 u32 l = 0; 433 u32 l = 0;
384 434
435 /* Ignore omap_set_gpio_triggering device match GPIO_STRING_7 and
436 * GPIO_PIN_18 used by RVC
437 */
438 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
439 GPIO_STRING_LEN) == 0) && (gpio == GPIO_PIN_18))
440 return 0;
441
385 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { 442 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
386 omap_set_gpio_trigger(bank, gpio, trigger); 443 omap_set_gpio_trigger(bank, gpio, trigger);
387 } else if (bank->regs->irqctrl) { 444 } else if (bank->regs->irqctrl) {
@@ -490,6 +547,13 @@ static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
490 unsigned long flags; 547 unsigned long flags;
491 unsigned offset = d->hwirq; 548 unsigned offset = d->hwirq;
492 549
550 /* Ignore omap_gpio_irq_type device match GPIO_STRING_7 and
551 * GPIO_PIN_18 used by RVC
552 */
553 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
554 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
555 return 0;
556
493 if (type & ~IRQ_TYPE_SENSE_MASK) 557 if (type & ~IRQ_TYPE_SENSE_MASK)
494 return -EINVAL; 558 return -EINVAL;
495 559
@@ -527,6 +591,7 @@ static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
527 void __iomem *reg = bank->base; 591 void __iomem *reg = bank->base;
528 592
529 reg += bank->regs->irqstatus; 593 reg += bank->regs->irqstatus;
594
530 writel_relaxed(gpio_mask, reg); 595 writel_relaxed(gpio_mask, reg);
531 596
532 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 597 /* Workaround for clearing DSP GPIO interrupts to allow retention */
@@ -542,6 +607,13 @@ static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
542static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, 607static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
543 unsigned offset) 608 unsigned offset)
544{ 609{
610 /* Ignore omap_clear_gpio_irqstatus device match GPIO_STRING_7 and
611 * GPIO_PIN_18 used by RVC
612 */
613 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
614 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
615 return;
616
545 omap_clear_gpio_irqbank(bank, BIT(offset)); 617 omap_clear_gpio_irqbank(bank, BIT(offset));
546} 618}
547 619
@@ -625,6 +697,13 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
625 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 697 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
626 unsigned long flags; 698 unsigned long flags;
627 699
700 /* Ignore omap_gpio_request device match GPIO_STRING_7 and
701 * GPIO_PIN_18 used by RVC
702 */
703 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
704 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
705 return 0;
706
628 /* 707 /*
629 * If this is the first gpio_request for the bank, 708 * If this is the first gpio_request for the bank,
630 * enable the bank module. 709 * enable the bank module.
@@ -645,6 +724,14 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
645 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 724 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
646 unsigned long flags; 725 unsigned long flags;
647 726
727 /* Ignore omap_gpio_free device match GPIO_STRING_7 and
728 * GPIO_PIN_18 used by RVC
729 */
730
731 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
732 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
733 return;
734
648 raw_spin_lock_irqsave(&bank->lock, flags); 735 raw_spin_lock_irqsave(&bank->lock, flags);
649 bank->mod_usage &= ~(BIT(offset)); 736 bank->mod_usage &= ~(BIT(offset));
650 if (!LINE_USED(bank->irq_usage, offset)) { 737 if (!LINE_USED(bank->irq_usage, offset)) {
@@ -698,6 +785,13 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
698 if (bank->level_mask) 785 if (bank->level_mask)
699 level_mask = bank->level_mask & enabled; 786 level_mask = bank->level_mask & enabled;
700 787
788 /* Mask level mask with GPIO_PIN_18 used by RVC when device
789 * match GPIO_STRING_7
790 */
791 if (strncmp(dev_name(bank->dev), GPIO_STRING_7,
792 GPIO_STRING_LEN) == 0)
793 level_mask |= (1 << GPIO_PIN_18);
794
701 /* clear edge sensitive interrupts before handler(s) are 795 /* clear edge sensitive interrupts before handler(s) are
702 called so that we don't miss any interrupt occurred while 796 called so that we don't miss any interrupt occurred while
703 executing them */ 797 executing them */
@@ -747,6 +841,13 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
747 unsigned long flags; 841 unsigned long flags;
748 unsigned offset = d->hwirq; 842 unsigned offset = d->hwirq;
749 843
844 /* Ignore omap_gpio_irq_startup device match GPIO_STRING_7 and
845 * GPIO_PIN_18 used by RVC
846 */
847 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
848 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
849 return 0;
850
750 raw_spin_lock_irqsave(&bank->lock, flags); 851 raw_spin_lock_irqsave(&bank->lock, flags);
751 852
752 if (!LINE_USED(bank->mod_usage, offset)) 853 if (!LINE_USED(bank->mod_usage, offset))
@@ -771,6 +872,13 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
771 unsigned long flags; 872 unsigned long flags;
772 unsigned offset = d->hwirq; 873 unsigned offset = d->hwirq;
773 874
875 /* Ignore omap_gpio_irq_shutdown device match GPIO_STRING_7 and
876 * GPIO_PIN_18 used by RVC
877 */
878 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
879 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
880 return;
881
774 raw_spin_lock_irqsave(&bank->lock, flags); 882 raw_spin_lock_irqsave(&bank->lock, flags);
775 bank->irq_usage &= ~(BIT(offset)); 883 bank->irq_usage &= ~(BIT(offset));
776 omap_set_gpio_irqenable(bank, offset, 0); 884 omap_set_gpio_irqenable(bank, offset, 0);
@@ -807,6 +915,13 @@ static void omap_gpio_ack_irq(struct irq_data *d)
807 struct gpio_bank *bank = omap_irq_data_get_bank(d); 915 struct gpio_bank *bank = omap_irq_data_get_bank(d);
808 unsigned offset = d->hwirq; 916 unsigned offset = d->hwirq;
809 917
918 /* Ignore omap_gpio_ack_irq device match GPIO_STRING_7 and
919 * GPIO_PIN_18 used by RVC
920 */
921 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
922 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
923 return;
924
810 omap_clear_gpio_irqstatus(bank, offset); 925 omap_clear_gpio_irqstatus(bank, offset);
811} 926}
812 927
@@ -816,6 +931,13 @@ static void omap_gpio_mask_irq(struct irq_data *d)
816 unsigned offset = d->hwirq; 931 unsigned offset = d->hwirq;
817 unsigned long flags; 932 unsigned long flags;
818 933
934 /* Ignore omap_gpio_mask_irq device match GPIO_STRING_7 and
935 * GPIO_PIN_18 used by RVC
936 */
937 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
938 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
939 return;
940
819 raw_spin_lock_irqsave(&bank->lock, flags); 941 raw_spin_lock_irqsave(&bank->lock, flags);
820 omap_set_gpio_irqenable(bank, offset, 0); 942 omap_set_gpio_irqenable(bank, offset, 0);
821 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 943 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
@@ -829,6 +951,13 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
829 u32 trigger = irqd_get_trigger_type(d); 951 u32 trigger = irqd_get_trigger_type(d);
830 unsigned long flags; 952 unsigned long flags;
831 953
954 /* Ignore omap_gpio_unmask_irq device match GPIO_STRING_7 and
955 * GPIO_PIN_18 used by RVC
956 */
957 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
958 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
959 return;
960
832 raw_spin_lock_irqsave(&bank->lock, flags); 961 raw_spin_lock_irqsave(&bank->lock, flags);
833 if (trigger) 962 if (trigger)
834 omap_set_gpio_triggering(bank, offset, trigger); 963 omap_set_gpio_triggering(bank, offset, trigger);
@@ -929,6 +1058,14 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
929 unsigned long flags; 1058 unsigned long flags;
930 1059
931 bank = container_of(chip, struct gpio_bank, chip); 1060 bank = container_of(chip, struct gpio_bank, chip);
1061
1062 /* Ignore omap_gpio_input device match GPIO_STRING_7 and
1063 * GPIO_PIN_18 used by RVC
1064 */
1065 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
1066 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
1067 return 0;
1068
932 raw_spin_lock_irqsave(&bank->lock, flags); 1069 raw_spin_lock_irqsave(&bank->lock, flags);
933 omap_set_gpio_direction(bank, offset, 1); 1070 omap_set_gpio_direction(bank, offset, 1);
934 raw_spin_unlock_irqrestore(&bank->lock, flags); 1071 raw_spin_unlock_irqrestore(&bank->lock, flags);
@@ -953,6 +1090,14 @@ static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
953 unsigned long flags; 1090 unsigned long flags;
954 1091
955 bank = container_of(chip, struct gpio_bank, chip); 1092 bank = container_of(chip, struct gpio_bank, chip);
1093
1094 /* Ignore omap_gpio_output device match GPIO_STRING_7 and
1095 * GPIO_PIN_18 used by RVC
1096 */
1097 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
1098 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
1099 return 0;
1100
956 raw_spin_lock_irqsave(&bank->lock, flags); 1101 raw_spin_lock_irqsave(&bank->lock, flags);
957 bank->set_dataout(bank, offset, value); 1102 bank->set_dataout(bank, offset, value);
958 omap_set_gpio_direction(bank, offset, 0); 1103 omap_set_gpio_direction(bank, offset, 0);
@@ -968,6 +1113,13 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
968 1113
969 bank = container_of(chip, struct gpio_bank, chip); 1114 bank = container_of(chip, struct gpio_bank, chip);
970 1115
1116 /* Ignore omap_gpio_debounce device match GPIO_STRING_7 and
1117 * GPIO_PIN_18 used by RVC
1118 */
1119 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
1120 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
1121 return 0;
1122
971 raw_spin_lock_irqsave(&bank->lock, flags); 1123 raw_spin_lock_irqsave(&bank->lock, flags);
972 omap2_set_gpio_debounce(bank, offset, debounce); 1124 omap2_set_gpio_debounce(bank, offset, debounce);
973 raw_spin_unlock_irqrestore(&bank->lock, flags); 1125 raw_spin_unlock_irqrestore(&bank->lock, flags);
@@ -981,6 +1133,14 @@ static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
981 unsigned long flags; 1133 unsigned long flags;
982 1134
983 bank = container_of(chip, struct gpio_bank, chip); 1135 bank = container_of(chip, struct gpio_bank, chip);
1136
1137 /* Ignore omap_gpio_set device match GPIO_STRING_7 and
1138 * GPIO_PIN_18 used by RVC
1139 */
1140 if ((strncmp(dev_name(bank->dev), GPIO_STRING_7,
1141 GPIO_STRING_LEN) == 0) && (offset == GPIO_PIN_18))
1142 return;
1143
984 raw_spin_lock_irqsave(&bank->lock, flags); 1144 raw_spin_lock_irqsave(&bank->lock, flags);
985 bank->set_dataout(bank, offset, value); 1145 bank->set_dataout(bank, offset, value);
986 raw_spin_unlock_irqrestore(&bank->lock, flags); 1146 raw_spin_unlock_irqrestore(&bank->lock, flags);
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
index da708953f6d2..b0f8dd78eb86 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
@@ -222,8 +222,14 @@ static int panel_dpi_probe_of(struct platform_device *pdev)
222 struct display_timing timing; 222 struct display_timing timing;
223 struct videomode vm; 223 struct videomode vm;
224 struct gpio_desc *gpio; 224 struct gpio_desc *gpio;
225 struct property *prop;
226 int gpio_val = GPIOD_OUT_LOW;
225 227
226 gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW); 228 prop = of_find_property(node, "gpio-init-val", NULL);
229 if (prop)
230 of_property_read_u32(node, "gpio-init-val", &gpio_val);
231
232 gpio = devm_gpiod_get_optional(&pdev->dev, "enable", gpio_val);
227 if (IS_ERR(gpio)) 233 if (IS_ERR(gpio))
228 return PTR_ERR(gpio); 234 return PTR_ERR(gpio);
229 235
diff --git a/drivers/gpu/drm/omapdrm/dss/Kconfig b/drivers/gpu/drm/omapdrm/dss/Kconfig
index f7450d401ab3..3965fc6a6149 100644
--- a/drivers/gpu/drm/omapdrm/dss/Kconfig
+++ b/drivers/gpu/drm/omapdrm/dss/Kconfig
@@ -138,6 +138,12 @@ config OMAP2_DSS_SLEEP_AFTER_VENC_RESET
138 138
139endif 139endif
140 140
141config OMAP2_DSS_NUM_OVLS
142 int "Number of Overlays"
143 range 1 10
144 help
145 Select the number of video pipelines which are used for composition.
146
141config TI_DSS6 147config TI_DSS6
142 tristate "TI DSS6 support" 148 tristate "TI DSS6 support"
143 select OMAP_DSS_BASE 149 select OMAP_DSS_BASE
diff --git a/drivers/gpu/drm/omapdrm/dss/core.c b/drivers/gpu/drm/omapdrm/dss/core.c
index 6a3ebfcd7223..142297f89056 100644
--- a/drivers/gpu/drm/omapdrm/dss/core.c
+++ b/drivers/gpu/drm/omapdrm/dss/core.c
@@ -34,6 +34,7 @@
34#include <linux/regulator/consumer.h> 34#include <linux/regulator/consumer.h>
35#include <linux/suspend.h> 35#include <linux/suspend.h>
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <video/omapdss.h>
37 38
38#include "omapdss.h" 39#include "omapdss.h"
39#include "dss.h" 40#include "dss.h"
@@ -45,6 +46,10 @@ static struct {
45 const char *default_display_name; 46 const char *default_display_name;
46} core; 47} core;
47 48
49static uint g_display_skip_init;
50static uint g_display_share;
51static uint g_display_skip_dss_initial;
52
48static char *def_disp_name; 53static char *def_disp_name;
49module_param_named(def_disp, def_disp_name, charp, 0); 54module_param_named(def_disp, def_disp_name, charp, 0);
50MODULE_PARM_DESC(def_disp, "default display name"); 55MODULE_PARM_DESC(def_disp, "default display name");
@@ -62,6 +67,24 @@ enum omapdss_version omapdss_get_version(void)
62} 67}
63EXPORT_SYMBOL(omapdss_get_version); 68EXPORT_SYMBOL(omapdss_get_version);
64 69
70int omapdss_skipinit(void)
71{
72 return g_display_skip_init;
73}
74EXPORT_SYMBOL(omapdss_skipinit);
75
76int omapdss_display_share(void)
77{
78 return g_display_share;
79}
80EXPORT_SYMBOL(omapdss_display_share);
81
82int omapdss_skipdss_initial(void)
83{
84 return g_display_skip_dss_initial;
85}
86EXPORT_SYMBOL(omapdss_skipdss_initial);
87
65struct platform_device *dss_get_core_pdev(void) 88struct platform_device *dss_get_core_pdev(void)
66{ 89{
67 return core.pdev; 90 return core.pdev;
@@ -181,9 +204,27 @@ static void dss_disable_all_devices(void)
181static int __init omap_dss_probe(struct platform_device *pdev) 204static int __init omap_dss_probe(struct platform_device *pdev)
182{ 205{
183 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 206 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
207 struct device_node *node;
184 int r; 208 int r;
185 209
186 core.pdev = pdev; 210 core.pdev = pdev;
211 node = of_find_compatible_node(NULL, NULL, "ti,dra7-dss");
212 if (node) {
213 r = of_property_read_u32(node, "is_shared",
214 &g_display_skip_init);
215
216 if (r)
217 g_display_skip_init = 0;
218
219 if (g_display_skip_init)
220 g_display_share = 1;
221
222 r = of_property_read_u32(node, "skip_dss_initial",
223 &g_display_skip_dss_initial);
224
225 if (r)
226 g_display_skip_dss_initial = 0;
227 }
187 228
188 dss_features_init(omapdss_get_version()); 229 dss_features_init(omapdss_get_version());
189 230
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 0be137b5e958..085498a4357f 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -40,6 +40,7 @@
40#include <linux/regmap.h> 40#include <linux/regmap.h>
41#include <linux/of.h> 41#include <linux/of.h>
42#include <linux/component.h> 42#include <linux/component.h>
43#include <video/omapdss.h>
43#include <drm/drm_fourcc.h> 44#include <drm/drm_fourcc.h>
44 45
45#include "omapdss.h" 46#include "omapdss.h"
@@ -628,7 +629,15 @@ static bool dispc_mgr_go_busy(enum omap_channel channel)
628static void dispc_mgr_go(enum omap_channel channel) 629static void dispc_mgr_go(enum omap_channel channel)
629{ 630{
630 WARN_ON(!dispc_mgr_is_enabled(channel)); 631 WARN_ON(!dispc_mgr_is_enabled(channel));
631 WARN_ON(dispc_mgr_go_busy(channel)); 632
633 if (omapdss_display_share()) {
634 /* In case of display share use case, the remote core
635 * will be setting GO bit independently. Hence we might see the
636 * channel as busy on kernel side. Ignore this and proceed
637 * further
638 */
639 /* WARN_ON(dispc_mgr_go_busy(channel)); */
640 }
632 641
633 DSSDBG("GO %s\n", mgr_desc[channel].name); 642 DSSDBG("GO %s\n", mgr_desc[channel].name);
634 643
@@ -2546,6 +2555,11 @@ static int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info
2546 enum omap_channel channel; 2555 enum omap_channel channel;
2547 const bool replication = true; 2556 const bool replication = true;
2548 2557
2558 if (omapdss_skipinit() &&
2559 ((plane == OMAP_DSS_VIDEO2) || (plane == OMAP_DSS_VIDEO3))) {
2560 return 0;
2561 }
2562
2549 channel = dispc_ovl_get_channel_out(plane); 2563 channel = dispc_ovl_get_channel_out(plane);
2550 2564
2551 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2565 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
@@ -3533,8 +3547,17 @@ static u32 dispc_read_irqstatus(void)
3533 return dispc_read_reg(DISPC_IRQSTATUS); 3547 return dispc_read_reg(DISPC_IRQSTATUS);
3534} 3548}
3535 3549
3550#define A15_DSS_IRQ_MASK (DISPC_IRQ_VSYNC | DISPC_IRQ_FRAMEDONE | DISPC_IRQ_SYNC_LOST | \
3551 DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_FRAMEDONETV | \
3552 DISPC_IRQ_SYNC_LOST_DIGIT | DISPC_IRQ_VSYNC2 | DISPC_IRQ_FRAMEDONE2 | \
3553 DISPC_IRQ_VSYNC3 | DISPC_IRQ_FRAMEDONE3 | DISPC_IRQ_SYNC_LOST3 | \
3554 DISPC_IRQ_GFX_FIFO_UNDERFLOW | DISPC_IRQ_VID1_FIFO_UNDERFLOW)
3555
3536static void dispc_clear_irqstatus(u32 mask) 3556static void dispc_clear_irqstatus(u32 mask)
3537{ 3557{
3558 if (omapdss_display_share())
3559 mask &= A15_DSS_IRQ_MASK;
3560
3538 dispc_write_reg(DISPC_IRQSTATUS, mask); 3561 dispc_write_reg(DISPC_IRQSTATUS, mask);
3539} 3562}
3540 3563
@@ -3550,7 +3573,13 @@ static void dispc_write_irqenable(u32 mask)
3550 /* clear the irqstatus for newly enabled irqs */ 3573 /* clear the irqstatus for newly enabled irqs */
3551 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3574 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3552 3575
3553 dispc_write_reg(DISPC_IRQENABLE, mask); 3576 if (omapdss_display_share())
3577 /* Should not clear already enabled interrupts since remote
3578 * core must be using it
3579 */
3580 dispc_write_reg(DISPC_IRQENABLE, mask | old_mask);
3581 else
3582 dispc_write_reg(DISPC_IRQENABLE, mask);
3554} 3583}
3555 3584
3556void dispc_enable_sidle(void) 3585void dispc_enable_sidle(void)
@@ -3709,16 +3738,23 @@ static void _omap_dispc_initial_config(void)
3709 dispc.core_clk_rate = dispc_fclk_rate(); 3738 dispc.core_clk_rate = dispc_fclk_rate();
3710 } 3739 }
3711 3740
3741 /* For RVC on J6, need to return when is_shared is 1 and skip_dss_initial is 1 on dts */
3742 if ((omapdss_skipdss_initial()) && (omapdss_skipinit())) {
3743 return;
3744 }
3745
3712 /* Use gamma table mode, instead of palette mode */ 3746 /* Use gamma table mode, instead of palette mode */
3713 if (dispc.feat->has_gamma_table) 3747 if (dispc.feat->has_gamma_table)
3714 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3); 3748 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
3715 3749
3716 /* For older DSS versions (FEAT_FUNCGATED) this enables 3750 if (!omapdss_skipinit()) {
3717 * func-clock auto-gating. For newer versions 3751 /* For older DSS versions (FEAT_FUNCGATED) this enables
3718 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables. 3752 * func-clock auto-gating. For newer versions
3719 */ 3753 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3720 if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table) 3754 */
3721 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3755 if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table)
3756 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3757 }
3722 3758
3723 dispc_setup_color_conv_coef(); 3759 dispc_setup_color_conv_coef();
3724 3760
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index a5209c951d2e..0527c1bc7006 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -33,6 +33,7 @@
33#include <linux/of.h> 33#include <linux/of.h>
34#include <linux/clk.h> 34#include <linux/clk.h>
35#include <linux/component.h> 35#include <linux/component.h>
36#include <video/omapdss.h>
36 37
37#include "omapdss.h" 38#include "omapdss.h"
38#include "dss.h" 39#include "dss.h"
@@ -309,7 +310,10 @@ static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel,
309 if (!ok) 310 if (!ok)
310 return -EINVAL; 311 return -EINVAL;
311 312
312 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); 313 if (!omapdss_skipinit())
314 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
315 else
316 r = 0;
313 if (r) 317 if (r)
314 return r; 318 return r;
315 319
@@ -376,7 +380,8 @@ static int dpi_set_mode(struct dpi_data *dpi)
376 t->pixelclock = pck; 380 t->pixelclock = pck;
377 } 381 }
378 382
379 dss_mgr_set_timings(channel, t); 383 if (!omapdss_skipinit())
384 dss_mgr_set_timings(channel, t);
380 385
381 return 0; 386 return 0;
382} 387}
@@ -395,7 +400,8 @@ static void dpi_config_lcd_manager(struct dpi_data *dpi)
395 400
396 dpi->mgr_config.lcden_sig_polarity = 0; 401 dpi->mgr_config.lcden_sig_polarity = 0;
397 402
398 dss_mgr_set_lcd_config(channel, &dpi->mgr_config); 403 if (!omapdss_skipinit())
404 dss_mgr_set_lcd_config(channel, &dpi->mgr_config);
399} 405}
400 406
401static int dpi_display_enable(struct omap_dss_device *dssdev) 407static int dpi_display_enable(struct omap_dss_device *dssdev)
@@ -585,7 +591,8 @@ static int dpi_verify_pll(struct dss_pll *pll)
585 if (r) 591 if (r)
586 return r; 592 return r;
587 593
588 dss_pll_disable(pll); 594 if (!omapdss_skipinit())
595 dss_pll_disable(pll);
589 596
590 return 0; 597 return 0;
591} 598}
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
index af04151c37ff..7c2107ee97ab 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss.c
@@ -41,6 +41,7 @@
41#include <linux/suspend.h> 41#include <linux/suspend.h>
42#include <linux/component.h> 42#include <linux/component.h>
43#include <linux/pinctrl/consumer.h> 43#include <linux/pinctrl/consumer.h>
44#include <video/omapdss.h>
44 45
45#include "omapdss.h" 46#include "omapdss.h"
46#include "dss.h" 47#include "dss.h"
@@ -862,6 +863,9 @@ int dss_runtime_get(void)
862{ 863{
863 int r; 864 int r;
864 865
866 if (omapdss_skipinit())
867 return 0;
868
865 DSSDBG("dss_runtime_get\n"); 869 DSSDBG("dss_runtime_get\n");
866 870
867 r = pm_runtime_get_sync(&dss.pdev->dev); 871 r = pm_runtime_get_sync(&dss.pdev->dev);
@@ -873,6 +877,9 @@ void dss_runtime_put(void)
873{ 877{
874 int r; 878 int r;
875 879
880 if (omapdss_skipinit())
881 return;
882
876 DSSDBG("dss_runtime_put\n"); 883 DSSDBG("dss_runtime_put\n");
877 884
878 r = pm_runtime_put_sync(&dss.pdev->dev); 885 r = pm_runtime_put_sync(&dss.pdev->dev);
@@ -1221,11 +1228,13 @@ static int dss_bind(struct device *dev)
1221 if (r) 1228 if (r)
1222 goto err_init_ports; 1229 goto err_init_ports;
1223 1230
1224 pm_runtime_enable(&pdev->dev); 1231 if (!omapdss_skipinit()) {
1232 pm_runtime_enable(&pdev->dev);
1225 1233
1226 r = dss_runtime_get(); 1234 r = dss_runtime_get();
1227 if (r) 1235 if (r)
1228 goto err_runtime_get; 1236 goto err_runtime_get;
1237 }
1229 1238
1230 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 1239 dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
1231 1240
@@ -1266,7 +1275,8 @@ static int dss_bind(struct device *dev)
1266 1275
1267err_component: 1276err_component:
1268err_runtime_get: 1277err_runtime_get:
1269 pm_runtime_disable(&pdev->dev); 1278 if (!omapdss_skipinit())
1279 pm_runtime_disable(&pdev->dev);
1270 dss_uninit_ports(pdev); 1280 dss_uninit_ports(pdev);
1271err_init_ports: 1281err_init_ports:
1272 if (dss.video1_pll) 1282 if (dss.video1_pll)
@@ -1296,7 +1306,8 @@ static void dss_unbind(struct device *dev)
1296 1306
1297 dss_uninit_ports(pdev); 1307 dss_uninit_ports(pdev);
1298 1308
1299 pm_runtime_disable(&pdev->dev); 1309 if (!omapdss_skipinit())
1310 pm_runtime_disable(&pdev->dev);
1300 1311
1301 dss_put_clocks(); 1312 dss_put_clocks();
1302} 1313}
diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c
index 2e2ae1080a56..4c18c3ae7525 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss_features.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c
@@ -28,6 +28,11 @@
28#include "dss.h" 28#include "dss.h"
29#include "dss_features.h" 29#include "dss_features.h"
30 30
31static int num_ovls;
32
33MODULE_PARM_DESC(num_ovls, "Number of pipelines used for composition");
34module_param(num_ovls, int, 0600);
35
31/* Defines a generic omap register field */ 36/* Defines a generic omap register field */
32struct dss_reg_field { 37struct dss_reg_field {
33 u8 start, end; 38 u8 start, end;
@@ -757,7 +762,7 @@ static const struct omap_dss_features omap5_dss_features = {
757 .num_features = ARRAY_SIZE(omap5_dss_feat_list), 762 .num_features = ARRAY_SIZE(omap5_dss_feat_list),
758 763
759 .num_mgrs = 4, 764 .num_mgrs = 4,
760 .num_ovls = 4, 765 .num_ovls = CONFIG_OMAP2_DSS_NUM_OVLS,
761 .supported_displays = omap5_dss_supported_displays, 766 .supported_displays = omap5_dss_supported_displays,
762 .supported_outputs = omap5_dss_supported_outputs, 767 .supported_outputs = omap5_dss_supported_outputs,
763 .supported_color_modes = omap4_dss_supported_color_modes, 768 .supported_color_modes = omap4_dss_supported_color_modes,
@@ -775,7 +780,7 @@ int dss_feat_get_num_mgrs(void)
775 780
776int dss_feat_get_num_ovls(void) 781int dss_feat_get_num_ovls(void)
777{ 782{
778 return omap_current_dss_features->num_ovls; 783 return num_ovls ? num_ovls : omap_current_dss_features->num_ovls;
779} 784}
780 785
781unsigned long dss_feat_get_param_min(enum dss_range_param param) 786unsigned long dss_feat_get_param_min(enum dss_range_param param)
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index f841edf14bac..ef4f49803966 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -158,11 +158,13 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
158 int ret; 158 int ret;
159 159
160 if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { 160 if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
161 priv->channel_status[channel] = true;
161 priv->dispc_ops->mgr_enable(channel, enable); 162 priv->dispc_ops->mgr_enable(channel, enable);
162 return; 163 return;
163 } 164 }
164 165
165 if (priv->dispc_ops->mgr_is_enabled(channel) == enable) 166 if (priv->channel_status[omap_crtc->channel] &&
167 priv->dispc_ops->mgr_is_enabled(omap_crtc->channel))
166 return; 168 return;
167 169
168 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { 170 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
@@ -194,6 +196,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
194 wait = omap_irq_wait_init(dev, vsync_irq, 2); 196 wait = omap_irq_wait_init(dev, vsync_irq, 2);
195 } 197 }
196 198
199 priv->channel_status[channel] = true;
197 priv->dispc_ops->mgr_enable(channel, enable); 200 priv->dispc_ops->mgr_enable(channel, enable);
198 201
199 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); 202 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
@@ -505,7 +508,8 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
505 priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length); 508 priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length);
506 } 509 }
507 510
508 if (priv->dispc_ops->mgr_is_enabled(omap_crtc->channel)) { 511 if (priv->channel_status[omap_crtc->channel] &&
512 priv->dispc_ops->mgr_is_enabled(omap_crtc->channel)) {
509 513
510 DBG("%s: GO", omap_crtc->name); 514 DBG("%s: GO", omap_crtc->name);
511 515
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index 82ba6dc9fc7c..57ceda1d139b 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -81,6 +81,8 @@ struct omap_drm_private {
81 81
82 struct workqueue_struct *wq; 82 struct workqueue_struct *wq;
83 83
84 unsigned int channel_status[8];
85
84 /* lock for obj_list below */ 86 /* lock for obj_list below */
85 spinlock_t list_lock; 87 spinlock_t list_lock;
86 88
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c
index 7e5374f201b7..1fa68a206253 100644
--- a/drivers/gpu/drm/omapdrm/omap_irq.c
+++ b/drivers/gpu/drm/omapdrm/omap_irq.c
@@ -18,6 +18,7 @@
18 */ 18 */
19 19
20#include "omap_drv.h" 20#include "omap_drv.h"
21#include <video/omapdss.h>
21 22
22static DEFINE_SPINLOCK(list_lock); 23static DEFINE_SPINLOCK(list_lock);
23 24
@@ -187,6 +188,12 @@ void omap_irq_disable_vblank(struct drm_device *dev, unsigned int pipe)
187 spin_unlock_irqrestore(&list_lock, flags); 188 spin_unlock_irqrestore(&list_lock, flags);
188} 189}
189 190
191#define A15_DSS_IRQ_MASK (DISPC_IRQ_VSYNC | DISPC_IRQ_FRAMEDONE | DISPC_IRQ_SYNC_LOST | \
192 DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_FRAMEDONETV | \
193 DISPC_IRQ_SYNC_LOST_DIGIT | DISPC_IRQ_VSYNC2 | DISPC_IRQ_FRAMEDONE2 | \
194 DISPC_IRQ_VSYNC3 | DISPC_IRQ_FRAMEDONE3 | DISPC_IRQ_SYNC_LOST3 | \
195 DISPC_IRQ_GFX_FIFO_UNDERFLOW | DISPC_IRQ_VID1_FIFO_UNDERFLOW)
196
190static irqreturn_t omap_irq_handler(int irq, void *arg) 197static irqreturn_t omap_irq_handler(int irq, void *arg)
191{ 198{
192 struct drm_device *dev = (struct drm_device *) arg; 199 struct drm_device *dev = (struct drm_device *) arg;
@@ -195,8 +202,19 @@ static irqreturn_t omap_irq_handler(int irq, void *arg)
195 unsigned long flags; 202 unsigned long flags;
196 unsigned int id; 203 unsigned int id;
197 u32 irqstatus; 204 u32 irqstatus;
205 u32 irqenable;
198 206
199 irqstatus = priv->dispc_ops->read_irqstatus(); 207 irqstatus = priv->dispc_ops->read_irqstatus();
208 irqenable = priv->dispc_ops->read_irqenable();
209 irqstatus &= irqenable;
210
211 if (omapdss_display_share()) {
212 if ((irqstatus & A15_DSS_IRQ_MASK) == 0x0000) {
213 udelay(1000);
214 return IRQ_HANDLED;
215 }
216 }
217
200 priv->dispc_ops->clear_irqstatus(irqstatus); 218 priv->dispc_ops->clear_irqstatus(irqstatus);
201 priv->dispc_ops->read_irqstatus(); /* flush posted write */ 219 priv->dispc_ops->read_irqstatus(); /* flush posted write */
202 220
diff --git a/drivers/video/backlight/led_bl.c b/drivers/video/backlight/led_bl.c
index 279caa9c271e..598253f5b234 100644
--- a/drivers/video/backlight/led_bl.c
+++ b/drivers/video/backlight/led_bl.c
@@ -30,6 +30,8 @@ struct led_bl_data {
30 30
31 unsigned int max_brightness; 31 unsigned int max_brightness;
32 unsigned int default_brightness; 32 unsigned int default_brightness;
33 unsigned int gpio_init_val;
34
33}; 35};
34 36
35static void led_bl_set_brightness(struct led_bl_data *priv, int brightness) 37static void led_bl_set_brightness(struct led_bl_data *priv, int brightness)
@@ -95,6 +97,8 @@ static int led_bl_parse_dt(struct device *dev,
95 u32 *levels; 97 u32 *levels;
96 u32 value; 98 u32 value;
97 int ret; 99 int ret;
100 struct property *prop;
101 int gpio_val = GPIOD_OUT_LOW;
98 102
99 if (!node) 103 if (!node)
100 return -ENODEV; 104 return -ENODEV;
@@ -122,9 +126,14 @@ static int led_bl_parse_dt(struct device *dev,
122 return -EINVAL; 126 return -EINVAL;
123 } 127 }
124 128
129 prop = of_find_property(node, "gpio-init-val", NULL);
130 if (prop)
131 of_property_read_u32(node, "gpio-init-val", &gpio_val);
132
125 priv->levels = levels; 133 priv->levels = levels;
126 priv->max_brightness = num_levels - 1; 134 priv->max_brightness = num_levels - 1;
127 priv->default_brightness = value; 135 priv->default_brightness = value;
136 priv->gpio_init_val = gpio_val;
128 137
129 priv->led_cdev = of_led_get(node); 138 priv->led_cdev = of_led_get(node);
130 if (IS_ERR(priv->led_cdev)) 139 if (IS_ERR(priv->led_cdev))
@@ -155,7 +164,7 @@ static int led_bl_probe(struct platform_device *pdev)
155 } 164 }
156 165
157 priv->enable_gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 166 priv->enable_gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
158 GPIOD_OUT_LOW); 167 priv->gpio_init_val);
159 if (IS_ERR(priv->enable_gpio)) { 168 if (IS_ERR(priv->enable_gpio)) {
160 ret = PTR_ERR(priv->enable_gpio); 169 ret = PTR_ERR(priv->enable_gpio);
161 goto err; 170 goto err;
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
new file mode 100644
index 000000000000..2b79220c83f8
--- /dev/null
+++ b/include/video/omapdss.h
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2016 Texas Instruments, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __OMAP_OMAPDSS_H
11#define __OMAP_OMAPDSS_H
12
13int omapdss_skipinit(void);
14int omapdss_display_share(void);
15int omapdss_skipdss_initial(void);
16
17#endif
diff --git a/ti_config_fragments/audio_display.cfg b/ti_config_fragments/audio_display.cfg
index 8925c31049fe..94aef5b6caf6 100644
--- a/ti_config_fragments/audio_display.cfg
+++ b/ti_config_fragments/audio_display.cfg
@@ -38,6 +38,7 @@ CONFIG_DRM_OMAP_NUM_CRTCS=2
38CONFIG_DRM_OMAP_WB=y 38CONFIG_DRM_OMAP_WB=y
39 39
40CONFIG_OMAP2_DSS=y 40CONFIG_OMAP2_DSS=y
41CONFIG_OMAP2_DSS_NUM_OVLS=2
41CONFIG_OMAP2_DSS_DEBUGFS=y 42CONFIG_OMAP2_DSS_DEBUGFS=y
42CONFIG_OMAP2_DSS_DPI=y 43CONFIG_OMAP2_DSS_DPI=y
43CONFIG_OMAP2_DSS_VENC=n 44CONFIG_OMAP2_DSS_VENC=n