diff options
Diffstat (limited to 'arch/arm/boot/dts/dra76-evm.dts')
-rw-r--r-- | arch/arm/boot/dts/dra76-evm.dts | 498 |
1 files changed, 498 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts new file mode 100644 index 000000000000..213f4b53f965 --- /dev/null +++ b/arch/arm/boot/dts/dra76-evm.dts | |||
@@ -0,0 +1,498 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | #include "dra76x.dtsi" | ||
11 | #include "dra7-evm-common.dtsi" | ||
12 | #include "dra76x-mmc-iodelay.dtsi" | ||
13 | #include <dt-bindings/net/ti-dp83867.h> | ||
14 | |||
15 | / { | ||
16 | model = "TI DRA762 EVM"; | ||
17 | compatible = "ti,dra76-evm", "ti,dra76", "ti,dra7"; | ||
18 | |||
19 | memory { | ||
20 | device_type = "memory"; | ||
21 | reg = <0x0 0x80000000 0x0 0x80000000>; | ||
22 | }; | ||
23 | |||
24 | reserved-memory { | ||
25 | #address-cells = <2>; | ||
26 | #size-cells = <2>; | ||
27 | ranges; | ||
28 | |||
29 | ipu2_cma_pool: ipu2_cma@95800000 { | ||
30 | compatible = "shared-dma-pool"; | ||
31 | reg = <0x0 0x95800000 0x0 0x3800000>; | ||
32 | reusable; | ||
33 | status = "okay"; | ||
34 | }; | ||
35 | |||
36 | dsp1_cma_pool: dsp1_cma@99000000 { | ||
37 | compatible = "shared-dma-pool"; | ||
38 | reg = <0x0 0x99000000 0x0 0x4000000>; | ||
39 | reusable; | ||
40 | status = "okay"; | ||
41 | }; | ||
42 | |||
43 | ipu1_cma_pool: ipu1_cma@9d000000 { | ||
44 | compatible = "shared-dma-pool"; | ||
45 | reg = <0x0 0x9d000000 0x0 0x2000000>; | ||
46 | reusable; | ||
47 | status = "okay"; | ||
48 | }; | ||
49 | |||
50 | dsp2_cma_pool: dsp2_cma@9f000000 { | ||
51 | compatible = "shared-dma-pool"; | ||
52 | reg = <0x0 0x9f000000 0x0 0x800000>; | ||
53 | reusable; | ||
54 | status = "okay"; | ||
55 | }; | ||
56 | }; | ||
57 | |||
58 | aliases { | ||
59 | i2c7 = &disp_ser; | ||
60 | }; | ||
61 | |||
62 | vsys_12v0: fixedregulator-vsys12v0 { | ||
63 | /* main supply */ | ||
64 | compatible = "regulator-fixed"; | ||
65 | regulator-name = "vsys_12v0"; | ||
66 | regulator-min-microvolt = <12000000>; | ||
67 | regulator-max-microvolt = <12000000>; | ||
68 | regulator-always-on; | ||
69 | regulator-boot-on; | ||
70 | }; | ||
71 | |||
72 | vsys_5v0: fixedregulator-vsys5v0 { | ||
73 | /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ | ||
74 | compatible = "regulator-fixed"; | ||
75 | regulator-name = "vsys_5v0"; | ||
76 | regulator-min-microvolt = <5000000>; | ||
77 | regulator-max-microvolt = <5000000>; | ||
78 | vin-supply = <&vsys_12v0>; | ||
79 | regulator-always-on; | ||
80 | regulator-boot-on; | ||
81 | }; | ||
82 | |||
83 | vsys_3v3: fixedregulator-vsys3v3 { | ||
84 | /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ | ||
85 | compatible = "regulator-fixed"; | ||
86 | regulator-name = "vsys_3v3"; | ||
87 | regulator-min-microvolt = <3300000>; | ||
88 | regulator-max-microvolt = <3300000>; | ||
89 | vin-supply = <&vsys_12v0>; | ||
90 | regulator-always-on; | ||
91 | regulator-boot-on; | ||
92 | }; | ||
93 | |||
94 | vio_3v3: fixedregulator-vio_3v3 { | ||
95 | compatible = "regulator-fixed"; | ||
96 | regulator-name = "vio_3v3"; | ||
97 | regulator-min-microvolt = <3300000>; | ||
98 | regulator-max-microvolt = <3300000>; | ||
99 | vin-supply = <&vsys_3v3>; | ||
100 | regulator-always-on; | ||
101 | regulator-boot-on; | ||
102 | }; | ||
103 | |||
104 | vio_3v3_sd: fixedregulator-sd { | ||
105 | compatible = "regulator-fixed"; | ||
106 | regulator-name = "vio_3v3_sd"; | ||
107 | regulator-min-microvolt = <3300000>; | ||
108 | regulator-max-microvolt = <3300000>; | ||
109 | vin-supply = <&vio_3v3>; | ||
110 | enable-active-high; | ||
111 | gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; | ||
112 | }; | ||
113 | |||
114 | vio_1v8: fixedregulator-vio_1v8 { | ||
115 | compatible = "regulator-fixed"; | ||
116 | regulator-name = "vio_1v8"; | ||
117 | regulator-min-microvolt = <1800000>; | ||
118 | regulator-max-microvolt = <1800000>; | ||
119 | vin-supply = <&smps5_reg>; | ||
120 | }; | ||
121 | |||
122 | vtt_fixed: fixedregulator-vtt { | ||
123 | compatible = "regulator-fixed"; | ||
124 | regulator-name = "vtt_fixed"; | ||
125 | regulator-min-microvolt = <1350000>; | ||
126 | regulator-max-microvolt = <1350000>; | ||
127 | vin-supply = <&vsys_3v3>; | ||
128 | regulator-always-on; | ||
129 | regulator-boot-on; | ||
130 | }; | ||
131 | |||
132 | aic_dvdd: fixedregulator-aic_dvdd { | ||
133 | /* TPS77018DBVT */ | ||
134 | compatible = "regulator-fixed"; | ||
135 | regulator-name = "aic_dvdd"; | ||
136 | vin-supply = <&vio_3v3>; | ||
137 | regulator-min-microvolt = <1800000>; | ||
138 | regulator-max-microvolt = <1800000>; | ||
139 | }; | ||
140 | }; | ||
141 | |||
142 | &i2c1 { | ||
143 | status = "okay"; | ||
144 | clock-frequency = <400000>; | ||
145 | |||
146 | tps65917: tps65917@58 { | ||
147 | compatible = "ti,tps65917"; | ||
148 | reg = <0x58>; | ||
149 | ti,system-power-controller; | ||
150 | interrupt-controller; | ||
151 | #interrupt-cells = <2>; | ||
152 | |||
153 | tps65917_pmic { | ||
154 | compatible = "ti,tps65917-pmic"; | ||
155 | |||
156 | smps12-in-supply = <&vsys_3v3>; | ||
157 | smps3-in-supply = <&vsys_3v3>; | ||
158 | smps4-in-supply = <&vsys_3v3>; | ||
159 | smps5-in-supply = <&vsys_3v3>; | ||
160 | ldo1-in-supply = <&vsys_3v3>; | ||
161 | ldo2-in-supply = <&vsys_3v3>; | ||
162 | ldo3-in-supply = <&vsys_5v0>; | ||
163 | ldo4-in-supply = <&vsys_5v0>; | ||
164 | ldo5-in-supply = <&vsys_3v3>; | ||
165 | |||
166 | tps65917_regulators: regulators { | ||
167 | smps12_reg: smps12 { | ||
168 | /* VDD_DSPEVE */ | ||
169 | regulator-name = "smps12"; | ||
170 | regulator-min-microvolt = <850000>; | ||
171 | regulator-max-microvolt = <1250000>; | ||
172 | regulator-always-on; | ||
173 | regulator-boot-on; | ||
174 | }; | ||
175 | |||
176 | smps3_reg: smps3 { | ||
177 | /* VDD_CORE */ | ||
178 | regulator-name = "smps3"; | ||
179 | regulator-min-microvolt = <850000>; | ||
180 | regulator-max-microvolt = <1250000>; | ||
181 | regulator-boot-on; | ||
182 | regulator-always-on; | ||
183 | }; | ||
184 | |||
185 | smps4_reg: smps4 { | ||
186 | /* VDD_IVA */ | ||
187 | regulator-name = "smps4"; | ||
188 | regulator-min-microvolt = <850000>; | ||
189 | regulator-max-microvolt = <1250000>; | ||
190 | regulator-always-on; | ||
191 | regulator-boot-on; | ||
192 | }; | ||
193 | |||
194 | smps5_reg: smps5 { | ||
195 | /* VDDS1V8 */ | ||
196 | regulator-name = "smps5"; | ||
197 | regulator-min-microvolt = <1800000>; | ||
198 | regulator-max-microvolt = <1800000>; | ||
199 | regulator-boot-on; | ||
200 | regulator-always-on; | ||
201 | }; | ||
202 | |||
203 | ldo1_reg: ldo1 { | ||
204 | /* LDO1_OUT --> VDA_PHY1_1V8 */ | ||
205 | regulator-name = "ldo1"; | ||
206 | regulator-min-microvolt = <1800000>; | ||
207 | regulator-max-microvolt = <1800000>; | ||
208 | regulator-always-on; | ||
209 | regulator-boot-on; | ||
210 | regulator-allow-bypass; | ||
211 | }; | ||
212 | |||
213 | ldo2_reg: ldo2 { | ||
214 | /* LDO2_OUT --> VDA_PHY2_1V8 */ | ||
215 | regulator-name = "ldo2"; | ||
216 | regulator-min-microvolt = <1800000>; | ||
217 | regulator-max-microvolt = <1800000>; | ||
218 | regulator-allow-bypass; | ||
219 | regulator-always-on; | ||
220 | }; | ||
221 | |||
222 | ldo3_reg: ldo3 { | ||
223 | /* VDA_USB_3V3 */ | ||
224 | regulator-name = "ldo3"; | ||
225 | regulator-min-microvolt = <3300000>; | ||
226 | regulator-max-microvolt = <3300000>; | ||
227 | regulator-boot-on; | ||
228 | regulator-always-on; | ||
229 | }; | ||
230 | |||
231 | ldo5_reg: ldo5 { | ||
232 | /* VDDA_1V8_PLL */ | ||
233 | regulator-name = "ldo5"; | ||
234 | regulator-min-microvolt = <1800000>; | ||
235 | regulator-max-microvolt = <1800000>; | ||
236 | regulator-always-on; | ||
237 | regulator-boot-on; | ||
238 | }; | ||
239 | |||
240 | ldo4_reg: ldo4 { | ||
241 | /* VDD_SDIO_DV */ | ||
242 | regulator-name = "ldo4"; | ||
243 | regulator-min-microvolt = <1800000>; | ||
244 | regulator-max-microvolt = <3300000>; | ||
245 | regulator-boot-on; | ||
246 | regulator-always-on; | ||
247 | }; | ||
248 | }; | ||
249 | }; | ||
250 | |||
251 | tps65917_power_button { | ||
252 | compatible = "ti,palmas-pwrbutton"; | ||
253 | interrupt-parent = <&tps65917>; | ||
254 | interrupts = <1 IRQ_TYPE_NONE>; | ||
255 | wakeup-source; | ||
256 | ti,palmas-long-press-seconds = <6>; | ||
257 | }; | ||
258 | }; | ||
259 | |||
260 | lp87565: lp87565@60 { | ||
261 | compatible = "ti,lp87565-q1"; | ||
262 | reg = <0x60>; | ||
263 | |||
264 | buck10-in-supply =<&vsys_3v3>; | ||
265 | buck23-in-supply =<&vsys_3v3>; | ||
266 | |||
267 | regulators: regulators { | ||
268 | buck10_reg: buck10 { | ||
269 | /*VDD_MPU*/ | ||
270 | regulator-name = "buck10"; | ||
271 | regulator-min-microvolt = <850000>; | ||
272 | regulator-max-microvolt = <1250000>; | ||
273 | regulator-always-on; | ||
274 | regulator-boot-on; | ||
275 | }; | ||
276 | |||
277 | buck23_reg: buck23 { | ||
278 | /* VDD_GPU*/ | ||
279 | regulator-name = "buck23"; | ||
280 | regulator-min-microvolt = <850000>; | ||
281 | regulator-max-microvolt = <1250000>; | ||
282 | regulator-boot-on; | ||
283 | regulator-always-on; | ||
284 | }; | ||
285 | }; | ||
286 | }; | ||
287 | |||
288 | pcf_lcd: pcf8757@20 { | ||
289 | compatible = "ti,pcf8575", "nxp,pcf8575"; | ||
290 | reg = <0x20>; | ||
291 | gpio-controller; | ||
292 | #gpio-cells = <2>; | ||
293 | interrupt-controller; | ||
294 | #interrupt-cells = <2>; | ||
295 | interrupt-parent = <&gpio1>; | ||
296 | interrupts = <3 IRQ_TYPE_EDGE_FALLING>; | ||
297 | }; | ||
298 | |||
299 | pcf_gpio_21: pcf8757@21 { | ||
300 | compatible = "ti,pcf8575", "nxp,pcf8575"; | ||
301 | reg = <0x21>; | ||
302 | gpio-controller; | ||
303 | #gpio-cells = <2>; | ||
304 | interrupt-parent = <&gpio1>; | ||
305 | interrupts = <3 IRQ_TYPE_EDGE_FALLING>; | ||
306 | interrupt-controller; | ||
307 | #interrupt-cells = <2>; | ||
308 | }; | ||
309 | |||
310 | pcf_hdmi: pcf8575@26 { | ||
311 | compatible = "ti,pcf8575", "nxp,pcf8575"; | ||
312 | reg = <0x26>; | ||
313 | gpio-controller; | ||
314 | #gpio-cells = <2>; | ||
315 | p1 { | ||
316 | /* vin6_sel_s0: high: VIN6, low: audio */ | ||
317 | gpio-hog; | ||
318 | gpios = <1 GPIO_ACTIVE_HIGH>; | ||
319 | output-low; | ||
320 | line-name = "vin6_sel_s0"; | ||
321 | }; | ||
322 | }; | ||
323 | |||
324 | tlv320aic3106: tlv320aic3106@19 { | ||
325 | #sound-dai-cells = <0>; | ||
326 | compatible = "ti,tlv320aic3106"; | ||
327 | reg = <0x19>; | ||
328 | adc-settle-ms = <40>; | ||
329 | ai3x-micbias-vg = <1>; /* 2.0V */ | ||
330 | status = "okay"; | ||
331 | |||
332 | /* Regulators */ | ||
333 | AVDD-supply = <&vio_3v3>; | ||
334 | IOVDD-supply = <&vio_3v3>; | ||
335 | DRVDD-supply = <&vio_3v3>; | ||
336 | DVDD-supply = <&aic_dvdd>; | ||
337 | }; | ||
338 | }; | ||
339 | |||
340 | &tpd12s015 { | ||
341 | compatible = "ti,tpd12s015"; | ||
342 | |||
343 | gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */ | ||
344 | <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */ | ||
345 | <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ | ||
346 | |||
347 | }; | ||
348 | |||
349 | &mmc1 { | ||
350 | status = "okay"; | ||
351 | vmmc-supply = <&vio_3v3_sd>; | ||
352 | vmmc_aux-supply = <&ldo4_reg>; | ||
353 | bus-width = <4>; | ||
354 | /* | ||
355 | * SDCD signal is not being used here - using the fact that GPIO mode | ||
356 | * is always hardwired. | ||
357 | */ | ||
358 | cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; | ||
359 | max-frequency = <192000000>; | ||
360 | pinctrl-names = "default", "hs"; | ||
361 | pinctrl-0 = <&mmc1_pins_default>; | ||
362 | pinctrl-1 = <&mmc1_pins_hs>; | ||
363 | }; | ||
364 | |||
365 | &mmc2 { | ||
366 | status = "okay"; | ||
367 | vmmc-supply = <&vio_1v8>; | ||
368 | bus-width = <8>; | ||
369 | max-frequency = <192000000>; | ||
370 | pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; | ||
371 | pinctrl-0 = <&mmc2_pins_default>; | ||
372 | pinctrl-1 = <&mmc2_pins_hs>; | ||
373 | pinctrl-2 = <&mmc2_pins_ddr>; | ||
374 | pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; | ||
375 | }; | ||
376 | |||
377 | &oppdm_mpu { | ||
378 | vdd-supply = <&buck10_reg>; | ||
379 | }; | ||
380 | |||
381 | &oppdm_dspeve { | ||
382 | vdd-supply = <&smps12_reg>; | ||
383 | }; | ||
384 | |||
385 | &oppdm_gpu { | ||
386 | vdd-supply = <&buck23_reg>; | ||
387 | }; | ||
388 | |||
389 | &oppdm_ivahd { | ||
390 | vdd-supply = <&smps4_reg>; | ||
391 | }; | ||
392 | |||
393 | &oppdm_core { | ||
394 | vdd-supply = <&smps3_reg>; | ||
395 | }; | ||
396 | |||
397 | /* No RTC on this device */ | ||
398 | &rtc { | ||
399 | status = "disabled"; | ||
400 | }; | ||
401 | |||
402 | &mac { | ||
403 | status = "okay"; | ||
404 | |||
405 | dual_emac; | ||
406 | }; | ||
407 | |||
408 | &cpsw_emac0 { | ||
409 | phy_id = <&davinci_mdio>, <2>; | ||
410 | phy-mode = "rgmii-id"; | ||
411 | dual_emac_res_vlan = <1>; | ||
412 | }; | ||
413 | |||
414 | &cpsw_emac1 { | ||
415 | phy_id = <&davinci_mdio>, <3>; | ||
416 | phy-mode = "rgmii-id"; | ||
417 | dual_emac_res_vlan = <2>; | ||
418 | }; | ||
419 | |||
420 | &davinci_mdio { | ||
421 | dp83867_0: ethernet-phy@2 { | ||
422 | reg = <2>; | ||
423 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; | ||
424 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; | ||
425 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; | ||
426 | ti,min-output-impedance; | ||
427 | ti,dp83867-rxctrl-strap-quirk; | ||
428 | }; | ||
429 | |||
430 | dp83867_1: ethernet-phy@3 { | ||
431 | reg = <3>; | ||
432 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; | ||
433 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; | ||
434 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; | ||
435 | ti,min-output-impedance; | ||
436 | ti,dp83867-rxctrl-strap-quirk; | ||
437 | }; | ||
438 | }; | ||
439 | |||
440 | &usb2_phy1 { | ||
441 | phy-supply = <&ldo3_reg>; | ||
442 | }; | ||
443 | |||
444 | &usb2_phy2 { | ||
445 | phy-supply = <&ldo3_reg>; | ||
446 | }; | ||
447 | |||
448 | &i2c3 { | ||
449 | disp_ser: serializer@0c { | ||
450 | compatible = "ti,ds90ub921q"; | ||
451 | reg = <0x0c>; | ||
452 | |||
453 | #address-cells = <1>; | ||
454 | #size-cells = <0>; | ||
455 | status = "disabled"; | ||
456 | }; | ||
457 | }; | ||
458 | |||
459 | &dss { | ||
460 | status = "ok"; | ||
461 | vdda_video-supply = <&ldo5_reg>; | ||
462 | |||
463 | ports { | ||
464 | #address-cells = <1>; | ||
465 | #size-cells = <0>; | ||
466 | |||
467 | status = "disabled"; | ||
468 | |||
469 | port@lcd3 { | ||
470 | reg = <2>; | ||
471 | |||
472 | dpi_out3: endpoint { | ||
473 | data-lines = <24>; | ||
474 | }; | ||
475 | }; | ||
476 | }; | ||
477 | }; | ||
478 | |||
479 | &hdmi { | ||
480 | vdda-supply = <&ldo1_reg>; | ||
481 | }; | ||
482 | |||
483 | &qspi { | ||
484 | spi-max-frequency = <96000000>; | ||
485 | m25p80@0 { | ||
486 | spi-max-frequency = <96000000>; | ||
487 | }; | ||
488 | }; | ||
489 | |||
490 | &pcie2_phy { | ||
491 | status = "okay"; | ||
492 | }; | ||
493 | |||
494 | &pcie1_rc { | ||
495 | num-lanes = <2>; | ||
496 | phys = <&pcie1_phy>, <&pcie2_phy>; | ||
497 | phy-names = "pcie-phy0", "pcie-phy1"; | ||
498 | }; | ||