diff options
Diffstat (limited to 'arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi')
-rw-r--r-- | arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 435 |
1 files changed, 435 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi new file mode 100644 index 000000000000..c95a8a1091ab --- /dev/null +++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | |||
@@ -0,0 +1,435 @@ | |||
1 | /* | ||
2 | * MMC IOdelay values for TI's DRA76x and AM576x SoCs. | ||
3 | * | ||
4 | * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | /* | ||
17 | * Rules for modifying this file: | ||
18 | * a) Update of this file should typically correspond to a datamanual revision. | ||
19 | * Datamanual revision that was used should be updated in comment below. | ||
20 | * If there is no update to datamanual, do not update the values. If you | ||
21 | * need to use values different from that recommended by the datamanual | ||
22 | * for your design, then you should consider adding values to the device- | ||
23 | * -tree file for your board directly. | ||
24 | * b) We keep the mode names as close to the datamanual as possible. So | ||
25 | * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, | ||
26 | * we follow that in code too. | ||
27 | * c) If the values change between multiple revisions of silicon, we add | ||
28 | * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, | ||
29 | * 'rev20' for PG 2.0 and so on. | ||
30 | * d) The node name and node label should be the exact same string. This is | ||
31 | * to curb naming creativity and achieve consistency. | ||
32 | * | ||
33 | * Datamanual Revisions: | ||
34 | * | ||
35 | * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017 | ||
36 | * | ||
37 | */ | ||
38 | |||
39 | &dra7_pmx_core { | ||
40 | mmc1_pins_default: mmc1_pins_default { | ||
41 | pinctrl-single,pins = < | ||
42 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | ||
43 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
44 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
45 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
46 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
47 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
48 | >; | ||
49 | }; | ||
50 | |||
51 | mmc1_pins_sdr12: mmc1_pins_sdr12 { | ||
52 | pinctrl-single,pins = < | ||
53 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | ||
54 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
55 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
56 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
57 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
58 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
59 | >; | ||
60 | }; | ||
61 | |||
62 | mmc1_pins_hs: mmc1_pins_hs { | ||
63 | pinctrl-single,pins = < | ||
64 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ | ||
65 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
66 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
67 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
68 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
69 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
70 | >; | ||
71 | }; | ||
72 | |||
73 | mmc1_pins_sdr25: mmc1_pins_sdr25 { | ||
74 | pinctrl-single,pins = < | ||
75 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ | ||
76 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
77 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
78 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
79 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
80 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
81 | >; | ||
82 | }; | ||
83 | |||
84 | mmc1_pins_sdr50: mmc1_pins_sdr50 { | ||
85 | pinctrl-single,pins = < | ||
86 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ | ||
87 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
88 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
89 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
90 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
91 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
92 | >; | ||
93 | }; | ||
94 | |||
95 | mmc1_pins_ddr50: mmc1_pins_ddr50 { | ||
96 | pinctrl-single,pins = < | ||
97 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ | ||
98 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
99 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
100 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
101 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
102 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
103 | >; | ||
104 | }; | ||
105 | |||
106 | mmc1_pins_sdr104: mmc1_pins_sdr104 { | ||
107 | pinctrl-single,pins = < | ||
108 | DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ | ||
109 | DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
110 | DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
111 | DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
112 | DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
113 | DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
114 | >; | ||
115 | }; | ||
116 | |||
117 | mmc2_pins_default: mmc2_pins_default { | ||
118 | pinctrl-single,pins = < | ||
119 | DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
120 | DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
121 | DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
122 | DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
123 | DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
124 | DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
125 | DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
126 | DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
127 | DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
128 | DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
129 | >; | ||
130 | }; | ||
131 | |||
132 | mmc2_pins_hs: mmc2_pins_hs { | ||
133 | pinctrl-single,pins = < | ||
134 | DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
135 | DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
136 | DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
137 | DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
138 | DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
139 | DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
140 | DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
141 | DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
142 | DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
143 | DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
144 | >; | ||
145 | }; | ||
146 | |||
147 | mmc2_pins_ddr: mmc2_pins_ddr { | ||
148 | pinctrl-single,pins = < | ||
149 | DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
150 | DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
151 | DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
152 | DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
153 | DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
154 | DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
155 | DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
156 | DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
157 | DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
158 | DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
159 | >; | ||
160 | }; | ||
161 | |||
162 | mmc2_pins_hs200: mmc2_pins_hs200 { | ||
163 | pinctrl-single,pins = < | ||
164 | DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
165 | DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
166 | DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
167 | DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
168 | DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
169 | DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
170 | DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
171 | DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
172 | DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
173 | DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
174 | >; | ||
175 | }; | ||
176 | |||
177 | mmc3_pins_default: mmc3_pins_default { | ||
178 | pinctrl-single,pins = < | ||
179 | DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ | ||
180 | DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ | ||
181 | DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ | ||
182 | DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ | ||
183 | DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ | ||
184 | DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ | ||
185 | >; | ||
186 | }; | ||
187 | |||
188 | mmc3_pins_hs: mmc3_pins_hs { | ||
189 | pinctrl-single,pins = < | ||
190 | DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ | ||
191 | DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ | ||
192 | DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ | ||
193 | DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ | ||
194 | DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ | ||
195 | DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ | ||
196 | >; | ||
197 | }; | ||
198 | |||
199 | mmc3_pins_sdr12: mmc3_pins_sdr12 { | ||
200 | pinctrl-single,pins = < | ||
201 | DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ | ||
202 | DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ | ||
203 | DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ | ||
204 | DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ | ||
205 | DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ | ||
206 | DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ | ||
207 | >; | ||
208 | }; | ||
209 | |||
210 | mmc3_pins_sdr25: mmc3_pins_sdr25 { | ||
211 | pinctrl-single,pins = < | ||
212 | DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ | ||
213 | DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ | ||
214 | DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ | ||
215 | DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ | ||
216 | DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ | ||
217 | DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ | ||
218 | >; | ||
219 | }; | ||
220 | |||
221 | mmc3_pins_sdr50: mmc3_pins_sdr50 { | ||
222 | pinctrl-single,pins = < | ||
223 | DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ | ||
224 | DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ | ||
225 | DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ | ||
226 | DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ | ||
227 | DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ | ||
228 | DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ | ||
229 | >; | ||
230 | }; | ||
231 | |||
232 | mmc4_pins_default: mmc4_pins_default { | ||
233 | pinctrl-single,pins = < | ||
234 | DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ | ||
235 | DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ | ||
236 | DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ | ||
237 | DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ | ||
238 | DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ | ||
239 | DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ | ||
240 | >; | ||
241 | }; | ||
242 | |||
243 | mmc4_pins_sdr12: mmc4_pins_sdr12 { | ||
244 | pinctrl-single,pins = < | ||
245 | DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ | ||
246 | DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ | ||
247 | DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ | ||
248 | DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ | ||
249 | DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ | ||
250 | DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ | ||
251 | >; | ||
252 | }; | ||
253 | |||
254 | mmc4_pins_hs: mmc4_pins_hs { | ||
255 | pinctrl-single,pins = < | ||
256 | DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ | ||
257 | DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ | ||
258 | DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ | ||
259 | DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ | ||
260 | DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ | ||
261 | DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ | ||
262 | >; | ||
263 | }; | ||
264 | |||
265 | mmc4_pins_sdr25: mmc4_pins_sdr25 { | ||
266 | pinctrl-single,pins = < | ||
267 | DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ | ||
268 | DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ | ||
269 | DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ | ||
270 | DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ | ||
271 | DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ | ||
272 | DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ | ||
273 | >; | ||
274 | }; | ||
275 | }; | ||
276 | |||
277 | &dra7_iodelay_core { | ||
278 | |||
279 | /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ | ||
280 | mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { | ||
281 | pinctrl-single,pins = < | ||
282 | 0x618 (A_DELAY(489) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ | ||
283 | 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ | ||
284 | 0x630 (A_DELAY(374) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ | ||
285 | 0x63c (A_DELAY(31) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ | ||
286 | 0x648 (A_DELAY(56) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ | ||
287 | 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ | ||
288 | 0x620 (A_DELAY(1355) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ | ||
289 | 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ | ||
290 | 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ | ||
291 | 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ | ||
292 | 0x638 (A_DELAY(0) | G_DELAY(4)) /* CFG_MMC1_DAT0_OUT */ | ||
293 | 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ | ||
294 | 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ | ||
295 | 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ | ||
296 | 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ | ||
297 | 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ | ||
298 | 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ | ||
299 | >; | ||
300 | }; | ||
301 | |||
302 | /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ | ||
303 | mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { | ||
304 | pinctrl-single,pins = < | ||
305 | 0x620 (A_DELAY(892) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ | ||
306 | 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ | ||
307 | 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ | ||
308 | 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ | ||
309 | 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ | ||
310 | 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ | ||
311 | 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ | ||
312 | 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ | ||
313 | 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ | ||
314 | 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ | ||
315 | 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ | ||
316 | >; | ||
317 | }; | ||
318 | |||
319 | /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ | ||
320 | mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { | ||
321 | pinctrl-single,pins = < | ||
322 | 0x190 (A_DELAY(384) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ | ||
323 | 0x194 (A_DELAY(0) | G_DELAY(174)) /* CFG_GPMC_A19_OUT */ | ||
324 | 0x1a8 (A_DELAY(410) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ | ||
325 | 0x1ac (A_DELAY(85) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ | ||
326 | 0x1b4 (A_DELAY(468) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ | ||
327 | 0x1b8 (A_DELAY(139) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ | ||
328 | 0x1c0 (A_DELAY(676) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ | ||
329 | 0x1c4 (A_DELAY(69) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ | ||
330 | 0x1d0 (A_DELAY(1062) | G_DELAY(154)) /* CFG_GPMC_A23_OUT */ | ||
331 | 0x1d8 (A_DELAY(640) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ | ||
332 | 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ | ||
333 | 0x1e4 (A_DELAY(356) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ | ||
334 | 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ | ||
335 | 0x1f0 (A_DELAY(579) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ | ||
336 | 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ | ||
337 | 0x1fc (A_DELAY(435) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ | ||
338 | 0x200 (A_DELAY(36) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ | ||
339 | 0x364 (A_DELAY(759) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ | ||
340 | 0x368 (A_DELAY(72) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ | ||
341 | >; | ||
342 | }; | ||
343 | |||
344 | /* Corresponds to MMC3_MANUAL1 in datamanual */ | ||
345 | mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { | ||
346 | pinctrl-single,pins = < | ||
347 | 0x678 (A_DELAY(0) | G_DELAY(386)) /* CFG_MMC3_CLK_IN */ | ||
348 | 0x680 (A_DELAY(605) | G_DELAY(0)) /* CFG_MMC3_CLK_OUT */ | ||
349 | 0x684 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_IN */ | ||
350 | 0x688 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OEN */ | ||
351 | 0x68c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OUT */ | ||
352 | 0x690 (A_DELAY(171) | G_DELAY(0)) /* CFG_MMC3_DAT0_IN */ | ||
353 | 0x694 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OEN */ | ||
354 | 0x698 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OUT */ | ||
355 | 0x69c (A_DELAY(221) | G_DELAY(0)) /* CFG_MMC3_DAT1_IN */ | ||
356 | 0x6a0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OEN */ | ||
357 | 0x6a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OUT */ | ||
358 | 0x6a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_IN */ | ||
359 | 0x6ac (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OEN */ | ||
360 | 0x6b0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OUT */ | ||
361 | 0x6b4 (A_DELAY(474) | G_DELAY(0)) /* CFG_MMC3_DAT3_IN */ | ||
362 | 0x6b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OEN */ | ||
363 | 0x6bc (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OUT */ | ||
364 | >; | ||
365 | }; | ||
366 | |||
367 | /* Corresponds to MMC3_MANUAL2 in datamanual */ | ||
368 | mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { | ||
369 | pinctrl-single,pins = < | ||
370 | 0x678 (A_DELAY(852) | G_DELAY(0)) /* CFG_MMC3_CLK_IN */ | ||
371 | 0x680 (A_DELAY(94) | G_DELAY(0)) /* CFG_MMC3_CLK_OUT */ | ||
372 | 0x684 (A_DELAY(122) | G_DELAY(0)) /* CFG_MMC3_CMD_IN */ | ||
373 | 0x688 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OEN */ | ||
374 | 0x68c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_CMD_OUT */ | ||
375 | 0x690 (A_DELAY(91) | G_DELAY(0)) /* CFG_MMC3_DAT0_IN */ | ||
376 | 0x694 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OEN */ | ||
377 | 0x698 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT0_OUT */ | ||
378 | 0x69c (A_DELAY(57) | G_DELAY(0)) /* CFG_MMC3_DAT1_IN */ | ||
379 | 0x6a0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OEN */ | ||
380 | 0x6a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT1_OUT */ | ||
381 | 0x6a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_IN */ | ||
382 | 0x6ac (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OEN */ | ||
383 | 0x6b0 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT2_OUT */ | ||
384 | 0x6b4 (A_DELAY(375) | G_DELAY(0)) /* CFG_MMC3_DAT3_IN */ | ||
385 | 0x6b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OEN */ | ||
386 | 0x6bc (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC3_DAT3_OUT */ | ||
387 | >; | ||
388 | }; | ||
389 | |||
390 | /* Corresponds to MMC4_MANUAL1 in datamanual */ | ||
391 | mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { | ||
392 | pinctrl-single,pins = < | ||
393 | 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */ | ||
394 | 0x848 (A_DELAY(1147) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */ | ||
395 | 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */ | ||
396 | 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */ | ||
397 | 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */ | ||
398 | 0x870 (A_DELAY(2165) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ | ||
399 | 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ | ||
400 | 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ | ||
401 | 0x87c (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_RTSN_IN */ | ||
402 | 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ | ||
403 | 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ | ||
404 | 0x888 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_RXD_IN */ | ||
405 | 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ | ||
406 | 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ | ||
407 | 0x894 (A_DELAY(2172) | G_DELAY(44)) /* CFG_UART2_TXD_IN */ | ||
408 | 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */ | ||
409 | 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */ | ||
410 | >; | ||
411 | }; | ||
412 | |||
413 | /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ | ||
414 | mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { | ||
415 | pinctrl-single,pins = < | ||
416 | 0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */ | ||
417 | 0x848 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */ | ||
418 | 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */ | ||
419 | 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */ | ||
420 | 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */ | ||
421 | 0x870 (A_DELAY(785) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ | ||
422 | 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ | ||
423 | 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ | ||
424 | 0x87c (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */ | ||
425 | 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ | ||
426 | 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ | ||
427 | 0x888 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_RXD_IN */ | ||
428 | 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ | ||
429 | 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ | ||
430 | 0x894 (A_DELAY(835) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ | ||
431 | 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */ | ||
432 | 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */ | ||
433 | >; | ||
434 | }; | ||
435 | }; | ||