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Diffstat (limited to 'arch/arm/mach-mx5/clock-mx51-mx53.c')
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c78
1 files changed, 71 insertions, 7 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index f7bf996f463b..4cb276977190 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -15,6 +15,7 @@
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/clkdev.h> 17#include <linux/clkdev.h>
18#include <linux/of.h>
18 19
19#include <asm/div64.h> 20#include <asm/div64.h>
20 21
@@ -1280,9 +1281,9 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1280 NULL, NULL, &ipg_clk, &gpt_ipg_clk); 1281 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
1281 1282
1282DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET, 1283DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
1283 NULL, NULL, &ipg_clk, NULL); 1284 NULL, NULL, &ipg_perclk, NULL);
1284DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET, 1285DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
1285 NULL, NULL, &ipg_clk, NULL); 1286 NULL, NULL, &ipg_perclk, NULL);
1286 1287
1287/* I2C */ 1288/* I2C */
1288DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, 1289DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -1401,6 +1402,22 @@ static struct clk esdhc4_mx53_clk = {
1401 .secondary = &esdhc4_ipg_clk, 1402 .secondary = &esdhc4_ipg_clk,
1402}; 1403};
1403 1404
1405static struct clk sata_clk = {
1406 .parent = &ipg_clk,
1407 .enable = _clk_max_enable,
1408 .enable_reg = MXC_CCM_CCGR4,
1409 .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
1410 .disable = _clk_max_disable,
1411};
1412
1413static struct clk ahci_phy_clk = {
1414 .parent = &usb_phy1_clk,
1415};
1416
1417static struct clk ahci_dma_clk = {
1418 .parent = &ahb_clk,
1419};
1420
1404DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); 1421DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1405DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); 1422DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1406DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); 1423DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1418,6 +1435,10 @@ DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
1418DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, 1435DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
1419 NULL, NULL, &pll3_sw_clk, NULL); 1436 NULL, NULL, &pll3_sw_clk, NULL);
1420 1437
1438/* PATA */
1439DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
1440 NULL, NULL, &ipg_clk, &spba_clk);
1441
1421#define _REGISTER_CLOCK(d, n, c) \ 1442#define _REGISTER_CLOCK(d, n, c) \
1422 { \ 1443 { \
1423 .dev_id = d, \ 1444 .dev_id = d, \
@@ -1474,6 +1495,7 @@ static struct clk_lookup mx51_lookups[] = {
1474 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) 1495 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1475 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) 1496 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1476 _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) 1497 _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
1498 _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1477}; 1499};
1478 1500
1479static struct clk_lookup mx53_lookups[] = { 1501static struct clk_lookup mx53_lookups[] = {
@@ -1507,6 +1529,10 @@ static struct clk_lookup mx53_lookups[] = {
1507 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 1529 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1508 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) 1530 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1509 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) 1531 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1532 _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1533 _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
1534 _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
1535 _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
1510}; 1536};
1511 1537
1512static void clk_tree_init(void) 1538static void clk_tree_init(void)
@@ -1548,9 +1574,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1548 clk_enable(&main_bus_clk); 1574 clk_enable(&main_bus_clk);
1549 1575
1550 clk_enable(&iim_clk); 1576 clk_enable(&iim_clk);
1551 mx51_revision(); 1577 imx_print_silicon_rev("i.MX51", mx51_revision());
1552 clk_disable(&iim_clk); 1578 clk_disable(&iim_clk);
1553 mx51_display_revision();
1554 1579
1555 /* move usb_phy_clk to 24MHz */ 1580 /* move usb_phy_clk to 24MHz */
1556 clk_set_parent(&usb_phy1_clk, &osc_clk); 1581 clk_set_parent(&usb_phy1_clk, &osc_clk);
@@ -1568,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1568 1593
1569 /* System timer */ 1594 /* System timer */
1570 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 1595 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1571 MX51_MXC_INT_GPT); 1596 MX51_INT_GPT);
1572 return 0; 1597 return 0;
1573} 1598}
1574 1599
@@ -1592,9 +1617,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1592 clk_enable(&main_bus_clk); 1617 clk_enable(&main_bus_clk);
1593 1618
1594 clk_enable(&iim_clk); 1619 clk_enable(&iim_clk);
1595 mx53_revision(); 1620 imx_print_silicon_rev("i.MX53", mx53_revision());
1596 clk_disable(&iim_clk); 1621 clk_disable(&iim_clk);
1597 mx53_display_revision();
1598 1622
1599 /* Set SDHC parents to be PLL2 */ 1623 /* Set SDHC parents to be PLL2 */
1600 clk_set_parent(&esdhc1_clk, &pll2_sw_clk); 1624 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
@@ -1609,3 +1633,43 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1609 MX53_INT_GPT); 1633 MX53_INT_GPT);
1610 return 0; 1634 return 0;
1611} 1635}
1636
1637#ifdef CONFIG_OF
1638static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
1639 unsigned long *ckih1, unsigned long *ckih2)
1640{
1641 struct device_node *np;
1642
1643 /* retrieve the freqency of fixed clocks from device tree */
1644 for_each_compatible_node(np, NULL, "fixed-clock") {
1645 u32 rate;
1646 if (of_property_read_u32(np, "clock-frequency", &rate))
1647 continue;
1648
1649 if (of_device_is_compatible(np, "fsl,imx-ckil"))
1650 *ckil = rate;
1651 else if (of_device_is_compatible(np, "fsl,imx-osc"))
1652 *osc = rate;
1653 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
1654 *ckih1 = rate;
1655 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
1656 *ckih2 = rate;
1657 }
1658}
1659
1660int __init mx51_clocks_init_dt(void)
1661{
1662 unsigned long ckil, osc, ckih1, ckih2;
1663
1664 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1665 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
1666}
1667
1668int __init mx53_clocks_init_dt(void)
1669{
1670 unsigned long ckil, osc, ckih1, ckih2;
1671
1672 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1673 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
1674}
1675#endif