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Diffstat (limited to 'arch/arm/mach-omap2/include/mach/debug-macro.S')
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S93
1 files changed, 42 insertions, 51 deletions
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 48adfe9fe4f3..cdfc2a1f0e75 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,15 +13,10 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
18#include <plat/serial.h> 16#include <plat/serial.h>
19 17
20#define UART_OFFSET(addr) ((addr) & 0x00ffffff) 18#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
21 19
22#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
23#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
24
25 .pushsection .data 20 .pushsection .data
26omap_uart_phys: .word 0 21omap_uart_phys: .word 0
27omap_uart_virt: .word 0 22omap_uart_virt: .word 0
@@ -34,26 +29,25 @@ omap_uart_lsr: .word 0
34 * the desired UART phys and virt addresses temporarily into 29 * the desired UART phys and virt addresses temporarily into
35 * the omap_uart_phys and omap_uart_virt above. 30 * the omap_uart_phys and omap_uart_virt above.
36 */ 31 */
37 .macro addruart, rp, rv 32 .macro addruart, rp, rv, tmp
38 33
39 /* Use omap_uart_phys/virt if already configured */ 34 /* Use omap_uart_phys/virt if already configured */
4010: mrc p15, 0, \rp, c1, c0 3510: adr \rp, 99f @ get effective addr of 99f
41 tst \rp, #1 @ MMU enabled? 36 ldr \rv, [\rp] @ get absolute addr of 99f
42 ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled 37 sub \rv, \rv, \rp @ offset between the two
43 ldrne \rp, =omap_uart_phys @ MMU enabled 38 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
44 add \rv, \rp, #4 @ omap_uart_virt 39 sub \tmp, \rp, \rv @ make it effective
45 ldr \rp, [\rp, #0] 40 ldr \rp, [\tmp, #0] @ omap_uart_phys
46 ldr \rv, [\rv, #0] 41 ldr \rv, [\tmp, #4] @ omap_uart_virt
47 cmp \rp, #0 @ is port configured? 42 cmp \rp, #0 @ is port configured?
48 cmpne \rv, #0 43 cmpne \rv, #0
49 bne 99f @ already configured 44 bne 100f @ already configured
50 45
51 /* Check the debug UART configuration set in uncompress.h */ 46 /* Check the debug UART configuration set in uncompress.h */
52 mrc p15, 0, \rp, c1, c0 47 mov \rp, pc
53 tst \rp, #1 @ MMU enabled? 48 ldr \rv, =OMAP_UART_INFO_OFS
54 ldreq \rp, =OMAP_UART_INFO @ MMU not enabled 49 and \rp, \rp, #0xff000000
55 ldrne \rp, =omap_uart_p2v(OMAP_UART_INFO) @ MMU enabled 50 ldr \rp, [\rp, \rv]
56 ldr \rp, [\rp, #0]
57 51
58 /* Select the UART to use based on the UART1 scratchpad value */ 52 /* Select the UART to use based on the UART1 scratchpad value */
59 cmp \rp, #0 @ no port configured? 53 cmp \rp, #0 @ no port configured?
@@ -72,11 +66,11 @@ omap_uart_lsr: .word 0
72 beq 34f @ configure OMAP3UART4 66 beq 34f @ configure OMAP3UART4
73 cmp \rp, #OMAP4UART4 @ only on 44xx 67 cmp \rp, #OMAP4UART4 @ only on 44xx
74 beq 44f @ configure OMAP4UART4 68 beq 44f @ configure OMAP4UART4
75 cmp \rp, #TI816XUART1 @ ti816x UART offsets different 69 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
76 beq 81f @ configure UART1 70 beq 81f @ configure UART1
77 cmp \rp, #TI816XUART2 @ ti816x UART offsets different 71 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
78 beq 82f @ configure UART2 72 beq 82f @ configure UART2
79 cmp \rp, #TI816XUART3 @ ti816x UART offsets different 73 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
80 beq 83f @ configure UART3 74 beq 83f @ configure UART3
81 cmp \rp, #ZOOM_UART @ only on zoom2/3 75 cmp \rp, #ZOOM_UART @ only on zoom2/3
82 beq 95f @ configure ZOOM_UART 76 beq 95f @ configure ZOOM_UART
@@ -100,56 +94,53 @@ omap_uart_lsr: .word 0
100 b 98f 94 b 98f
10144: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) 9544: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
102 b 98f 96 b 98f
10381: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) 9781: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
104 b 98f 98 b 98f
10582: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) 9982: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
106 b 98f 100 b 98f
10783: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) 10183: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
108 b 98f 102 b 98f
103
10995: ldr \rp, =ZOOM_UART_BASE 10495: ldr \rp, =ZOOM_UART_BASE
110 mrc p15, 0, \rv, c1, c0 105 str \rp, [\tmp, #0] @ omap_uart_phys
111 tst \rv, #1 @ MMU enabled?
112 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
113 ldrne \rv, =omap_uart_phys @ MMU enabled
114 str \rp, [\rv, #0]
115 ldr \rp, =ZOOM_UART_VIRT 106 ldr \rp, =ZOOM_UART_VIRT
116 add \rv, \rv, #4 @ omap_uart_virt 107 str \rp, [\tmp, #4] @ omap_uart_virt
117 str \rp, [\rv, #0]
118 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT) 108 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
119 add \rv, \rv, #4 @ omap_uart_lsr 109 str \rp, [\tmp, #8] @ omap_uart_lsr
120 str \rp, [\rv, #0]
121 b 10b 110 b 10b
122 111
123 /* Store both phys and virt address for the uart */ 112 /* Store both phys and virt address for the uart */
12498: add \rp, \rp, #0x48000000 @ phys base 11398: add \rp, \rp, #0x48000000 @ phys base
125 mrc p15, 0, \rv, c1, c0 114 str \rp, [\tmp, #0] @ omap_uart_phys
126 tst \rv, #1 @ MMU enabled?
127 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
128 ldrne \rv, =omap_uart_phys @ MMU enabled
129 str \rp, [\rv, #0]
130 sub \rp, \rp, #0x48000000 @ phys base 115 sub \rp, \rp, #0x48000000 @ phys base
131 add \rp, \rp, #0xfa000000 @ virt base 116 add \rp, \rp, #0xfa000000 @ virt base
132 add \rv, \rv, #4 @ omap_uart_virt 117 str \rp, [\tmp, #4] @ omap_uart_virt
133 str \rp, [\rv, #0]
134 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) 118 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
135 add \rv, \rv, #4 @ omap_uart_lsr 119 str \rp, [\tmp, #8] @ omap_uart_lsr
136 str \rp, [\rv, #0]
137 120
138 b 10b 121 b 10b
13999: 122
123 .align
12499: .word .
125 .word omap_uart_phys
126 .ltorg
127
128100: /* Pass the UART_LSR reg address */
129 ldr \tmp, [\tmp, #8] @ omap_uart_lsr
130 add \rp, \rp, \tmp
131 add \rv, \rv, \tmp
140 .endm 132 .endm
141 133
142 .macro senduart,rd,rx 134 .macro senduart,rd,rx
143 strb \rd, [\rx] 135 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
136 bic \rx, \rx, #0xff @ get base (THR) reg address
137 strb \rd, [\rx] @ send lower byte of rd
138 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
139 bic \rd, \rd, #(0xff << 24) @ restore original rd
144 .endm 140 .endm
145 141
146 .macro busyuart,rd,rx 142 .macro busyuart,rd,rx
1471001: mrc p15, 0, \rd, c1, c0 1431001: ldrb \rd, [\rx] @ rx contains UART_LSR address
148 tst \rd, #1 @ MMU enabled?
149 ldreq \rd, =omap_uart_v2p(omap_uart_lsr) @ MMU disabled
150 ldrne \rd, =omap_uart_lsr @ MMU enabled
151 ldr \rd, [\rd, #0]
152 ldrb \rd, [\rx, \rd]
153 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 144 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
154 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 145 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
155 bne 1001b 146 bne 1001b