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-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h224
1 files changed, 127 insertions, 97 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 359b83348aed..90b50984cd2e 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -1,132 +1,162 @@
1 /* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver header 2 * OMAP4XXX L3 Interconnect error handling driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com> 6 * sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25 25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3 26#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31) 27#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2 28#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0 29#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0 30#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0 31#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1 32#define L3_DEBUG_ERROR 0x1
39 33
40u32 l3_flagmux[L3_MODULES] = { 34/* L3 TARG register offsets */
41 0x50C, 35#define L3_TARG_STDERRLOG_MAIN 0x48
42 0x100C, 36#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
43 0X020C 37#define L3_TARG_STDERRLOG_MSTADDR 0x68
38#define L3_FLAGMUX_REGERR0 0xc
39
40#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
41
42static u32 l3_flagmux[L3_MODULES] = {
43 0x500,
44 0x1000,
45 0X0200
44}; 46};
45 47
46/* 48/* L3 Target standard Error register offsets */
47 * L3 Target standard Error register offsets 49static u32 l3_targ_inst_clk1[] = {
48 */ 50 0x100, /* DMM1 */
49u32 l3_targ_stderrlog_main_clk1[] = { 51 0x200, /* DMM2 */
50 0x148, /* DMM1 */ 52 0x300, /* ABE */
51 0x248, /* DMM2 */ 53 0x400, /* L4CFG */
52 0x348, /* ABE */ 54 0x600 /* CLK2 PWR DISC */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55}; 55};
56 56
57u32 l3_targ_stderrlog_main_clk2[] = { 57static u32 l3_targ_inst_clk2[] = {
58 0x548, /* CORTEX M3 */ 58 0x500, /* CORTEX M3 */
59 0x348, /* DSS */ 59 0x300, /* DSS */
60 0x148, /* GPMC */ 60 0x100, /* GPMC */
61 0x448, /* ISS */ 61 0x400, /* ISS */
62 0x748, /* IVAHD */ 62 0x700, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/ 63 0xD00, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/ 64 0x900, /* L4 PER0*/
65 0x248, /* OCMRAM */ 65 0x200, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/ 66 0x100, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */ 67 0x600, /* SGX */
68 0x848, /* SL2 */ 68 0x800, /* SL2 */
69 0x1648, /* C2C */ 69 0x1600, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ 70 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/ 71 0xF00, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/ 72 0xE00, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */ 73 0xC00, /* L4 PER3 */
74 0xA48, /* L4 PER1*/ 74 0xA00, /* L4 PER1*/
75 0xB48 /* L4 PER2*/ 75 0xB00 /* L4 PER2*/
76}; 76};
77 77
78u32 l3_targ_stderrlog_main_clk3[] = { 78static u32 l3_targ_inst_clk3[] = {
79 0x0148 /* EMUSS */ 79 0x0100 /* EMUSS */
80}; 80};
81 81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { 82static struct l3_masters_data {
83 u32 id;
84 char name[10];
85} l3_masters[] = {
86 { 0x0 , "MPU"},
87 { 0x10, "CS_ADP"},
88 { 0x14, "xxx"},
89 { 0x20, "DSP"},
90 { 0x30, "IVAHD"},
91 { 0x40, "ISS"},
92 { 0x44, "DucatiM3"},
93 { 0x48, "FaceDetect"},
94 { 0x50, "SDMA_Rd"},
95 { 0x54, "SDMA_Wr"},
96 { 0x58, "xxx"},
97 { 0x5C, "xxx"},
98 { 0x60, "SGX"},
99 { 0x70, "DSS"},
100 { 0x80, "C2C"},
101 { 0x88, "xxx"},
102 { 0x8C, "xxx"},
103 { 0x90, "HSI"},
104 { 0xA0, "MMC1"},
105 { 0xA4, "MMC2"},
106 { 0xA8, "MMC6"},
107 { 0xB0, "UNIPRO1"},
108 { 0xC0, "USBHOSTHS"},
109 { 0xC4, "USBOTGHS"},
110 { 0xC8, "USBHOSTFS"}
111};
112
113static char *l3_targ_inst_name[L3_MODULES][18] = {
83 { 114 {
84 "DMM1", 115 "DMM1",
85 "DMM2", 116 "DMM2",
86 "ABE", 117 "ABE",
87 "L4CFG", 118 "L4CFG",
88 "CLK2 PWR DISC", 119 "CLK2 PWR DISC",
89 }, 120 },
90 { 121 {
91 "CORTEX M3" , 122 "CORTEX M3" ,
92 "DSS ", 123 "DSS ",
93 "GPMC ", 124 "GPMC ",
94 "ISS ", 125 "ISS ",
95 "IVAHD ", 126 "IVAHD ",
96 "AES1", 127 "AES1",
97 "L4 PER0", 128 "L4 PER0",
98 "OCMRAM ", 129 "OCMRAM ",
99 "GPMC sERROR", 130 "GPMC sERROR",
100 "SGX ", 131 "SGX ",
101 "SL2 ", 132 "SL2 ",
102 "C2C ", 133 "C2C ",
103 "PWR DISC CLK1", 134 "PWR DISC CLK1",
104 "SHA1", 135 "SHA1",
105 "AES2", 136 "AES2",
106 "L4 PER3", 137 "L4 PER3",
107 "L4 PER1", 138 "L4 PER1",
108 "L4 PER2", 139 "L4 PER2",
109 }, 140 },
110 { 141 {
111 "EMUSS", 142 "EMUSS",
112 }, 143 },
113}; 144};
114 145
115u32 *l3_targ[L3_MODULES] = { 146static u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1, 147 l3_targ_inst_clk1,
117 l3_targ_stderrlog_main_clk2, 148 l3_targ_inst_clk2,
118 l3_targ_stderrlog_main_clk3, 149 l3_targ_inst_clk3,
119}; 150};
120 151
121struct omap4_l3 { 152struct omap4_l3 {
122 struct device *dev; 153 struct device *dev;
123 struct clk *ick; 154 struct clk *ick;
124 155
125 /* memory base */ 156 /* memory base */
126 void __iomem *l3_base[4]; 157 void __iomem *l3_base[L3_MODULES];
127 158
128 int debug_irq; 159 int debug_irq;
129 int app_irq; 160 int app_irq;
130}; 161};
131
132#endif 162#endif
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