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-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h164
1 files changed, 82 insertions, 82 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
index ba2ed9a850cc..4f3cebca4179 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver header 2 * OMAP3XXX L3 Interconnect Driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com> 7 * sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26 26
@@ -40,7 +40,7 @@
40#define L3_SI_CONTROL 0x020 40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510 41#define L3_SI_FLAG_STATUS_0 0x510
42 42
43const u64 shift = 1; 43static const u64 shift = 1;
44 44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0) 45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1) 46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
@@ -78,32 +78,32 @@ const u64 shift = 1;
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) 78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) 79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80 80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ 81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \ 82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \ 83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \ 84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \ 85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \ 86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \ 87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \ 88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \ 89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \ 90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \ 91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \ 92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \ 93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \ 94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \ 95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \ 96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \ 97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \ 98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \ 99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \ 100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \ 101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \ 102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \ 103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \ 104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \ 105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \ 106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ) 107 | L3_STATUS_0_MAD2DTA_REQ)
108 108
109#define L3_SI_FLAG_STATUS_1 0x530 109#define L3_SI_FLAG_STATUS_1 0x530
@@ -137,19 +137,19 @@ const u64 shift = 1;
137 137
138enum omap3_l3_initiator_id { 138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */ 139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29, 140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */ 141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28, 142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */ 143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27, 144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26, 145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25, 146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24, 147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23, 148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/ 149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22, 150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21, 151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20, 152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */ 153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19, 154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18, 155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
@@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15, 158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14, 159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */ 160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13, 161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */ 162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12, 163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11, 164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10, 165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */ 166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9, 167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */ 168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8, 169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7, 170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */ 171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6, 172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5, 173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4, 174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3, 175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */ 176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2, 177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */ 178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1, 179 OMAP_L3_USBHOST = 1,
180}; 180};
181 181
182enum omap3_l3_code { 182enum omap3_l3_code {
@@ -192,21 +192,21 @@ enum omap3_l3_code {
192}; 192};
193 193
194struct omap3_l3 { 194struct omap3_l3 {
195 struct device *dev; 195 struct device *dev;
196 struct clk *ick; 196 struct clk *ick;
197 197
198 /* memory base*/ 198 /* memory base*/
199 void __iomem *rt; 199 void __iomem *rt;
200 200
201 int debug_irq; 201 int debug_irq;
202 int app_irq; 202 int app_irq;
203 203
204 /* true when and inband functional error occurs */ 204 /* true when and inband functional error occurs */
205 unsigned inband:1; 205 unsigned inband:1;
206}; 206};
207 207
208/* offsets for l3 agents in order with the Flag status register */ 208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = { 209static unsigned int omap3_l3_app_bases[] = {
210 /* MPU IA */ 210 /* MPU IA */
211 0x1400, 211 0x1400,
212 0x1400, 212 0x1400,
@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
305 0, 305 0,
306}; 306};
307 307
308unsigned int __iomem omap3_l3_debug_bases[] = { 308static unsigned int omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */ 309 /* MPU DATA IA */
310 0x1400, 310 0x1400,
311 /* RESERVED */ 311 /* RESERVED */
@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
321 /* REST RESERVED */ 321 /* REST RESERVED */
322}; 322};
323 323
324u32 *omap3_l3_bases[] = { 324static u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases, 325 omap3_l3_app_bases,
326 omap3_l3_debug_bases, 326 omap3_l3_debug_bases,
327}; 327};
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