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Diffstat (limited to 'arch/arm/mach-s5p64x0/clock-s5p6450.c')
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c168
1 files changed, 106 insertions, 62 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d9dc16cde109..dae6a13f43bb 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -17,7 +17,7 @@
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/sysdev.h> 20#include <linux/device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
@@ -31,7 +31,8 @@
31#include <plat/pll.h> 31#include <plat/pll.h>
32#include <plat/s5p-clock.h> 32#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h> 33#include <plat/clock-clksrc.h>
34#include <plat/s5p6450.h> 34
35#include "common.h"
35 36
36static struct clksrc_clk clk_mout_dpll = { 37static struct clksrc_clk clk_mout_dpll = {
37 .clk = { 38 .clk = {
@@ -179,7 +180,8 @@ static struct clk init_clocks_off[] = {
179 .enable = s5p64x0_hclk0_ctrl, 180 .enable = s5p64x0_hclk0_ctrl,
180 .ctrlbit = (1 << 3), 181 .ctrlbit = (1 << 3),
181 }, { 182 }, {
182 .name = "pdma", 183 .name = "dma",
184 .devname = "dma-pl330",
183 .parent = &clk_hclk_low.clk, 185 .parent = &clk_hclk_low.clk,
184 .enable = s5p64x0_hclk0_ctrl, 186 .enable = s5p64x0_hclk0_ctrl,
185 .ctrlbit = (1 << 12), 187 .ctrlbit = (1 << 12),
@@ -412,65 +414,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
412static struct clksrc_clk clksrcs[] = { 414static struct clksrc_clk clksrcs[] = {
413 { 415 {
414 .clk = { 416 .clk = {
415 .name = "sclk_mmc",
416 .devname = "s3c-sdhci.0",
417 .ctrlbit = (1 << 24),
418 .enable = s5p64x0_sclk_ctrl,
419 },
420 .sources = &clkset_group2,
421 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
422 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
423 }, {
424 .clk = {
425 .name = "sclk_mmc",
426 .devname = "s3c-sdhci.1",
427 .ctrlbit = (1 << 25),
428 .enable = s5p64x0_sclk_ctrl,
429 },
430 .sources = &clkset_group2,
431 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
432 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
433 }, {
434 .clk = {
435 .name = "sclk_mmc",
436 .devname = "s3c-sdhci.2",
437 .ctrlbit = (1 << 26),
438 .enable = s5p64x0_sclk_ctrl,
439 },
440 .sources = &clkset_group2,
441 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
442 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
443 }, {
444 .clk = {
445 .name = "uclk1",
446 .ctrlbit = (1 << 5),
447 .enable = s5p64x0_sclk_ctrl,
448 },
449 .sources = &clkset_uart,
450 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
451 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
452 }, {
453 .clk = {
454 .name = "sclk_spi",
455 .devname = "s3c64xx-spi.0",
456 .ctrlbit = (1 << 20),
457 .enable = s5p64x0_sclk_ctrl,
458 },
459 .sources = &clkset_group2,
460 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
461 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
462 }, {
463 .clk = {
464 .name = "sclk_spi",
465 .devname = "s3c64xx-spi.1",
466 .ctrlbit = (1 << 21),
467 .enable = s5p64x0_sclk_ctrl,
468 },
469 .sources = &clkset_group2,
470 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
471 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
472 }, {
473 .clk = {
474 .name = "sclk_fimc", 417 .name = "sclk_fimc",
475 .ctrlbit = (1 << 10), 418 .ctrlbit = (1 << 10),
476 .enable = s5p64x0_sclk_ctrl, 419 .enable = s5p64x0_sclk_ctrl,
@@ -535,6 +478,97 @@ static struct clksrc_clk clksrcs[] = {
535 }, 478 },
536}; 479};
537 480
481static struct clksrc_clk clk_sclk_mmc0 = {
482 .clk = {
483 .name = "sclk_mmc",
484 .devname = "s3c-sdhci.0",
485 .ctrlbit = (1 << 24),
486 .enable = s5p64x0_sclk_ctrl,
487 },
488 .sources = &clkset_group2,
489 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
490 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
491};
492
493static struct clksrc_clk clk_sclk_mmc1 = {
494 .clk = {
495 .name = "sclk_mmc",
496 .devname = "s3c-sdhci.1",
497 .ctrlbit = (1 << 25),
498 .enable = s5p64x0_sclk_ctrl,
499 },
500 .sources = &clkset_group2,
501 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
502 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
503};
504
505static struct clksrc_clk clk_sclk_mmc2 = {
506 .clk = {
507 .name = "sclk_mmc",
508 .devname = "s3c-sdhci.2",
509 .ctrlbit = (1 << 26),
510 .enable = s5p64x0_sclk_ctrl,
511 },
512 .sources = &clkset_group2,
513 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
514 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
515};
516
517static struct clksrc_clk clk_sclk_uclk = {
518 .clk = {
519 .name = "uclk1",
520 .ctrlbit = (1 << 5),
521 .enable = s5p64x0_sclk_ctrl,
522 },
523 .sources = &clkset_uart,
524 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
525 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
526};
527
528static struct clksrc_clk clk_sclk_spi0 = {
529 .clk = {
530 .name = "sclk_spi",
531 .devname = "s3c64xx-spi.0",
532 .ctrlbit = (1 << 20),
533 .enable = s5p64x0_sclk_ctrl,
534 },
535 .sources = &clkset_group2,
536 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
537 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
538};
539
540static struct clksrc_clk clk_sclk_spi1 = {
541 .clk = {
542 .name = "sclk_spi",
543 .devname = "s3c64xx-spi.1",
544 .ctrlbit = (1 << 21),
545 .enable = s5p64x0_sclk_ctrl,
546 },
547 .sources = &clkset_group2,
548 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
549 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
550};
551
552static struct clksrc_clk *clksrc_cdev[] = {
553 &clk_sclk_uclk,
554 &clk_sclk_spi0,
555 &clk_sclk_spi1,
556 &clk_sclk_mmc0,
557 &clk_sclk_mmc1,
558 &clk_sclk_mmc2,
559};
560
561static struct clk_lookup s5p6450_clk_lookup[] = {
562 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
563 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
564 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
565 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
566 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
567 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
568 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
569 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
570};
571
538/* Clock initialization code */ 572/* Clock initialization code */
539static struct clksrc_clk *sysclks[] = { 573static struct clksrc_clk *sysclks[] = {
540 &clk_mout_apll, 574 &clk_mout_apll,
@@ -553,6 +587,11 @@ static struct clksrc_clk *sysclks[] = {
553 &clk_sclk_audio0, 587 &clk_sclk_audio0,
554}; 588};
555 589
590static struct clk dummy_apb_pclk = {
591 .name = "apb_pclk",
592 .id = -1,
593};
594
556void __init_or_cpufreq s5p6450_setup_clocks(void) 595void __init_or_cpufreq s5p6450_setup_clocks(void)
557{ 596{
558 struct clk *xtal_clk; 597 struct clk *xtal_clk;
@@ -628,9 +667,14 @@ void __init s5p6450_register_clocks(void)
628 667
629 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 668 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
630 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 669 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
670 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
671 s3c_register_clksrc(clksrc_cdev[ptr], 1);
631 672
632 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 673 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
633 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 674 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
675 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
676
677 s3c24xx_register_clock(&dummy_apb_pclk);
634 678
635 s3c_pwmclk_init(); 679 s3c_pwmclk_init();
636} 680}
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