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Diffstat (limited to 'arch/arm64/mm/cache.S')
-rw-r--r--arch/arm64/mm/cache.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 07d7352d7c38..3be2cda5dbda 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -23,6 +23,7 @@
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24#include <asm/cpufeature.h> 24#include <asm/cpufeature.h>
25#include <asm/alternative.h> 25#include <asm/alternative.h>
26#include <asm/uaccess.h>
26 27
27/* 28/*
28 * flush_icache_range(start,end) 29 * flush_icache_range(start,end)
@@ -48,6 +49,7 @@ ENTRY(flush_icache_range)
48 * - end - virtual end address of region 49 * - end - virtual end address of region
49 */ 50 */
50ENTRY(__flush_cache_user_range) 51ENTRY(__flush_cache_user_range)
52 uaccess_ttbr0_enable x2, x3
51 dcache_line_size x2, x3 53 dcache_line_size x2, x3
52 sub x3, x2, #1 54 sub x3, x2, #1
53 bic x4, x0, x3 55 bic x4, x0, x3
@@ -69,10 +71,12 @@ USER(9f, ic ivau, x4 ) // invalidate I line PoU
69 dsb ish 71 dsb ish
70 isb 72 isb
71 mov x0, #0 73 mov x0, #0
741:
75 uaccess_ttbr0_disable x1
72 ret 76 ret
739: 779:
74 mov x0, #-EFAULT 78 mov x0, #-EFAULT
75 ret 79 b 1b
76ENDPROC(flush_icache_range) 80ENDPROC(flush_icache_range)
77ENDPROC(__flush_cache_user_range) 81ENDPROC(__flush_cache_user_range)
78 82