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-rw-r--r--arch/c6x/include/asm/cache.h90
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
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1/*
2 * Port on Texas Instruments TMS320C6x architecture
3 *
4 * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ASM_C6X_CACHE_H
12#define _ASM_C6X_CACHE_H
13
14#include <linux/irqflags.h>
15
16/*
17 * Cache line size
18 */
19#define L1D_CACHE_BYTES 64
20#define L1P_CACHE_BYTES 32
21#define L2_CACHE_BYTES 128
22
23/*
24 * L2 used as cache
25 */
26#define L2MODE_SIZE L2MODE_256K_CACHE
27
28/*
29 * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
30 * the L2 line size
31 */
32#define L1_CACHE_BYTES L2_CACHE_BYTES
33
34#define L2_CACHE_ALIGN_LOW(x) \
35 (((x) & ~(L2_CACHE_BYTES - 1)))
36#define L2_CACHE_ALIGN_UP(x) \
37 (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
38#define L2_CACHE_ALIGN_CNT(x) \
39 (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
40
41#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
42#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
43
44/*
45 * This is the granularity of hardware cacheability control.
46 */
47#define CACHEABILITY_ALIGN 0x01000000
48
49/*
50 * Align a physical address to MAR regions
51 */
52#define CACHE_REGION_START(v) \
53 (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
54#define CACHE_REGION_END(v) \
55 (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
56
57extern void __init c6x_cache_init(void);
58
59extern void enable_caching(unsigned long start, unsigned long end);
60extern void disable_caching(unsigned long start, unsigned long end);
61
62extern void L1_cache_off(void);
63extern void L1_cache_on(void);
64
65extern void L1P_cache_global_invalidate(void);
66extern void L1D_cache_global_invalidate(void);
67extern void L1D_cache_global_writeback(void);
68extern void L1D_cache_global_writeback_invalidate(void);
69extern void L2_cache_set_mode(unsigned int mode);
70extern void L2_cache_global_writeback_invalidate(void);
71extern void L2_cache_global_writeback(void);
72
73extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
74extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
75extern void L1D_cache_block_writeback_invalidate(unsigned int start,
76 unsigned int end);
77extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
78extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
79extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
80extern void L2_cache_block_writeback_invalidate(unsigned int start,
81 unsigned int end);
82extern void L2_cache_block_invalidate_nowait(unsigned int start,
83 unsigned int end);
84extern void L2_cache_block_writeback_nowait(unsigned int start,
85 unsigned int end);
86
87extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
88 unsigned int end);
89
90#endif /* _ASM_C6X_CACHE_H */
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