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Diffstat (limited to 'arch/cris/arch-v10/mm/init.c')
-rw-r--r--arch/cris/arch-v10/mm/init.c264
1 files changed, 264 insertions, 0 deletions
diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c
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index 000000000000..a9f975a9cfb5
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1/*
2 * linux/arch/cris/arch-v10/mm/init.c
3 *
4 */
5#include <linux/config.h>
6#include <linux/mmzone.h>
7#include <linux/init.h>
8#include <linux/bootmem.h>
9#include <linux/mm.h>
10#include <asm/pgtable.h>
11#include <asm/page.h>
12#include <asm/types.h>
13#include <asm/mmu.h>
14#include <asm/io.h>
15#include <asm/mmu_context.h>
16#include <asm/arch/svinto.h>
17
18extern void tlb_init(void);
19
20/*
21 * The kernel is already mapped with a kernel segment at kseg_c so
22 * we don't need to map it with a page table. However head.S also
23 * temporarily mapped it at kseg_4 so we should set up the ksegs again,
24 * clear the TLB and do some other paging setup stuff.
25 */
26
27void __init
28paging_init(void)
29{
30 int i;
31 unsigned long zones_size[MAX_NR_ZONES];
32
33 printk("Setting up paging and the MMU.\n");
34
35 /* clear out the init_mm.pgd that will contain the kernel's mappings */
36
37 for(i = 0; i < PTRS_PER_PGD; i++)
38 swapper_pg_dir[i] = __pgd(0);
39
40 /* make sure the current pgd table points to something sane
41 * (even if it is most probably not used until the next
42 * switch_mm)
43 */
44
45 current_pgd = init_mm.pgd;
46
47 /* initialise the TLB (tlb.c) */
48
49 tlb_init();
50
51 /* see README.mm for details on the KSEG setup */
52
53#ifdef CONFIG_CRIS_LOW_MAP
54 /* Etrax-100 LX version 1 has a bug so that we cannot map anything
55 * across the 0x80000000 boundary, so we need to shrink the user-virtual
56 * area to 0x50000000 instead of 0xb0000000 and map things slightly
57 * different. The unused areas are marked as paged so that we can catch
58 * freak kernel accesses there.
59 *
60 * The ARTPEC chip is mapped at 0xa so we pass that segment straight
61 * through. We cannot vremap it because the vmalloc area is below 0x8
62 * and Juliette needs an uncached area above 0x8.
63 *
64 * Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards.
65 * We map them straight over in LOW_MAP, but use vremap in LX version 2.
66 */
67
68#define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
69
70 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
71 IO_STATE(R_MMU_KSEG, seg_e, page ) |
72 IO_STATE(R_MMU_KSEG, seg_d, page ) |
73 IO_STATE(R_MMU_KSEG, seg_c, page ) |
74 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
75#ifdef CONFIG_JULIETTE
76 IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */
77#else
78 IO_STATE(R_MMU_KSEG, seg_a, page ) |
79#endif
80 IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
81 IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
82 IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
83 IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */
84 IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */
85 IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */
86 IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */
87 IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */
88 IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */
89 IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
90
91 *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
92 IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
93 IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
94 IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
95 IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
96#ifdef CONFIG_JULIETTE
97 IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) |
98#else
99 IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
100#endif
101 IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
102 IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
103
104 *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
105 IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
106 IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
107 IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
108 IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
109 IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
110 IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
111 IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
112#else
113 /* This code is for the corrected Etrax-100 LX version 2... */
114
115#define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
116
117 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */
118 IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */
119 IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
120 IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */
121 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
122 IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */
123 IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
124 IO_STATE(R_MMU_KSEG, seg_8, page ) |
125 IO_STATE(R_MMU_KSEG, seg_7, page ) |
126 IO_STATE(R_MMU_KSEG, seg_6, page ) |
127 IO_STATE(R_MMU_KSEG, seg_5, page ) |
128 IO_STATE(R_MMU_KSEG, seg_4, page ) |
129 IO_STATE(R_MMU_KSEG, seg_3, page ) |
130 IO_STATE(R_MMU_KSEG, seg_2, page ) |
131 IO_STATE(R_MMU_KSEG, seg_1, page ) |
132 IO_STATE(R_MMU_KSEG, seg_0, page ) );
133
134 *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
135 IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) |
136 IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
137 IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
138 IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
139 IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
140 IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
141 IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
142
143 *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
144 IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) |
145 IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
146 IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
147 IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
148 IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
149 IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
150 IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
151#endif
152
153 *R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) );
154
155 /* The MMU has been enabled ever since head.S but just to make
156 * it totally obvious we do it here as well.
157 */
158
159 *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) |
160 IO_STATE(R_MMU_CTRL, acc_excp, enable ) |
161 IO_STATE(R_MMU_CTRL, we_excp, enable ) );
162
163 *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable);
164
165 /*
166 * initialize the bad page table and bad page to point
167 * to a couple of allocated pages
168 */
169
170 empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
171 memset((void *)empty_zero_page, 0, PAGE_SIZE);
172
173 /* All pages are DMA'able in Etrax, so put all in the DMA'able zone */
174
175 zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
176
177 for (i = 1; i < MAX_NR_ZONES; i++)
178 zones_size[i] = 0;
179
180 /* Use free_area_init_node instead of free_area_init, because the former
181 * is designed for systems where the DRAM starts at an address substantially
182 * higher than 0, like us (we start at PAGE_OFFSET). This saves space in the
183 * mem_map page array.
184 */
185
186 free_area_init_node(0, &contig_page_data, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
187}
188
189/* Initialize remaps of some I/O-ports. It is important that this
190 * is called before any driver is initialized.
191 */
192
193static int
194__init init_ioremap(void)
195{
196
197 /* Give the external I/O-port addresses their values */
198
199#ifdef CONFIG_CRIS_LOW_MAP
200 /* Simply a linear map (see the KSEG map above in paging_init) */
201 port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START |
202 MEM_NON_CACHEABLE);
203 port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START |
204 MEM_NON_CACHEABLE);
205 port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START |
206 MEM_NON_CACHEABLE);
207#else
208 /* Note that nothing blows up just because we do this remapping
209 * it's ok even if the ports are not used or connected
210 * to anything (or connected to a non-I/O thing) */
211 port_cse1_addr = (volatile unsigned long *)
212 ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16);
213 port_csp0_addr = (volatile unsigned long *)
214 ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16);
215 port_csp4_addr = (volatile unsigned long *)
216 ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16);
217#endif
218 return 0;
219}
220
221__initcall(init_ioremap);
222
223/* Helper function for the two below */
224
225static inline void
226flush_etrax_cacherange(void *startadr, int length)
227{
228 /* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
229 * we can use to get fast dummy-reads of cachelines
230 */
231
232 volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
233 CACHED_BOOTROM);
234
235 length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */
236
237 while(length > 0) {
238 *flushadr; /* dummy read to flush */
239 flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */
240 length -= 32;
241 }
242}
243
244/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
245 * will occationally corrupt certain CPU writes if the DMA buffers
246 * happen to be hot in the cache.
247 *
248 * As a workaround, we have to flush the relevant parts of the cache
249 * before (re) inserting any receiving descriptor into the DMA HW.
250 */
251
252void
253prepare_rx_descriptor(struct etrax_dma_descr *desc)
254{
255 flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
256}
257
258/* Do the same thing but flush the entire cache */
259
260void
261flush_etrax_cache(void)
262{
263 flush_etrax_cacherange(0, 8192);
264}
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