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Diffstat (limited to 'arch/x86/include/asm/pgtable_types.h')
-rw-r--r--arch/x86/include/asm/pgtable_types.h29
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 79c91853e50e..8dba273da25a 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -89,7 +89,7 @@
89#define _PAGE_NX (_AT(pteval_t, 0)) 89#define _PAGE_NX (_AT(pteval_t, 0))
90#endif 90#endif
91 91
92#define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE) 92#define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
93 93
94#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \ 94#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
95 _PAGE_ACCESSED | _PAGE_DIRTY) 95 _PAGE_ACCESSED | _PAGE_DIRTY)
@@ -102,6 +102,33 @@
102 _PAGE_SOFT_DIRTY) 102 _PAGE_SOFT_DIRTY)
103#define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE) 103#define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)
104 104
105/* The ASID is the lower 12 bits of CR3 */
106#define X86_CR3_PCID_ASID_MASK (_AC((1<<12)-1,UL))
107
108/* Mask for all the PCID-related bits in CR3: */
109#define X86_CR3_PCID_MASK (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_MASK)
110#define X86_CR3_PCID_ASID_KERN (_AC(0x0,UL))
111
112#if defined(CONFIG_PAGE_TABLE_ISOLATION) && defined(CONFIG_X86_64)
113/* Let X86_CR3_PCID_ASID_USER be usable for the X86_CR3_PCID_NOFLUSH bit */
114#define X86_CR3_PCID_ASID_USER (_AC(0x80,UL))
115
116#define X86_CR3_PCID_KERN_FLUSH (X86_CR3_PCID_ASID_KERN)
117#define X86_CR3_PCID_USER_FLUSH (X86_CR3_PCID_ASID_USER)
118#define X86_CR3_PCID_KERN_NOFLUSH (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_KERN)
119#define X86_CR3_PCID_USER_NOFLUSH (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_USER)
120#else
121#define X86_CR3_PCID_ASID_USER (_AC(0x0,UL))
122/*
123 * PCIDs are unsupported on 32-bit and none of these bits can be
124 * set in CR3:
125 */
126#define X86_CR3_PCID_KERN_FLUSH (0)
127#define X86_CR3_PCID_USER_FLUSH (0)
128#define X86_CR3_PCID_KERN_NOFLUSH (0)
129#define X86_CR3_PCID_USER_NOFLUSH (0)
130#endif
131
105/* 132/*
106 * The cache modes defined here are used to translate between pure SW usage 133 * The cache modes defined here are used to translate between pure SW usage
107 * and the HW defined cache mode bits and/or PAT entries. 134 * and the HW defined cache mode bits and/or PAT entries.