diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v10_0.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 29 |
1 files changed, 8 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 5b261adb4b69..3a25da4a6e60 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | |||
@@ -1126,23 +1126,10 @@ static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) | |||
1126 | a.full = dfixed_const(available_bandwidth); | 1126 | a.full = dfixed_const(available_bandwidth); |
1127 | b.full = dfixed_const(wm->num_heads); | 1127 | b.full = dfixed_const(wm->num_heads); |
1128 | a.full = dfixed_div(a, b); | 1128 | a.full = dfixed_div(a, b); |
1129 | tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); | ||
1130 | tmp = min(dfixed_trunc(a), tmp); | ||
1129 | 1131 | ||
1130 | b.full = dfixed_const(mc_latency + 512); | 1132 | lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); |
1131 | c.full = dfixed_const(wm->disp_clk); | ||
1132 | b.full = dfixed_div(b, c); | ||
1133 | |||
1134 | c.full = dfixed_const(dmif_size); | ||
1135 | b.full = dfixed_div(c, b); | ||
1136 | |||
1137 | tmp = min(dfixed_trunc(a), dfixed_trunc(b)); | ||
1138 | |||
1139 | b.full = dfixed_const(1000); | ||
1140 | c.full = dfixed_const(wm->disp_clk); | ||
1141 | b.full = dfixed_div(c, b); | ||
1142 | c.full = dfixed_const(wm->bytes_per_pixel); | ||
1143 | b.full = dfixed_mul(b, c); | ||
1144 | |||
1145 | lb_fill_bw = min(tmp, dfixed_trunc(b)); | ||
1146 | 1133 | ||
1147 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | 1134 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); |
1148 | b.full = dfixed_const(1000); | 1135 | b.full = dfixed_const(1000); |
@@ -1250,14 +1237,14 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, | |||
1250 | { | 1237 | { |
1251 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; | 1238 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; |
1252 | struct dce10_wm_params wm_low, wm_high; | 1239 | struct dce10_wm_params wm_low, wm_high; |
1253 | u32 pixel_period; | 1240 | u32 active_time; |
1254 | u32 line_time = 0; | 1241 | u32 line_time = 0; |
1255 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | 1242 | u32 latency_watermark_a = 0, latency_watermark_b = 0; |
1256 | u32 tmp, wm_mask, lb_vblank_lead_lines = 0; | 1243 | u32 tmp, wm_mask, lb_vblank_lead_lines = 0; |
1257 | 1244 | ||
1258 | if (amdgpu_crtc->base.enabled && num_heads && mode) { | 1245 | if (amdgpu_crtc->base.enabled && num_heads && mode) { |
1259 | pixel_period = 1000000 / (u32)mode->clock; | 1246 | active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock; |
1260 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | 1247 | line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535); |
1261 | 1248 | ||
1262 | /* watermark for high clocks */ | 1249 | /* watermark for high clocks */ |
1263 | if (adev->pm.dpm_enabled) { | 1250 | if (adev->pm.dpm_enabled) { |
@@ -1272,7 +1259,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, | |||
1272 | 1259 | ||
1273 | wm_high.disp_clk = mode->clock; | 1260 | wm_high.disp_clk = mode->clock; |
1274 | wm_high.src_width = mode->crtc_hdisplay; | 1261 | wm_high.src_width = mode->crtc_hdisplay; |
1275 | wm_high.active_time = mode->crtc_hdisplay * pixel_period; | 1262 | wm_high.active_time = active_time; |
1276 | wm_high.blank_time = line_time - wm_high.active_time; | 1263 | wm_high.blank_time = line_time - wm_high.active_time; |
1277 | wm_high.interlaced = false; | 1264 | wm_high.interlaced = false; |
1278 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | 1265 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
@@ -1311,7 +1298,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, | |||
1311 | 1298 | ||
1312 | wm_low.disp_clk = mode->clock; | 1299 | wm_low.disp_clk = mode->clock; |
1313 | wm_low.src_width = mode->crtc_hdisplay; | 1300 | wm_low.src_width = mode->crtc_hdisplay; |
1314 | wm_low.active_time = mode->crtc_hdisplay * pixel_period; | 1301 | wm_low.active_time = active_time; |
1315 | wm_low.blank_time = line_time - wm_low.active_time; | 1302 | wm_low.blank_time = line_time - wm_low.active_time; |
1316 | wm_low.interlaced = false; | 1303 | wm_low.interlaced = false; |
1317 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | 1304 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |