1 files changed, 8 insertions, 21 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 9b4dcf76ce6c..d6e51d4b04f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1096,23 +1096,10 @@ static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
         a.full = dfixed_const(available_bandwidth);
         b.full = dfixed_const(wm->num_heads);
         a.full = dfixed_div(a, b);
+        tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
+        tmp = min(dfixed_trunc(a), tmp);
 
-        b.full = dfixed_const(mc_latency + 512);
-        c.full = dfixed_const(wm->disp_clk);
-        b.full = dfixed_div(b, c);
-
-        c.full = dfixed_const(dmif_size);
-        b.full = dfixed_div(c, b);
-
-        tmp = min(dfixed_trunc(a), dfixed_trunc(b));
-
-        b.full = dfixed_const(1000);
-        c.full = dfixed_const(wm->disp_clk);
-        b.full = dfixed_div(c, b);
-        c.full = dfixed_const(wm->bytes_per_pixel);
-        b.full = dfixed_mul(b, c);
-
-        lb_fill_bw = min(tmp, dfixed_trunc(b));
+        lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 
         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
         b.full = dfixed_const(1000);
@@ -1220,14 +1207,14 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 {
         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
         struct dce8_wm_params wm_low, wm_high;
-        u32 pixel_period;
+        u32 active_time;
         u32 line_time = 0;
         u32 latency_watermark_a = 0, latency_watermark_b = 0;
         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
         if (amdgpu_crtc->base.enabled && num_heads && mode) {
-                pixel_period = 1000000 / (u32)mode->clock;
-                line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+                active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+                line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
                 /* watermark for high clocks */
                 if (adev->pm.dpm_enabled) {
@@ -1242,7 +1229,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
                 wm_high.disp_clk = mode->clock;
                 wm_high.src_width = mode->crtc_hdisplay;
-                wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+                wm_high.active_time = active_time;
                 wm_high.blank_time = line_time - wm_high.active_time;
                 wm_high.interlaced = false;
                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1281,7 +1268,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
                 wm_low.disp_clk = mode->clock;
                 wm_low.src_width = mode->crtc_hdisplay;
-                wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+                wm_low.active_time = active_time;
                 wm_low.blank_time = line_time - wm_low.active_time;
                 wm_low.interlaced = false;
                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)