aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/usb/host/pci-quirks.c')
-rw-r--r--drivers/usb/host/pci-quirks.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 1fc6f478a02c..89e9494c3245 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -969,7 +969,7 @@ EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
969 * 969 *
970 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 970 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
971 * It signals to the BIOS that the OS wants control of the host controller, 971 * It signals to the BIOS that the OS wants control of the host controller,
972 * and then waits 5 seconds for the BIOS to hand over control. 972 * and then waits 1 second for the BIOS to hand over control.
973 * If we timeout, assume the BIOS is broken and take control anyway. 973 * If we timeout, assume the BIOS is broken and take control anyway.
974 */ 974 */
975static void quirk_usb_handoff_xhci(struct pci_dev *pdev) 975static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
@@ -1015,9 +1015,9 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
1015 if (val & XHCI_HC_BIOS_OWNED) { 1015 if (val & XHCI_HC_BIOS_OWNED) {
1016 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); 1016 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
1017 1017
1018 /* Wait for 5 seconds with 10 microsecond polling interval */ 1018 /* Wait for 1 second with 10 microsecond polling interval */
1019 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 1019 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
1020 0, 5000, 10); 1020 0, 1000000, 10);
1021 1021
1022 /* Assume a buggy BIOS and take HC ownership anyway */ 1022 /* Assume a buggy BIOS and take HC ownership anyway */
1023 if (timeout) { 1023 if (timeout) {
@@ -1046,7 +1046,7 @@ hc_init:
1046 * operational or runtime registers. Wait 5 seconds and no more. 1046 * operational or runtime registers. Wait 5 seconds and no more.
1047 */ 1047 */
1048 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 1048 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1049 5000, 10); 1049 5000000, 10);
1050 /* Assume a buggy HC and start HC initialization anyway */ 1050 /* Assume a buggy HC and start HC initialization anyway */
1051 if (timeout) { 1051 if (timeout) {
1052 val = readl(op_reg_base + XHCI_STS_OFFSET); 1052 val = readl(op_reg_base + XHCI_STS_OFFSET);