aboutsummaryrefslogtreecommitdiffstats
blob: 29705754460c7d3a95dbd8eba8635e35ff20ed15 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include "dra7.dtsi"

/ {
	compatible = "ti,dra722", "ti,dra72", "ti,dra7";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;

			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <2>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	aliases {
		rproc0 = &ipu1;
		rproc1 = &ipu2;
		rproc2 = &dsp1;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <&wakeupgen>;
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	};

	ocp {
		cal: cal@4845b000 {
			compatible = "ti,dra72-cal";
			ti,hwmods = "cal";
			reg = <0x4845B000 0x400>,
			      <0x4845B800 0x40>,
			      <0x4845B900 0x40>,
			      <0x4A002e94 0x4>;
			reg-names = "cal_top",
				    "cal_rx_core0",
				    "cal_rx_core1",
				    "camerrx_control";
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi2_0: port@0 {
					reg = <0>;
				};
				csi2_1: port@1 {
					reg = <1>;
				};
			};
		};
	};
};

&scm {
	dra72_vip_mux: pinmux@4a002e8c {
		compatible = "pinctrl-single";
		reg = <0xe8c 0x4>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x7f>;
	};
};

&dss {
	reg = <0x58000000 0x80>,
	      <0x58004054 0x4>,
	      <0x58004300 0x20>;
	reg-names = "dss", "pll1_clkctrl", "pll1";

	clocks = <&dss_dss_clk>,
		 <&dss_video1_clk>;
	clock-names = "fck", "video1_clk";
};

&mailbox3 {
	mbox_pru1_0: mbox_pru1_0 {
		ti,mbox-tx = <0 0 0>;
		ti,mbox-rx = <1 0 0>;
		status = "disabled";
	};
	mbox_pru1_1: mbox_pru1_1 {
		ti,mbox-tx = <2 0 0>;
		ti,mbox-rx = <3 0 0>;
		status = "disabled";
	};
};

&mailbox4 {
	mbox_pru2_0: mbox_pru2_0 {
		ti,mbox-tx = <0 0 0>;
		ti,mbox-rx = <1 0 0>;
		status = "disabled";
	};
	mbox_pru2_1: mbox_pru2_1 {
		ti,mbox-tx = <2 0 0>;
		ti,mbox-rx = <3 0 0>;
		status = "disabled";
	};
};

&mailbox5 {
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		ti,mbox-tx = <5 2 2>;
		ti,mbox-rx = <1 2 2>;
		status = "disabled";
	};
};

&mailbox6 {
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
};

&pcie1_rc {
	compatible = "ti,dra726-pcie-rc";
};

&pcie1_ep {
	compatible = "ti,dra726-pcie-ep";
};

&pcie2_rc {
	compatible = "ti,dra726-pcie-rc";
};