/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "TI DRA722";
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
aliases {
display0 = &tlc59108;
display1 = &hdmi0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1024 MB */
};
tpd12s015: encoder@0 {
compatible = "omapdss,ti,tpd12s015";
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint@0 {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint@0 {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
hdmi0: connector@0 {
compatible = "omapdss,hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ipu2_cma_pool: ipu2_cma@95800000 {
compatible = "shared-dma-pool";
reg = <0x95800000 0x3800000>;
reusable;
status = "okay";
};
dsp1_cma_pool: dsp1_cma@99000000 {
compatible = "shared-dma-pool";
reg = <0x99000000 0x4000000>;
reusable;
status = "okay";
};
ipu1_cma_pool: ipu1_cma@9d000000 {
compatible = "shared-dma-pool";
reg = <0x9d000000 0x2000000>;
reusable;
status = "okay";
};
};
mmc2_3v3: fixedregulator-mmc2 {
compatible = "regulator-fixed";
regulator-name = "mmc2_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&dra7_pmx_core {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
>;
};
uart1_pins: pinmix_uart1_pins {
pinctrl-single,pins = <
0x3e0 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd */
0x3e4 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_txd */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x408 (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_scl */
0x40c (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_sda */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 2 */
0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
0x198 (PIN_OFF_NONE)
0x19c (PIN_OFF_NONE)
0x1a0 (PIN_OFF_NONE)
0x1a4 (PIN_OFF_NONE)
0x1a8 (PIN_OFF_NONE)
0x1ac (PIN_OFF_NONE)
0x1b0 (PIN_OFF_NONE)
0x1b4 (PIN_OFF_NONE)
0x1b8 (PIN_OFF_NONE)
0x1bc (PIN_OFF_NONE)
0x1c0 (PIN_OFF_NONE)
0x1c4 (PIN_OFF_NONE)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
0x23c (PIN_OFF_NONE)
0x240 (PIN_OFF_NONE)
>;
};
tps65917_pins_default: tps65917_pins_default {
pinctrl-single,pins = <
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
nand_default: nand_default {
pinctrl-single,pins = <
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d4 (PIN_INPUT | MUX_MODE0) /* dcan1_tx */
0x418 (PIN_INPUT | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d4 (PIN_INPUT | MUX_MODE15) /* dcan1_tx.off */
0x418 (PIN_INPUT | MUX_MODE15) /* wakeup0.off */
>;
};
vout1_pins: pinmux_vout1_pins {
pinctrl-single,pins = <
0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
>;
};
hpd_pin: pinmux_hpd_pin {
pinctrl-single,pins = <
0x3b8 (PIN_INPUT | MUX_MODE14) /* gpio7_12 */
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&tps65917_pins_default>;
interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
&dra7_pmx_core 0x424>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1030000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo2_reg: ldo2 {
/* LDO2_OUT --> TP1017 (UNUSED) */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
pcf_lcd: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
/* TLC chip for LCD panel power and backlight */
tlc59108: tlc59108@40 {
compatible = "ti,tlc59108-lp101";
reg = <0x40>;
enable-gpio = <&pcf_lcd 13 GPIO_ACTIVE_HIGH>; /* P15, CON_LCD_PWR_DN */
port {
tlc_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
};
};
&dra7_pmx_core {
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
/*
* initial state is used here to keep the mdio interface
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
* VIN2_S0 driven high otherwise Ethernet stops working
*/
lines-initial-states = <0xff29>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
&dra7_pmx_core 0x3e0>;
status = "okay";
};
&mmc1 {
/* Using default configured pins */
status = "okay";
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 0>;
};
&mmc2 {
/* Using default configured pins */
status = "okay";
vmmc-supply = <&mmc2_3v3>;
bus-width = <8>;
ti,non-removable;
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
&cpu0 {
cpu0-voltdm = <&voltdm_mpu>;
voltage-tolerance = <1>;
};
&voltdm_mpu {
vdd-supply = <&smps1_reg>;
};
&voltdm_core {
vdd-supply = <&smps2_reg>;
};
&voltdm_dspeve {
vdd-supply = <&smps3_reg>;
};
&voltdm_gpu {
vdd-supply = <&smps3_reg>;
};
&voltdm_ivahd {
vdd-supply = <&smps3_reg>;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_default>;
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
reg = <0 0 4>; /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&vout1_pins>;
vdda-supply = <&ldo5_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port {
reg = <0>;
dpi_out: endpoint {
remote-endpoint = <&tlc_in>;
data-lines = <24>;
};
};
};
};
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan1_pins_default>;
pinctrl-1 = <&dcan1_pins_sleep>;
};
&hdmi {
status = "ok";
vdda-supply = <&ldo3_reg>;
pinctrl-names = "default";
pinctrl-0 = <&hpd_pin &i2c2_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&mailbox5 {
status = "okay";
mbox_ipu1_legacy: mbox_ipu1_legacy {
status = "okay";
};
mbox_dsp1_legacy: mbox_dsp1_legacy {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_legacy: mbox_ipu2_legacy {
status = "okay";
};
};
&mmu0_dsp1 {
status = "okay";
};
&mmu1_dsp1 {
status = "okay";
};
&mmu_ipu1 {
status = "okay";
};
&mmu_ipu2 {
status = "okay";
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_cma_pool>;
mboxes = <&mailbox6 &mbox_ipu2_legacy>;
timers = <&timer3>;
watchdog-timers = <&timer4>, <&timer9>;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_cma_pool>;
mboxes = <&mailbox5 &mbox_ipu1_legacy>;
timers = <&timer11>;
};
&dsp1 {
status = "okay";
memory-region = <&dsp1_cma_pool>;
mboxes = <&mailbox5 &mbox_dsp1_legacy>;
timers = <&timer5>;
};
